hw/net/fsl_etsec/etsec.h

   1 /*
   2  * QEMU Freescale eTSEC Emulator
   3  *
   4  * Copyright (c) 2011-2013 AdaCore
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef ETSEC_H
  26 #define ETSEC_H
  27
  28 #include "hw/qdev.h"
  29 #include "hw/sysbus.h"
  30 #include "net/net.h"
  31 #include "hw/ptimer.h"
  32
  33 /* Buffer Descriptors */
  34
  35 typedef struct eTSEC_rxtx_bd {
  36     uint16_t flags;
  37     uint16_t length;
  38     uint32_t bufptr;
  39 } eTSEC_rxtx_bd;
  40
  41 #define BD_WRAP       (1 << 13)
  42 #define BD_INTERRUPT  (1 << 12)
  43 #define BD_LAST       (1 << 11)
  44
  45 #define BD_TX_READY     (1 << 15)
  46 #define BD_TX_PADCRC    (1 << 14)
  47 #define BD_TX_TC        (1 << 10)
  48 #define BD_TX_PREDEF    (1 << 9)
  49 #define BD_TX_HFELC     (1 << 7)
  50 #define BD_TX_CFRL      (1 << 6)
  51 #define BD_TX_RC_MASK   0xF
  52 #define BD_TX_RC_OFFSET 0x2
  53 #define BD_TX_TOEUN     (1 << 1)
  54 #define BD_TX_TR        (1 << 0)
  55
  56 #define BD_RX_EMPTY     (1 << 15)
  57 #define BD_RX_RO1       (1 << 14)
  58 #define BD_RX_FIRST     (1 << 10)
  59 #define BD_RX_MISS      (1 << 8)
  60 #define BD_RX_BROADCAST (1 << 7)
  61 #define BD_RX_MULTICAST (1 << 6)
  62 #define BD_RX_LG        (1 << 5)
  63 #define BD_RX_NO        (1 << 4)
  64 #define BD_RX_SH        (1 << 3)
  65 #define BD_RX_CR        (1 << 2)
  66 #define BD_RX_OV        (1 << 1)
  67 #define BD_RX_TR        (1 << 0)
  68
  69 /* Tx FCB flags */
  70 #define FCB_TX_VLN     (1 << 7)
  71 #define FCB_TX_IP      (1 << 6)
  72 #define FCB_TX_IP6     (1 << 5)
  73 #define FCB_TX_TUP     (1 << 4)
  74 #define FCB_TX_UDP     (1 << 3)
  75 #define FCB_TX_CIP     (1 << 2)
  76 #define FCB_TX_CTU     (1 << 1)
  77 #define FCB_TX_NPH     (1 << 0)
  78
  79 /* PHY Status Register */
  80 #define MII_SR_EXTENDED_CAPS     0x0001    /* Extended register capabilities */
  81 #define MII_SR_JABBER_DETECT     0x0002    /* Jabber Detected */
  82 #define MII_SR_LINK_STATUS       0x0004    /* Link Status 1 = link */
  83 #define MII_SR_AUTONEG_CAPS      0x0008    /* Auto Neg Capable */
  84 #define MII_SR_REMOTE_FAULT      0x0010    /* Remote Fault Detect */
  85 #define MII_SR_AUTONEG_COMPLETE  0x0020    /* Auto Neg Complete */
  86 #define MII_SR_PREAMBLE_SUPPRESS 0x0040    /* Preamble may be suppressed */
  87 #define MII_SR_EXTENDED_STATUS   0x0100    /* Ext. status info in Reg 0x0F */
  88 #define MII_SR_100T2_HD_CAPS     0x0200    /* 100T2 Half Duplex Capable */
  89 #define MII_SR_100T2_FD_CAPS     0x0400    /* 100T2 Full Duplex Capable */
  90 #define MII_SR_10T_HD_CAPS       0x0800    /* 10T   Half Duplex Capable */
  91 #define MII_SR_10T_FD_CAPS       0x1000    /* 10T   Full Duplex Capable */
  92 #define MII_SR_100X_HD_CAPS      0x2000    /* 100X  Half Duplex Capable */
  93 #define MII_SR_100X_FD_CAPS      0x4000    /* 100X  Full Duplex Capable */
  94 #define MII_SR_100T4_CAPS        0x8000    /* 100T4 Capable */
  95
  96 /* eTSEC */
  97
  98 /* Number of register in the device */
  99 #define ETSEC_REG_NUMBER 1024
 100
 101 typedef struct eTSEC_Register {
 102     const char *name;
 103     const char *desc;
 104     uint32_t    access;
 105     uint32_t    value;
 106 } eTSEC_Register;
 107
 108 typedef struct eTSEC {
 109     SysBusDevice  busdev;
 110
 111     MemoryRegion  io_area;
 112
 113     eTSEC_Register regs[ETSEC_REG_NUMBER];
 114
 115     NICState *nic;
 116     NICConf   conf;
 117
 118     /* Tx */
 119
 120     uint8_t       *tx_buffer;
 121     uint32_t       tx_buffer_len;
 122     eTSEC_rxtx_bd  first_bd;
 123
 124     /* Rx */
 125
 126     uint8_t       *rx_buffer;
 127     uint32_t       rx_buffer_len;
 128     uint32_t       rx_remaining_data;
 129     uint8_t        rx_first_in_frame;
 130     uint8_t        rx_fcb_size;
 131     eTSEC_rxtx_bd  rx_first_bd;
 132     uint8_t        rx_fcb[10];
 133     uint32_t       rx_padding;
 134
 135     /* IRQs */
 136     qemu_irq     tx_irq;
 137     qemu_irq     rx_irq;
 138     qemu_irq     err_irq;
 139
 140
 141     uint16_t phy_status;
 142     uint16_t phy_control;
 143
 144     /* Polling */
 145     QEMUBH *bh;
 146     struct ptimer_state *ptimer;
 147
 148     /* Whether we should flush the rx queue when buffer becomes available. */
 149     bool need_flush;
 150 } eTSEC;
 151
 152 #define TYPE_ETSEC_COMMON "eTSEC"
 153 #define ETSEC_COMMON(obj) \
 154      OBJECT_CHECK(eTSEC, (obj), TYPE_ETSEC_COMMON)
 155
 156 #define eTSEC_TRANSMIT 1
 157 #define eTSEC_RECEIVE  2
 158
 159 DeviceState *etsec_create(hwaddr        base,
 160                           MemoryRegion *mr,
 161                           NICInfo      *nd,
 162                           qemu_irq      tx_irq,
 163                           qemu_irq      rx_irq,
 164                           qemu_irq      err_irq);
 165
 166 void etsec_update_irq(eTSEC *etsec);
 167
 168 void etsec_walk_tx_ring(eTSEC *etsec, int ring_nbr);
 169 void etsec_walk_rx_ring(eTSEC *etsec, int ring_nbr);
 170 ssize_t etsec_rx_ring_write(eTSEC *etsec, const uint8_t *buf, size_t size);
 171
 172 void etsec_write_miim(eTSEC          *etsec,
 173                       eTSEC_Register *reg,
 174                       uint32_t        reg_index,
 175                       uint32_t        value);
 176
 177 void etsec_miim_link_status(eTSEC *etsec, NetClientState *nc);
 178
 179 #endif /* ETSEC_H */