hw/arm/xlnx-zynqmp.c

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu-common.h"
  21 #include "cpu.h"
  22 #include "hw/arm/xlnx-zynqmp.h"
  23 #include "hw/intc/arm_gic_common.h"
  24 #include "exec/address-spaces.h"
  25 #include "sysemu/kvm.h"
  26 #include "kvm_arm.h"
  27
  28 #define GIC_NUM_SPI_INTR 160
  29
  30 #define ARM_PHYS_TIMER_PPI  30
  31 #define ARM_VIRT_TIMER_PPI  27
  32 #define ARM_HYP_TIMER_PPI   26
  33 #define ARM_SEC_TIMER_PPI   29
  34 #define GIC_MAINTENANCE_PPI 25
  35
  36 #define GEM_REVISION        0x40070106
  37
  38 #define GIC_BASE_ADDR       0xf9000000
  39 #define GIC_DIST_ADDR       0xf9010000
  40 #define GIC_CPU_ADDR        0xf9020000
  41 #define GIC_VIFACE_ADDR     0xf9040000
  42 #define GIC_VCPU_ADDR       0xf9060000
  43
  44 #define SATA_INTR           133
  45 #define SATA_ADDR           0xFD0C0000
  46 #define SATA_NUM_PORTS      2
  47
  48 #define QSPI_ADDR           0xff0f0000
  49 #define LQSPI_ADDR          0xc0000000
  50 #define QSPI_IRQ            15
  51
  52 #define DP_ADDR             0xfd4a0000
  53 #define DP_IRQ              113
  54
  55 #define DPDMA_ADDR          0xfd4c0000
  56 #define DPDMA_IRQ           116
  57
  58 #define IPI_ADDR            0xFF300000
  59 #define IPI_IRQ             64
  60
  61 #define RTC_ADDR            0xffa60000
  62 #define RTC_IRQ             26
  63
  64 #define SDHCI_CAPABILITIES  0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
  65
  66 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  67     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  68 };
  69
  70 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  71     57, 59, 61, 63,
  72 };
  73
  74 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  75     0xFF000000, 0xFF010000,
  76 };
  77
  78 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  79     21, 22,
  80 };
  81
  82 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
  83     0xFF160000, 0xFF170000,
  84 };
  85
  86 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
  87     48, 49,
  88 };
  89
  90 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
  91     0xFF040000, 0xFF050000,
  92 };
  93
  94 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
  95     19, 20,
  96 };
  97
  98 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
  99     0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
 100     0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
 101 };
 102
 103 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
 104     124, 125, 126, 127, 128, 129, 130, 131
 105 };
 106
 107 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
 108     0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
 109     0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
 110 };
 111
 112 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
 113     77, 78, 79, 80, 81, 82, 83, 84
 114 };
 115
 116 typedef struct XlnxZynqMPGICRegion {
 117     int region_index;
 118     uint32_t address;
 119     uint32_t offset;
 120     bool virt;
 121 } XlnxZynqMPGICRegion;
 122
 123 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
 124     /* Distributor */
 125     {
 126         .region_index = 0,
 127         .address = GIC_DIST_ADDR,
 128         .offset = 0,
 129         .virt = false
 130     },
 131
 132     /* CPU interface */
 133     {
 134         .region_index = 1,
 135         .address = GIC_CPU_ADDR,
 136         .offset = 0,
 137         .virt = false
 138     },
 139     {
 140         .region_index = 1,
 141         .address = GIC_CPU_ADDR + 0x10000,
 142         .offset = 0x1000,
 143         .virt = false
 144     },
 145
 146     /* Virtual interface */
 147     {
 148         .region_index = 2,
 149         .address = GIC_VIFACE_ADDR,
 150         .offset = 0,
 151         .virt = true
 152     },
 153
 154     /* Virtual CPU interface */
 155     {
 156         .region_index = 3,
 157         .address = GIC_VCPU_ADDR,
 158         .offset = 0,
 159         .virt = true
 160     },
 161     {
 162         .region_index = 3,
 163         .address = GIC_VCPU_ADDR + 0x10000,
 164         .offset = 0x1000,
 165         .virt = true
 166     },
 167 };
 168
 169 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
 170 {
 171     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
 172 }
 173
 174 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
 175                                    Error **errp)
 176 {
 177     Error *err = NULL;
 178     int i;
 179     int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS);
 180
 181     for (i = 0; i < num_rpus; i++) {
 182         char *name;
 183
 184         object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
 185                           "cortex-r5f-" TYPE_ARM_CPU);
 186         object_property_add_child(OBJECT(s), "rpu-cpu[*]",
 187                                   OBJECT(&s->rpu_cpu[i]), &error_abort);
 188
 189         name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
 190         if (strcmp(name, boot_cpu)) {
 191             /* Secondary CPUs start in PSCI powered-down state */
 192             object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
 193                                      "start-powered-off", &error_abort);
 194         } else {
 195             s->boot_cpu_ptr = &s->rpu_cpu[i];
 196         }
 197         g_free(name);
 198
 199         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
 200                                  &error_abort);
 201         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
 202                                  &err);
 203         if (err) {
 204             error_propagate(errp, err);
 205             return;
 206         }
 207     }
 208 }
 209
 210 static void xlnx_zynqmp_init(Object *obj)
 211 {
 212     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
 213     int i;
 214     int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 215
 216     for (i = 0; i < num_apus; i++) {
 217         object_initialize_child(obj, "apu-cpu[*]", &s->apu_cpu[i],
 218                                 sizeof(s->apu_cpu[i]),
 219                                 "cortex-a53-" TYPE_ARM_CPU, &error_abort, NULL);
 220     }
 221
 222     sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
 223                           gic_class_name());
 224
 225     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 226         sysbus_init_child_obj(obj, "gem[*]", &s->gem[i], sizeof(s->gem[i]),
 227                               TYPE_CADENCE_GEM);
 228     }
 229
 230     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 231         sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
 232                               TYPE_CADENCE_UART);
 233     }
 234
 235     sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata),
 236                           TYPE_SYSBUS_AHCI);
 237
 238     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 239         sysbus_init_child_obj(obj, "sdhci[*]", &s->sdhci[i],
 240                               sizeof(s->sdhci[i]), TYPE_SYSBUS_SDHCI);
 241     }
 242
 243     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 244         sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
 245                               TYPE_XILINX_SPIPS);
 246     }
 247
 248     sysbus_init_child_obj(obj, "qspi", &s->qspi, sizeof(s->qspi),
 249                           TYPE_XLNX_ZYNQMP_QSPIPS);
 250
 251     sysbus_init_child_obj(obj, "xxxdp", &s->dp, sizeof(s->dp), TYPE_XLNX_DP);
 252
 253     sysbus_init_child_obj(obj, "dp-dma", &s->dpdma, sizeof(s->dpdma),
 254                           TYPE_XLNX_DPDMA);
 255
 256     sysbus_init_child_obj(obj, "ipi", &s->ipi, sizeof(s->ipi),
 257                           TYPE_XLNX_ZYNQMP_IPI);
 258
 259     sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
 260                           TYPE_XLNX_ZYNQMP_RTC);
 261
 262     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
 263         sysbus_init_child_obj(obj, "gdma[*]", &s->gdma[i], sizeof(s->gdma[i]),
 264                               TYPE_XLNX_ZDMA);
 265     }
 266
 267     for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
 268         sysbus_init_child_obj(obj, "adma[*]", &s->adma[i], sizeof(s->adma[i]),
 269                               TYPE_XLNX_ZDMA);
 270     }
 271 }
 272
 273 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 274 {
 275     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
 276     MemoryRegion *system_memory = get_system_memory();
 277     uint8_t i;
 278     uint64_t ram_size;
 279     int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 280     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
 281     ram_addr_t ddr_low_size, ddr_high_size;
 282     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
 283     Error *err = NULL;
 284
 285     ram_size = memory_region_size(s->ddr_ram);
 286
 287     /* Create the DDR Memory Regions. User friendly checks should happen at
 288      * the board level
 289      */
 290     if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
 291         /* The RAM size is above the maximum available for the low DDR.
 292          * Create the high DDR memory region as well.
 293          */
 294         assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
 295         ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 296         ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 297
 298         memory_region_init_alias(&s->ddr_ram_high, NULL,
 299                                  "ddr-ram-high", s->ddr_ram,
 300                                   ddr_low_size, ddr_high_size);
 301         memory_region_add_subregion(get_system_memory(),
 302                                     XLNX_ZYNQMP_HIGH_RAM_START,
 303                                     &s->ddr_ram_high);
 304     } else {
 305         /* RAM must be non-zero */
 306         assert(ram_size);
 307         ddr_low_size = ram_size;
 308     }
 309
 310     memory_region_init_alias(&s->ddr_ram_low, NULL,
 311                              "ddr-ram-low", s->ddr_ram,
 312                               0, ddr_low_size);
 313     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
 314
 315     /* Create the four OCM banks */
 316     for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
 317         char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
 318
 319         memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
 320                                XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
 321         memory_region_add_subregion(get_system_memory(),
 322                                     XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
 323                                         i * XLNX_ZYNQMP_OCM_RAM_SIZE,
 324                                     &s->ocm_ram[i]);
 325
 326         g_free(ocm_name);
 327     }
 328
 329     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
 330     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
 331     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
 332     qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
 333     qdev_prop_set_bit(DEVICE(&s->gic),
 334                       "has-virtualization-extensions", s->virt);
 335
 336     /* Realize APUs before realizing the GIC. KVM requires this.  */
 337     for (i = 0; i < num_apus; i++) {
 338         char *name;
 339
 340         object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
 341                                 "psci-conduit", &error_abort);
 342
 343         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
 344         if (strcmp(name, boot_cpu)) {
 345             /* Secondary CPUs start in PSCI powered-down state */
 346             object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
 347                                      "start-powered-off", &error_abort);
 348         } else {
 349             s->boot_cpu_ptr = &s->apu_cpu[i];
 350         }
 351         g_free(name);
 352
 353         object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 354                                  s->secure, "has_el3", NULL);
 355         object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 356                                  s->virt, "has_el2", NULL);
 357         object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
 358                                 "reset-cbar", &error_abort);
 359         object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus,
 360                                 "core-count", &error_abort);
 361         object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
 362                                  &err);
 363         if (err) {
 364             error_propagate(errp, err);
 365             return;
 366         }
 367     }
 368
 369     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
 370     if (err) {
 371         error_propagate(errp, err);
 372         return;
 373     }
 374
 375     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
 376     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
 377         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
 378         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
 379         MemoryRegion *mr;
 380         uint32_t addr = r->address;
 381         int j;
 382
 383         if (r->virt && !s->virt) {
 384             continue;
 385         }
 386
 387         mr = sysbus_mmio_get_region(gic, r->region_index);
 388         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
 389             MemoryRegion *alias = &s->gic_mr[i][j];
 390
 391             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
 392                                      r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE);
 393             memory_region_add_subregion(system_memory, addr, alias);
 394
 395             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
 396         }
 397     }
 398
 399     for (i = 0; i < num_apus; i++) {
 400         qemu_irq irq;
 401
 402         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
 403                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 404                                             ARM_CPU_IRQ));
 405         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus,
 406                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 407                                             ARM_CPU_FIQ));
 408         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2,
 409                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 410                                             ARM_CPU_VIRQ));
 411         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3,
 412                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 413                                             ARM_CPU_VFIQ));
 414         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 415                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
 416         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq);
 417         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 418                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
 419         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq);
 420         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 421                                arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
 422         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq);
 423         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 424                                arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
 425         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq);
 426
 427         if (s->virt) {
 428             irq = qdev_get_gpio_in(DEVICE(&s->gic),
 429                                    arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI));
 430             sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq);
 431         }
 432     }
 433
 434     if (s->has_rpu) {
 435         info_report("The 'has_rpu' property is no longer required, to use the "
 436                     "RPUs just use -smp 6.");
 437     }
 438
 439     xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
 440     if (err) {
 441         error_propagate(errp, err);
 442         return;
 443     }
 444
 445     if (!s->boot_cpu_ptr) {
 446         error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
 447         return;
 448     }
 449
 450     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
 451         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 452     }
 453
 454     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 455         NICInfo *nd = &nd_table[i];
 456
 457         if (nd->used) {
 458             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 459             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
 460         }
 461         object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
 462                                 &error_abort);
 463         object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
 464                                 &error_abort);
 465         object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
 466         if (err) {
 467             error_propagate(errp, err);
 468             return;
 469         }
 470         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
 471         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
 472                            gic_spi[gem_intr[i]]);
 473     }
 474
 475     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 476         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 477         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 478         if (err) {
 479             error_propagate(errp, err);
 480             return;
 481         }
 482         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
 483         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 484                            gic_spi[uart_intr[i]]);
 485     }
 486
 487     object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
 488                             &error_abort);
 489     object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
 490     if (err) {
 491         error_propagate(errp, err);
 492         return;
 493     }
 494
 495     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
 496     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
 497
 498     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 499         char *bus_name = g_strdup_printf("sd-bus%d", i);
 500         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
 501         Object *sdhci = OBJECT(&s->sdhci[i]);
 502
 503         /* Compatible with:
 504          * - SD Host Controller Specification Version 3.00
 505          * - SDIO Specification Version 3.0
 506          * - eMMC Specification Version 4.51
 507          */
 508         object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
 509         object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
 510         object_property_set_uint(sdhci, UHS_I, "uhs", &err);
 511         object_property_set_bool(sdhci, true, "realized", &err);
 512         if (err) {
 513             error_propagate(errp, err);
 514             return;
 515         }
 516         sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
 517         sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
 518
 519         /* Alias controller SD bus to the SoC itself */
 520         object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus",
 521                                   &error_abort);
 522         g_free(bus_name);
 523     }
 524
 525     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 526         gchar *bus_name;
 527
 528         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 529
 530         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
 531         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 532                            gic_spi[spi_intr[i]]);
 533
 534         /* Alias controller SPI bus to the SoC itself */
 535         bus_name = g_strdup_printf("spi%d", i);
 536         object_property_add_alias(OBJECT(s), bus_name,
 537                                   OBJECT(&s->spi[i]), "spi0",
 538                                   &error_abort);
 539         g_free(bus_name);
 540     }
 541
 542     object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
 543     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
 544     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
 545     sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
 546
 547     for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
 548         gchar *bus_name;
 549         gchar *target_bus;
 550
 551         /* Alias controller SPI bus to the SoC itself */
 552         bus_name = g_strdup_printf("qspi%d", i);
 553         target_bus = g_strdup_printf("spi%d", i);
 554         object_property_add_alias(OBJECT(s), bus_name,
 555                                   OBJECT(&s->qspi), target_bus,
 556                                   &error_abort);
 557         g_free(bus_name);
 558         g_free(target_bus);
 559     }
 560
 561     object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
 562     if (err) {
 563         error_propagate(errp, err);
 564         return;
 565     }
 566     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
 567     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
 568
 569     object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
 570     if (err) {
 571         error_propagate(errp, err);
 572         return;
 573     }
 574     object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
 575                              &error_abort);
 576     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
 577     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
 578
 579     object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err);
 580     if (err) {
 581         error_propagate(errp, err);
 582         return;
 583     }
 584     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
 585     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
 586
 587     object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
 588     if (err) {
 589         error_propagate(errp, err);
 590         return;
 591     }
 592     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
 593     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
 594
 595     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
 596         object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err);
 597         object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err);
 598         if (err) {
 599             error_propagate(errp, err);
 600             return;
 601         }
 602
 603         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
 604         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
 605                            gic_spi[gdma_ch_intr[i]]);
 606     }
 607
 608     for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
 609         object_property_set_bool(OBJECT(&s->adma[i]), true, "realized", &err);
 610         if (err) {
 611             error_propagate(errp, err);
 612             return;
 613         }
 614
 615         sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
 616         sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
 617                            gic_spi[adma_ch_intr[i]]);
 618     }
 619 }
 620
 621 static Property xlnx_zynqmp_props[] = {
 622     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
 623     DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
 624     DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
 625     DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
 626     DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
 627                      MemoryRegion *),
 628     DEFINE_PROP_END_OF_LIST()
 629 };
 630
 631 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 632 {
 633     DeviceClass *dc = DEVICE_CLASS(oc);
 634
 635     dc->props = xlnx_zynqmp_props;
 636     dc->realize = xlnx_zynqmp_realize;
 637     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 638     dc->user_creatable = false;
 639 }
 640
 641 static const TypeInfo xlnx_zynqmp_type_info = {
 642     .name = TYPE_XLNX_ZYNQMP,
 643     .parent = TYPE_DEVICE,
 644     .instance_size = sizeof(XlnxZynqMPState),
 645     .instance_init = xlnx_zynqmp_init,
 646     .class_init = xlnx_zynqmp_class_init,
 647 };
 648
 649 static void xlnx_zynqmp_register_types(void)
 650 {
 651     type_register_static(&xlnx_zynqmp_type_info);
 652 }
 653
 654 type_init(xlnx_zynqmp_register_types)