hw/arm/versatilepb.c

   1 /*
   2  * ARM Versatile Platform/Application Baseboard System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw/sysbus.h"
  11 #include "hw/arm/arm.h"
  12 #include "hw/devices.h"
  13 #include "net/net.h"
  14 #include "sysemu/sysemu.h"
  15 #include "hw/pci/pci.h"
  16 #include "hw/i2c/i2c.h"
  17 #include "hw/boards.h"
  18 #include "sysemu/block-backend.h"
  19 #include "exec/address-spaces.h"
  20 #include "hw/block/flash.h"
  21 #include "qemu/error-report.h"
  22
  23 #define VERSATILE_FLASH_ADDR 0x34000000
  24 #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)
  25 #define VERSATILE_FLASH_SECT_SIZE (256 * 1024)
  26
  27 /* Primary interrupt controller.  */
  28
  29 #define TYPE_VERSATILE_PB_SIC "versatilepb_sic"
  30 #define VERSATILE_PB_SIC(obj) \
  31     OBJECT_CHECK(vpb_sic_state, (obj), TYPE_VERSATILE_PB_SIC)
  32
  33 typedef struct vpb_sic_state {
  34     SysBusDevice parent_obj;
  35
  36     MemoryRegion iomem;
  37     uint32_t level;
  38     uint32_t mask;
  39     uint32_t pic_enable;
  40     qemu_irq parent[32];
  41     int irq;
  42 } vpb_sic_state;
  43
  44 static const VMStateDescription vmstate_vpb_sic = {
  45     .name = "versatilepb_sic",
  46     .version_id = 1,
  47     .minimum_version_id = 1,
  48     .fields = (VMStateField[]) {
  49         VMSTATE_UINT32(level, vpb_sic_state),
  50         VMSTATE_UINT32(mask, vpb_sic_state),
  51         VMSTATE_UINT32(pic_enable, vpb_sic_state),
  52         VMSTATE_END_OF_LIST()
  53     }
  54 };
  55
  56 static void vpb_sic_update(vpb_sic_state *s)
  57 {
  58     uint32_t flags;
  59
  60     flags = s->level & s->mask;
  61     qemu_set_irq(s->parent[s->irq], flags != 0);
  62 }
  63
  64 static void vpb_sic_update_pic(vpb_sic_state *s)
  65 {
  66     int i;
  67     uint32_t mask;
  68
  69     for (i = 21; i <= 30; i++) {
  70         mask = 1u << i;
  71         if (!(s->pic_enable & mask))
  72             continue;
  73         qemu_set_irq(s->parent[i], (s->level & mask) != 0);
  74     }
  75 }
  76
  77 static void vpb_sic_set_irq(void *opaque, int irq, int level)
  78 {
  79     vpb_sic_state *s = (vpb_sic_state *)opaque;
  80     if (level)
  81         s->level |= 1u << irq;
  82     else
  83         s->level &= ~(1u << irq);
  84     if (s->pic_enable & (1u << irq))
  85         qemu_set_irq(s->parent[irq], level);
  86     vpb_sic_update(s);
  87 }
  88
  89 static uint64_t vpb_sic_read(void *opaque, hwaddr offset,
  90                              unsigned size)
  91 {
  92     vpb_sic_state *s = (vpb_sic_state *)opaque;
  93
  94     switch (offset >> 2) {
  95     case 0: /* STATUS */
  96         return s->level & s->mask;
  97     case 1: /* RAWSTAT */
  98         return s->level;
  99     case 2: /* ENABLE */
 100         return s->mask;
 101     case 4: /* SOFTINT */
 102         return s->level & 1;
 103     case 8: /* PICENABLE */
 104         return s->pic_enable;
 105     default:
 106         printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
 107         return 0;
 108     }
 109 }
 110
 111 static void vpb_sic_write(void *opaque, hwaddr offset,
 112                           uint64_t value, unsigned size)
 113 {
 114     vpb_sic_state *s = (vpb_sic_state *)opaque;
 115
 116     switch (offset >> 2) {
 117     case 2: /* ENSET */
 118         s->mask |= value;
 119         break;
 120     case 3: /* ENCLR */
 121         s->mask &= ~value;
 122         break;
 123     case 4: /* SOFTINTSET */
 124         if (value)
 125             s->mask |= 1;
 126         break;
 127     case 5: /* SOFTINTCLR */
 128         if (value)
 129             s->mask &= ~1u;
 130         break;
 131     case 8: /* PICENSET */
 132         s->pic_enable |= (value & 0x7fe00000);
 133         vpb_sic_update_pic(s);
 134         break;
 135     case 9: /* PICENCLR */
 136         s->pic_enable &= ~value;
 137         vpb_sic_update_pic(s);
 138         break;
 139     default:
 140         printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
 141         return;
 142     }
 143     vpb_sic_update(s);
 144 }
 145
 146 static const MemoryRegionOps vpb_sic_ops = {
 147     .read = vpb_sic_read,
 148     .write = vpb_sic_write,
 149     .endianness = DEVICE_NATIVE_ENDIAN,
 150 };
 151
 152 static int vpb_sic_init(SysBusDevice *sbd)
 153 {
 154     DeviceState *dev = DEVICE(sbd);
 155     vpb_sic_state *s = VERSATILE_PB_SIC(dev);
 156     int i;
 157
 158     qdev_init_gpio_in(dev, vpb_sic_set_irq, 32);
 159     for (i = 0; i < 32; i++) {
 160         sysbus_init_irq(sbd, &s->parent[i]);
 161     }
 162     s->irq = 31;
 163     memory_region_init_io(&s->iomem, OBJECT(s), &vpb_sic_ops, s,
 164                           "vpb-sic", 0x1000);
 165     sysbus_init_mmio(sbd, &s->iomem);
 166     return 0;
 167 }
 168
 169 /* Board init.  */
 170
 171 /* The AB and PB boards both use the same core, just with different
 172    peripherals and expansion busses.  For now we emulate a subset of the
 173    PB peripherals and just change the board ID.  */
 174
 175 static struct arm_boot_info versatile_binfo;
 176
 177 static void versatile_init(MachineState *machine, int board_id)
 178 {
 179     ObjectClass *cpu_oc;
 180     Object *cpuobj;
 181     ARMCPU *cpu;
 182     MemoryRegion *sysmem = get_system_memory();
 183     MemoryRegion *ram = g_new(MemoryRegion, 1);
 184     qemu_irq pic[32];
 185     qemu_irq sic[32];
 186     DeviceState *dev, *sysctl;
 187     SysBusDevice *busdev;
 188     DeviceState *pl041;
 189     PCIBus *pci_bus;
 190     NICInfo *nd;
 191     I2CBus *i2c;
 192     int n;
 193     int done_smc = 0;
 194     DriveInfo *dinfo;
 195     Error *err = NULL;
 196
 197     if (!machine->cpu_model) {
 198         machine->cpu_model = "arm926";
 199     }
 200
 201     cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);
 202     if (!cpu_oc) {
 203         fprintf(stderr, "Unable to find CPU definition\n");
 204         exit(1);
 205     }
 206
 207     cpuobj = object_new(object_class_get_name(cpu_oc));
 208
 209     /* By default ARM1176 CPUs have EL3 enabled.  This board does not
 210      * currently support EL3 so the CPU EL3 property is disabled before
 211      * realization.
 212      */
 213     if (object_property_find(cpuobj, "has_el3", NULL)) {
 214         object_property_set_bool(cpuobj, false, "has_el3", &err);
 215         if (err) {
 216             error_report_err(err);
 217             exit(1);
 218         }
 219     }
 220
 221     object_property_set_bool(cpuobj, true, "realized", &err);
 222     if (err) {
 223         error_report_err(err);
 224         exit(1);
 225     }
 226
 227     cpu = ARM_CPU(cpuobj);
 228
 229     memory_region_allocate_system_memory(ram, NULL, "versatile.ram",
 230                                          machine->ram_size);
 231     /* ??? RAM should repeat to fill physical memory space.  */
 232     /* SDRAM at address zero.  */
 233     memory_region_add_subregion(sysmem, 0, ram);
 234
 235     sysctl = qdev_create(NULL, "realview_sysctl");
 236     qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
 237     qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
 238     qdev_init_nofail(sysctl);
 239     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
 240
 241     dev = sysbus_create_varargs("pl190", 0x10140000,
 242                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
 243                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
 244                                 NULL);
 245     for (n = 0; n < 32; n++) {
 246         pic[n] = qdev_get_gpio_in(dev, n);
 247     }
 248     dev = sysbus_create_simple(TYPE_VERSATILE_PB_SIC, 0x10003000, NULL);
 249     for (n = 0; n < 32; n++) {
 250         sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]);
 251         sic[n] = qdev_get_gpio_in(dev, n);
 252     }
 253
 254     sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
 255     sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
 256
 257     dev = qdev_create(NULL, "versatile_pci");
 258     busdev = SYS_BUS_DEVICE(dev);
 259     qdev_init_nofail(dev);
 260     sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */
 261     sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */
 262     sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */
 263     sysbus_mmio_map(busdev, 3, 0x43000000); /* PCI I/O */
 264     sysbus_mmio_map(busdev, 4, 0x44000000); /* PCI memory window 1 */
 265     sysbus_mmio_map(busdev, 5, 0x50000000); /* PCI memory window 2 */
 266     sysbus_mmio_map(busdev, 6, 0x60000000); /* PCI memory window 3 */
 267     sysbus_connect_irq(busdev, 0, sic[27]);
 268     sysbus_connect_irq(busdev, 1, sic[28]);
 269     sysbus_connect_irq(busdev, 2, sic[29]);
 270     sysbus_connect_irq(busdev, 3, sic[30]);
 271     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
 272
 273     for(n = 0; n < nb_nics; n++) {
 274         nd = &nd_table[n];
 275
 276         if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) {
 277             smc91c111_init(nd, 0x10010000, sic[25]);
 278             done_smc = 1;
 279         } else {
 280             pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL);
 281         }
 282     }
 283     if (usb_enabled()) {
 284         pci_create_simple(pci_bus, -1, "pci-ohci");
 285     }
 286     n = drive_get_max_bus(IF_SCSI);
 287     while (n >= 0) {
 288         pci_create_simple(pci_bus, -1, "lsi53c895a");
 289         n--;
 290     }
 291
 292     sysbus_create_simple("pl011", 0x101f1000, pic[12]);
 293     sysbus_create_simple("pl011", 0x101f2000, pic[13]);
 294     sysbus_create_simple("pl011", 0x101f3000, pic[14]);
 295     sysbus_create_simple("pl011", 0x10009000, sic[6]);
 296
 297     sysbus_create_simple("pl080", 0x10130000, pic[17]);
 298     sysbus_create_simple("sp804", 0x101e2000, pic[4]);
 299     sysbus_create_simple("sp804", 0x101e3000, pic[5]);
 300
 301     sysbus_create_simple("pl061", 0x101e4000, pic[6]);
 302     sysbus_create_simple("pl061", 0x101e5000, pic[7]);
 303     sysbus_create_simple("pl061", 0x101e6000, pic[8]);
 304     sysbus_create_simple("pl061", 0x101e7000, pic[9]);
 305
 306     /* The versatile/PB actually has a modified Color LCD controller
 307        that includes hardware cursor support from the PL111.  */
 308     dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
 309     /* Wire up the mux control signals from the SYS_CLCD register */
 310     qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));
 311
 312     sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
 313     sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
 314
 315     /* Add PL031 Real Time Clock. */
 316     sysbus_create_simple("pl031", 0x101e8000, pic[10]);
 317
 318     dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
 319     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 320     i2c_create_slave(i2c, "ds1338", 0x68);
 321
 322     /* Add PL041 AACI Interface to the LM4549 codec */
 323     pl041 = qdev_create(NULL, "pl041");
 324     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 325     qdev_init_nofail(pl041);
 326     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
 327     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]);
 328
 329     /* Memory map for Versatile/PB:  */
 330     /* 0x10000000 System registers.  */
 331     /* 0x10001000 PCI controller config registers.  */
 332     /* 0x10002000 Serial bus interface.  */
 333     /*  0x10003000 Secondary interrupt controller.  */
 334     /* 0x10004000 AACI (audio).  */
 335     /*  0x10005000 MMCI0.  */
 336     /*  0x10006000 KMI0 (keyboard).  */
 337     /*  0x10007000 KMI1 (mouse).  */
 338     /* 0x10008000 Character LCD Interface.  */
 339     /*  0x10009000 UART3.  */
 340     /* 0x1000a000 Smart card 1.  */
 341     /*  0x1000b000 MMCI1.  */
 342     /*  0x10010000 Ethernet.  */
 343     /* 0x10020000 USB.  */
 344     /* 0x10100000 SSMC.  */
 345     /* 0x10110000 MPMC.  */
 346     /*  0x10120000 CLCD Controller.  */
 347     /*  0x10130000 DMA Controller.  */
 348     /*  0x10140000 Vectored interrupt controller.  */
 349     /* 0x101d0000 AHB Monitor Interface.  */
 350     /* 0x101e0000 System Controller.  */
 351     /* 0x101e1000 Watchdog Interface.  */
 352     /* 0x101e2000 Timer 0/1.  */
 353     /* 0x101e3000 Timer 2/3.  */
 354     /* 0x101e4000 GPIO port 0.  */
 355     /* 0x101e5000 GPIO port 1.  */
 356     /* 0x101e6000 GPIO port 2.  */
 357     /* 0x101e7000 GPIO port 3.  */
 358     /* 0x101e8000 RTC.  */
 359     /* 0x101f0000 Smart card 0.  */
 360     /*  0x101f1000 UART0.  */
 361     /*  0x101f2000 UART1.  */
 362     /*  0x101f3000 UART2.  */
 363     /* 0x101f4000 SSPI.  */
 364     /* 0x34000000 NOR Flash */
 365
 366     dinfo = drive_get(IF_PFLASH, 0, 0);
 367     if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, NULL, "versatile.flash",
 368                           VERSATILE_FLASH_SIZE,
 369                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 370                           VERSATILE_FLASH_SECT_SIZE,
 371                           VERSATILE_FLASH_SIZE / VERSATILE_FLASH_SECT_SIZE,
 372                           4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
 373         fprintf(stderr, "qemu: Error registering flash memory.\n");
 374     }
 375
 376     versatile_binfo.ram_size = machine->ram_size;
 377     versatile_binfo.kernel_filename = machine->kernel_filename;
 378     versatile_binfo.kernel_cmdline = machine->kernel_cmdline;
 379     versatile_binfo.initrd_filename = machine->initrd_filename;
 380     versatile_binfo.board_id = board_id;
 381     arm_load_kernel(cpu, &versatile_binfo);
 382 }
 383
 384 static void vpb_init(MachineState *machine)
 385 {
 386     versatile_init(machine, 0x183);
 387 }
 388
 389 static void vab_init(MachineState *machine)
 390 {
 391     versatile_init(machine, 0x25e);
 392 }
 393
 394 static QEMUMachine versatilepb_machine = {
 395     .name = "versatilepb",
 396     .desc = "ARM Versatile/PB (ARM926EJ-S)",
 397     .init = vpb_init,
 398     .block_default_type = IF_SCSI,
 399 };
 400
 401 static QEMUMachine versatileab_machine = {
 402     .name = "versatileab",
 403     .desc = "ARM Versatile/AB (ARM926EJ-S)",
 404     .init = vab_init,
 405     .block_default_type = IF_SCSI,
 406 };
 407
 408 static void versatile_machine_init(void)
 409 {
 410     qemu_register_machine(&versatilepb_machine);
 411     qemu_register_machine(&versatileab_machine);
 412 }
 413
 414 machine_init(versatile_machine_init);
 415
 416 static void vpb_sic_class_init(ObjectClass *klass, void *data)
 417 {
 418     DeviceClass *dc = DEVICE_CLASS(klass);
 419     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 420
 421     k->init = vpb_sic_init;
 422     dc->vmsd = &vmstate_vpb_sic;
 423 }
 424
 425 static const TypeInfo vpb_sic_info = {
 426     .name          = TYPE_VERSATILE_PB_SIC,
 427     .parent        = TYPE_SYS_BUS_DEVICE,
 428     .instance_size = sizeof(vpb_sic_state),
 429     .class_init    = vpb_sic_class_init,
 430 };
 431
 432 static void versatilepb_register_types(void)
 433 {
 434     type_register_static(&vpb_sic_info);
 435 }
 436
 437 type_init(versatilepb_register_types)