2 * ARM Versatile Platform/Application Baseboard System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/sysbus.h"
13 #include "migration/vmstate.h"
14 #include "hw/arm/boot.h"
15 #include "hw/net/smc91c111.h"
17 #include "sysemu/sysemu.h"
18 #include "hw/pci/pci.h"
19 #include "hw/i2c/i2c.h"
20 #include "hw/i2c/arm_sbcon_i2c.h"
22 #include "hw/boards.h"
23 #include "hw/block/flash.h"
24 #include "qemu/error-report.h"
25 #include "hw/char/pl011.h"
27 #include "qom/object.h"
28 #include "audio/audio.h"
29 #include "target/arm/cpu-qom.h"
31 #define VERSATILE_FLASH_ADDR 0x34000000
32 #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)
33 #define VERSATILE_FLASH_SECT_SIZE (256 * 1024)
35 /* Primary interrupt controller. */
37 #define TYPE_VERSATILE_PB_SIC "versatilepb_sic"
38 OBJECT_DECLARE_SIMPLE_TYPE(vpb_sic_state
, VERSATILE_PB_SIC
)
40 struct vpb_sic_state
{
41 SysBusDevice parent_obj
;
51 static const VMStateDescription vmstate_vpb_sic
= {
52 .name
= "versatilepb_sic",
54 .minimum_version_id
= 1,
55 .fields
= (const VMStateField
[]) {
56 VMSTATE_UINT32(level
, vpb_sic_state
),
57 VMSTATE_UINT32(mask
, vpb_sic_state
),
58 VMSTATE_UINT32(pic_enable
, vpb_sic_state
),
63 static void vpb_sic_update(vpb_sic_state
*s
)
67 flags
= s
->level
& s
->mask
;
68 qemu_set_irq(s
->parent
[s
->irq
], flags
!= 0);
71 static void vpb_sic_update_pic(vpb_sic_state
*s
)
76 for (i
= 21; i
<= 30; i
++) {
78 if (!(s
->pic_enable
& mask
))
80 qemu_set_irq(s
->parent
[i
], (s
->level
& mask
) != 0);
84 static void vpb_sic_set_irq(void *opaque
, int irq
, int level
)
86 vpb_sic_state
*s
= (vpb_sic_state
*)opaque
;
88 s
->level
|= 1u << irq
;
90 s
->level
&= ~(1u << irq
);
91 if (s
->pic_enable
& (1u << irq
))
92 qemu_set_irq(s
->parent
[irq
], level
);
96 static uint64_t vpb_sic_read(void *opaque
, hwaddr offset
,
99 vpb_sic_state
*s
= (vpb_sic_state
*)opaque
;
101 switch (offset
>> 2) {
103 return s
->level
& s
->mask
;
104 case 1: /* RAWSTAT */
108 case 4: /* SOFTINT */
110 case 8: /* PICENABLE */
111 return s
->pic_enable
;
113 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset
);
118 static void vpb_sic_write(void *opaque
, hwaddr offset
,
119 uint64_t value
, unsigned size
)
121 vpb_sic_state
*s
= (vpb_sic_state
*)opaque
;
123 switch (offset
>> 2) {
130 case 4: /* SOFTINTSET */
134 case 5: /* SOFTINTCLR */
138 case 8: /* PICENSET */
139 s
->pic_enable
|= (value
& 0x7fe00000);
140 vpb_sic_update_pic(s
);
142 case 9: /* PICENCLR */
143 s
->pic_enable
&= ~value
;
144 vpb_sic_update_pic(s
);
147 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset
);
153 static const MemoryRegionOps vpb_sic_ops
= {
154 .read
= vpb_sic_read
,
155 .write
= vpb_sic_write
,
156 .endianness
= DEVICE_NATIVE_ENDIAN
,
159 static void vpb_sic_init(Object
*obj
)
161 DeviceState
*dev
= DEVICE(obj
);
162 vpb_sic_state
*s
= VERSATILE_PB_SIC(obj
);
163 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
166 qdev_init_gpio_in(dev
, vpb_sic_set_irq
, 32);
167 for (i
= 0; i
< 32; i
++) {
168 sysbus_init_irq(sbd
, &s
->parent
[i
]);
171 memory_region_init_io(&s
->iomem
, obj
, &vpb_sic_ops
, s
,
173 sysbus_init_mmio(sbd
, &s
->iomem
);
178 /* The AB and PB boards both use the same core, just with different
179 peripherals and expansion busses. For now we emulate a subset of the
180 PB peripherals and just change the board ID. */
182 static struct arm_boot_info versatile_binfo
;
184 static void versatile_init(MachineState
*machine
, int board_id
)
188 MemoryRegion
*sysmem
= get_system_memory();
191 DeviceState
*dev
, *sysctl
;
192 SysBusDevice
*busdev
;
199 if (machine
->ram_size
> 0x10000000) {
200 /* Device starting at address 0x10000000,
201 * and memory cannot overlap with devices.
202 * Refuse to run rather than behaving very confusingly.
204 error_report("versatilepb: memory size must not exceed 256MB");
208 cpuobj
= object_new(machine
->cpu_type
);
210 /* By default ARM1176 CPUs have EL3 enabled. This board does not
211 * currently support EL3 so the CPU EL3 property is disabled before
214 if (object_property_find(cpuobj
, "has_el3")) {
215 object_property_set_bool(cpuobj
, "has_el3", false, &error_fatal
);
218 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
220 cpu
= ARM_CPU(cpuobj
);
222 /* ??? RAM should repeat to fill physical memory space. */
223 /* SDRAM at address zero. */
224 memory_region_add_subregion(sysmem
, 0, machine
->ram
);
226 sysctl
= qdev_new("realview_sysctl");
227 qdev_prop_set_uint32(sysctl
, "sys_id", 0x41007004);
228 qdev_prop_set_uint32(sysctl
, "proc_id", 0x02000000);
229 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl
), &error_fatal
);
230 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl
), 0, 0x10000000);
232 dev
= sysbus_create_varargs("pl190", 0x10140000,
233 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_IRQ
),
234 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_FIQ
),
236 for (n
= 0; n
< 32; n
++) {
237 pic
[n
] = qdev_get_gpio_in(dev
, n
);
239 dev
= sysbus_create_simple(TYPE_VERSATILE_PB_SIC
, 0x10003000, NULL
);
240 for (n
= 0; n
< 32; n
++) {
241 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), n
, pic
[n
]);
242 sic
[n
] = qdev_get_gpio_in(dev
, n
);
245 sysbus_create_simple("pl050_keyboard", 0x10006000, sic
[3]);
246 sysbus_create_simple("pl050_mouse", 0x10007000, sic
[4]);
248 dev
= qdev_new("versatile_pci");
249 busdev
= SYS_BUS_DEVICE(dev
);
250 sysbus_realize_and_unref(busdev
, &error_fatal
);
251 sysbus_mmio_map(busdev
, 0, 0x10001000); /* PCI controller regs */
252 sysbus_mmio_map(busdev
, 1, 0x41000000); /* PCI self-config */
253 sysbus_mmio_map(busdev
, 2, 0x42000000); /* PCI config */
254 sysbus_mmio_map(busdev
, 3, 0x43000000); /* PCI I/O */
255 sysbus_mmio_map(busdev
, 4, 0x44000000); /* PCI memory window 1 */
256 sysbus_mmio_map(busdev
, 5, 0x50000000); /* PCI memory window 2 */
257 sysbus_mmio_map(busdev
, 6, 0x60000000); /* PCI memory window 3 */
258 sysbus_connect_irq(busdev
, 0, sic
[27]);
259 sysbus_connect_irq(busdev
, 1, sic
[28]);
260 sysbus_connect_irq(busdev
, 2, sic
[29]);
261 sysbus_connect_irq(busdev
, 3, sic
[30]);
262 pci_bus
= (PCIBus
*)qdev_get_child_bus(dev
, "pci");
264 if (qemu_find_nic_info("smc91c111", true, NULL
)) {
265 smc91c111_init(0x10010000, sic
[25]);
267 pci_init_nic_devices(pci_bus
, "rtl8139");
269 if (machine_usb(machine
)) {
270 pci_create_simple(pci_bus
, -1, "pci-ohci");
272 n
= drive_get_max_bus(IF_SCSI
);
274 dev
= DEVICE(pci_create_simple(pci_bus
, -1, "lsi53c895a"));
275 lsi53c8xx_handle_legacy_cmdline(dev
);
279 pl011_create(0x101f1000, pic
[12], serial_hd(0));
280 pl011_create(0x101f2000, pic
[13], serial_hd(1));
281 pl011_create(0x101f3000, pic
[14], serial_hd(2));
282 pl011_create(0x10009000, sic
[6], serial_hd(3));
284 dev
= qdev_new("pl080");
285 object_property_set_link(OBJECT(dev
), "downstream", OBJECT(sysmem
),
287 busdev
= SYS_BUS_DEVICE(dev
);
288 sysbus_realize_and_unref(busdev
, &error_fatal
);
289 sysbus_mmio_map(busdev
, 0, 0x10130000);
290 sysbus_connect_irq(busdev
, 0, pic
[17]);
292 sysbus_create_simple("sp804", 0x101e2000, pic
[4]);
293 sysbus_create_simple("sp804", 0x101e3000, pic
[5]);
295 sysbus_create_simple("pl061", 0x101e4000, pic
[6]);
296 sysbus_create_simple("pl061", 0x101e5000, pic
[7]);
297 sysbus_create_simple("pl061", 0x101e6000, pic
[8]);
298 sysbus_create_simple("pl061", 0x101e7000, pic
[9]);
300 /* The versatile/PB actually has a modified Color LCD controller
301 that includes hardware cursor support from the PL111. */
302 dev
= qdev_new("pl110_versatile");
303 object_property_set_link(OBJECT(dev
), "framebuffer-memory",
304 OBJECT(sysmem
), &error_fatal
);
305 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
306 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0x10120000);
307 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[16]);
309 /* Wire up the mux control signals from the SYS_CLCD register */
310 qdev_connect_gpio_out(sysctl
, 0, qdev_get_gpio_in(dev
, 0));
312 dev
= sysbus_create_varargs("pl181", 0x10005000, sic
[22], sic
[1], NULL
);
313 dinfo
= drive_get(IF_SD
, 0, 0);
317 card
= qdev_new(TYPE_SD_CARD
);
318 qdev_prop_set_drive_err(card
, "drive", blk_by_legacy_dinfo(dinfo
),
320 qdev_realize_and_unref(card
, qdev_get_child_bus(dev
, "sd-bus"),
324 dev
= sysbus_create_varargs("pl181", 0x1000b000, sic
[23], sic
[2], NULL
);
325 dinfo
= drive_get(IF_SD
, 0, 1);
329 card
= qdev_new(TYPE_SD_CARD
);
330 qdev_prop_set_drive_err(card
, "drive", blk_by_legacy_dinfo(dinfo
),
332 qdev_realize_and_unref(card
, qdev_get_child_bus(dev
, "sd-bus"),
336 /* Add PL031 Real Time Clock. */
337 sysbus_create_simple("pl031", 0x101e8000, pic
[10]);
339 dev
= sysbus_create_simple(TYPE_ARM_SBCON_I2C
, 0x10002000, NULL
);
340 i2c
= (I2CBus
*)qdev_get_child_bus(dev
, "i2c");
341 i2c_slave_create_simple(i2c
, "ds1338", 0x68);
343 /* Add PL041 AACI Interface to the LM4549 codec */
344 pl041
= qdev_new("pl041");
345 qdev_prop_set_uint32(pl041
, "nc_fifo_depth", 512);
346 if (machine
->audiodev
) {
347 qdev_prop_set_string(pl041
, "audiodev", machine
->audiodev
);
349 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041
), &error_fatal
);
350 sysbus_mmio_map(SYS_BUS_DEVICE(pl041
), 0, 0x10004000);
351 sysbus_connect_irq(SYS_BUS_DEVICE(pl041
), 0, sic
[24]);
353 /* Memory map for Versatile/PB: */
354 /* 0x10000000 System registers. */
355 /* 0x10001000 PCI controller config registers. */
356 /* 0x10002000 Serial bus interface. */
357 /* 0x10003000 Secondary interrupt controller. */
358 /* 0x10004000 AACI (audio). */
359 /* 0x10005000 MMCI0. */
360 /* 0x10006000 KMI0 (keyboard). */
361 /* 0x10007000 KMI1 (mouse). */
362 /* 0x10008000 Character LCD Interface. */
363 /* 0x10009000 UART3. */
364 /* 0x1000a000 Smart card 1. */
365 /* 0x1000b000 MMCI1. */
366 /* 0x10010000 Ethernet. */
367 /* 0x10020000 USB. */
368 /* 0x10100000 SSMC. */
369 /* 0x10110000 MPMC. */
370 /* 0x10120000 CLCD Controller. */
371 /* 0x10130000 DMA Controller. */
372 /* 0x10140000 Vectored interrupt controller. */
373 /* 0x101d0000 AHB Monitor Interface. */
374 /* 0x101e0000 System Controller. */
375 /* 0x101e1000 Watchdog Interface. */
376 /* 0x101e2000 Timer 0/1. */
377 /* 0x101e3000 Timer 2/3. */
378 /* 0x101e4000 GPIO port 0. */
379 /* 0x101e5000 GPIO port 1. */
380 /* 0x101e6000 GPIO port 2. */
381 /* 0x101e7000 GPIO port 3. */
382 /* 0x101e8000 RTC. */
383 /* 0x101f0000 Smart card 0. */
384 /* 0x101f1000 UART0. */
385 /* 0x101f2000 UART1. */
386 /* 0x101f3000 UART2. */
387 /* 0x101f4000 SSPI. */
388 /* 0x34000000 NOR Flash */
390 dinfo
= drive_get(IF_PFLASH
, 0, 0);
391 pflash_cfi01_register(VERSATILE_FLASH_ADDR
, "versatile.flash",
392 VERSATILE_FLASH_SIZE
,
393 dinfo
? blk_by_legacy_dinfo(dinfo
) : NULL
,
394 VERSATILE_FLASH_SECT_SIZE
,
395 4, 0x0089, 0x0018, 0x0000, 0x0, 0);
397 versatile_binfo
.ram_size
= machine
->ram_size
;
398 versatile_binfo
.board_id
= board_id
;
399 arm_load_kernel(cpu
, machine
, &versatile_binfo
);
402 static void vpb_init(MachineState
*machine
)
404 versatile_init(machine
, 0x183);
407 static void vab_init(MachineState
*machine
)
409 versatile_init(machine
, 0x25e);
412 static void versatilepb_class_init(ObjectClass
*oc
, void *data
)
414 MachineClass
*mc
= MACHINE_CLASS(oc
);
416 mc
->desc
= "ARM Versatile/PB (ARM926EJ-S)";
418 mc
->block_default_type
= IF_SCSI
;
419 mc
->ignore_memory_transaction_failures
= true;
420 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("arm926");
421 mc
->default_ram_id
= "versatile.ram";
423 machine_add_audiodev_property(mc
);
426 static const TypeInfo versatilepb_type
= {
427 .name
= MACHINE_TYPE_NAME("versatilepb"),
428 .parent
= TYPE_MACHINE
,
429 .class_init
= versatilepb_class_init
,
432 static void versatileab_class_init(ObjectClass
*oc
, void *data
)
434 MachineClass
*mc
= MACHINE_CLASS(oc
);
436 mc
->desc
= "ARM Versatile/AB (ARM926EJ-S)";
438 mc
->block_default_type
= IF_SCSI
;
439 mc
->ignore_memory_transaction_failures
= true;
440 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("arm926");
441 mc
->default_ram_id
= "versatile.ram";
443 machine_add_audiodev_property(mc
);
446 static const TypeInfo versatileab_type
= {
447 .name
= MACHINE_TYPE_NAME("versatileab"),
448 .parent
= TYPE_MACHINE
,
449 .class_init
= versatileab_class_init
,
452 static void versatile_machine_init(void)
454 type_register_static(&versatilepb_type
);
455 type_register_static(&versatileab_type
);
458 type_init(versatile_machine_init
)
460 static void vpb_sic_class_init(ObjectClass
*klass
, void *data
)
462 DeviceClass
*dc
= DEVICE_CLASS(klass
);
464 dc
->vmsd
= &vmstate_vpb_sic
;
467 static const TypeInfo vpb_sic_info
= {
468 .name
= TYPE_VERSATILE_PB_SIC
,
469 .parent
= TYPE_SYS_BUS_DEVICE
,
470 .instance_size
= sizeof(vpb_sic_state
),
471 .instance_init
= vpb_sic_init
,
472 .class_init
= vpb_sic_class_init
,
475 static void versatilepb_register_types(void)
477 type_register_static(&vpb_sic_info
);
480 type_init(versatilepb_register_types
)