2 * QEMU model of Xilinx AXI-DMA block.
4 * Copyright (c) 2011 Edgar E. Iglesias.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "qapi/error.h"
28 #include "qemu/timer.h"
29 #include "hw/ptimer.h"
31 #include "qemu/main-loop.h"
32 #include "qemu/module.h"
34 #include "hw/stream.h"
38 #define TYPE_XILINX_AXI_DMA "xlnx.axi-dma"
39 #define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream"
40 #define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream"
42 #define XILINX_AXI_DMA(obj) \
43 OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
45 #define XILINX_AXI_DMA_DATA_STREAM(obj) \
46 OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
47 TYPE_XILINX_AXI_DMA_DATA_STREAM)
49 #define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
50 OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
51 TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
53 #define R_DMACR (0x00 / 4)
54 #define R_DMASR (0x04 / 4)
55 #define R_CURDESC (0x08 / 4)
56 #define R_TAILDESC (0x10 / 4)
57 #define R_MAX (0x30 / 4)
59 #define CONTROL_PAYLOAD_WORDS 5
60 #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
62 typedef struct XilinxAXIDMA XilinxAXIDMA
;
63 typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave
;
67 DMACR_TAILPTR_MODE
= 2,
74 DMASR_IOC_IRQ
= 1 << 12,
75 DMASR_DLY_IRQ
= 1 << 13,
77 DMASR_IRQ_MASK
= 7 << 12
82 uint64_t buffer_address
;
86 uint8_t app
[CONTROL_PAYLOAD_SIZE
];
90 SDESC_CTRL_EOF
= (1 << 26),
91 SDESC_CTRL_SOF
= (1 << 27),
93 SDESC_CTRL_LEN_MASK
= (1 << 23) - 1
97 SDESC_STATUS_EOF
= (1 << 26),
98 SDESC_STATUS_SOF_BIT
= 27,
99 SDESC_STATUS_SOF
= (1 << SDESC_STATUS_SOF_BIT
),
100 SDESC_STATUS_COMPLETE
= (1 << 31)
105 ptimer_state
*ptimer
;
112 unsigned int complete_cnt
;
113 uint32_t regs
[R_MAX
];
115 unsigned char txbuf
[16 * 1024];
118 struct XilinxAXIDMAStreamSlave
{
121 struct XilinxAXIDMA
*dma
;
124 struct XilinxAXIDMA
{
128 StreamSlave
*tx_data_dev
;
129 StreamSlave
*tx_control_dev
;
130 XilinxAXIDMAStreamSlave rx_data_dev
;
131 XilinxAXIDMAStreamSlave rx_control_dev
;
133 struct Stream streams
[2];
135 StreamCanPushNotifyFn notify
;
140 * Helper calls to extract info from descriptors and other trivial
143 static inline int stream_desc_sof(struct SDesc
*d
)
145 return d
->control
& SDESC_CTRL_SOF
;
148 static inline int stream_desc_eof(struct SDesc
*d
)
150 return d
->control
& SDESC_CTRL_EOF
;
153 static inline int stream_resetting(struct Stream
*s
)
155 return !!(s
->regs
[R_DMACR
] & DMACR_RESET
);
158 static inline int stream_running(struct Stream
*s
)
160 return s
->regs
[R_DMACR
] & DMACR_RUNSTOP
;
163 static inline int stream_idle(struct Stream
*s
)
165 return !!(s
->regs
[R_DMASR
] & DMASR_IDLE
);
168 static void stream_reset(struct Stream
*s
)
170 s
->regs
[R_DMASR
] = DMASR_HALTED
; /* starts up halted. */
171 s
->regs
[R_DMACR
] = 1 << 16; /* Starts with one in compl threshold. */
174 /* Map an offset addr into a channel index. */
175 static inline int streamid_from_addr(hwaddr addr
)
184 static void stream_desc_load(struct Stream
*s
, hwaddr addr
)
186 struct SDesc
*d
= &s
->desc
;
188 cpu_physical_memory_read(addr
, d
, sizeof *d
);
190 /* Convert from LE into host endianness. */
191 d
->buffer_address
= le64_to_cpu(d
->buffer_address
);
192 d
->nxtdesc
= le64_to_cpu(d
->nxtdesc
);
193 d
->control
= le32_to_cpu(d
->control
);
194 d
->status
= le32_to_cpu(d
->status
);
197 static void stream_desc_store(struct Stream
*s
, hwaddr addr
)
199 struct SDesc
*d
= &s
->desc
;
201 /* Convert from host endianness into LE. */
202 d
->buffer_address
= cpu_to_le64(d
->buffer_address
);
203 d
->nxtdesc
= cpu_to_le64(d
->nxtdesc
);
204 d
->control
= cpu_to_le32(d
->control
);
205 d
->status
= cpu_to_le32(d
->status
);
206 cpu_physical_memory_write(addr
, d
, sizeof *d
);
209 static void stream_update_irq(struct Stream
*s
)
211 unsigned int pending
, mask
, irq
;
213 pending
= s
->regs
[R_DMASR
] & DMASR_IRQ_MASK
;
214 mask
= s
->regs
[R_DMACR
] & DMASR_IRQ_MASK
;
216 irq
= pending
& mask
;
218 qemu_set_irq(s
->irq
, !!irq
);
221 static void stream_reload_complete_cnt(struct Stream
*s
)
223 unsigned int comp_th
;
224 comp_th
= (s
->regs
[R_DMACR
] >> 16) & 0xff;
225 s
->complete_cnt
= comp_th
;
228 static void timer_hit(void *opaque
)
230 struct Stream
*s
= opaque
;
232 stream_reload_complete_cnt(s
);
233 s
->regs
[R_DMASR
] |= DMASR_DLY_IRQ
;
234 stream_update_irq(s
);
237 static void stream_complete(struct Stream
*s
)
239 unsigned int comp_delay
;
241 /* Start the delayed timer. */
242 comp_delay
= s
->regs
[R_DMACR
] >> 24;
244 ptimer_stop(s
->ptimer
);
245 ptimer_set_count(s
->ptimer
, comp_delay
);
246 ptimer_run(s
->ptimer
, 1);
250 if (s
->complete_cnt
== 0) {
251 /* Raise the IOC irq. */
252 s
->regs
[R_DMASR
] |= DMASR_IOC_IRQ
;
253 stream_reload_complete_cnt(s
);
257 static void stream_process_mem2s(struct Stream
*s
, StreamSlave
*tx_data_dev
,
258 StreamSlave
*tx_control_dev
)
263 if (!stream_running(s
) || stream_idle(s
)) {
268 stream_desc_load(s
, s
->regs
[R_CURDESC
]);
270 if (s
->desc
.status
& SDESC_STATUS_COMPLETE
) {
271 s
->regs
[R_DMASR
] |= DMASR_HALTED
;
275 if (stream_desc_sof(&s
->desc
)) {
277 stream_push(tx_control_dev
, s
->desc
.app
, sizeof(s
->desc
.app
));
280 txlen
= s
->desc
.control
& SDESC_CTRL_LEN_MASK
;
281 if ((txlen
+ s
->pos
) > sizeof s
->txbuf
) {
282 hw_error("%s: too small internal txbuf! %d\n", __func__
,
286 cpu_physical_memory_read(s
->desc
.buffer_address
,
287 s
->txbuf
+ s
->pos
, txlen
);
290 if (stream_desc_eof(&s
->desc
)) {
291 stream_push(tx_data_dev
, s
->txbuf
, s
->pos
);
296 /* Update the descriptor. */
297 s
->desc
.status
= txlen
| SDESC_STATUS_COMPLETE
;
298 stream_desc_store(s
, s
->regs
[R_CURDESC
]);
301 prev_d
= s
->regs
[R_CURDESC
];
302 s
->regs
[R_CURDESC
] = s
->desc
.nxtdesc
;
303 if (prev_d
== s
->regs
[R_TAILDESC
]) {
304 s
->regs
[R_DMASR
] |= DMASR_IDLE
;
310 static size_t stream_process_s2mem(struct Stream
*s
, unsigned char *buf
,
318 if (!stream_running(s
) || stream_idle(s
)) {
323 stream_desc_load(s
, s
->regs
[R_CURDESC
]);
325 if (s
->desc
.status
& SDESC_STATUS_COMPLETE
) {
326 s
->regs
[R_DMASR
] |= DMASR_HALTED
;
330 rxlen
= s
->desc
.control
& SDESC_CTRL_LEN_MASK
;
336 cpu_physical_memory_write(s
->desc
.buffer_address
, buf
+ pos
, rxlen
);
340 /* Update the descriptor. */
343 memcpy(s
->desc
.app
, s
->app
, sizeof(s
->desc
.app
));
344 s
->desc
.status
|= SDESC_STATUS_EOF
;
347 s
->desc
.status
|= sof
<< SDESC_STATUS_SOF_BIT
;
348 s
->desc
.status
|= SDESC_STATUS_COMPLETE
;
349 stream_desc_store(s
, s
->regs
[R_CURDESC
]);
353 prev_d
= s
->regs
[R_CURDESC
];
354 s
->regs
[R_CURDESC
] = s
->desc
.nxtdesc
;
355 if (prev_d
== s
->regs
[R_TAILDESC
]) {
356 s
->regs
[R_DMASR
] |= DMASR_IDLE
;
364 static void xilinx_axidma_reset(DeviceState
*dev
)
367 XilinxAXIDMA
*s
= XILINX_AXI_DMA(dev
);
369 for (i
= 0; i
< 2; i
++) {
370 stream_reset(&s
->streams
[i
]);
375 xilinx_axidma_control_stream_push(StreamSlave
*obj
, unsigned char *buf
,
378 XilinxAXIDMAStreamSlave
*cs
= XILINX_AXI_DMA_CONTROL_STREAM(obj
);
379 struct Stream
*s
= &cs
->dma
->streams
[1];
381 if (len
!= CONTROL_PAYLOAD_SIZE
) {
382 hw_error("AXI DMA requires %d byte control stream payload\n",
383 (int)CONTROL_PAYLOAD_SIZE
);
386 memcpy(s
->app
, buf
, len
);
391 xilinx_axidma_data_stream_can_push(StreamSlave
*obj
,
392 StreamCanPushNotifyFn notify
,
395 XilinxAXIDMAStreamSlave
*ds
= XILINX_AXI_DMA_DATA_STREAM(obj
);
396 struct Stream
*s
= &ds
->dma
->streams
[1];
398 if (!stream_running(s
) || stream_idle(s
)) {
399 ds
->dma
->notify
= notify
;
400 ds
->dma
->notify_opaque
= notify_opaque
;
408 xilinx_axidma_data_stream_push(StreamSlave
*obj
, unsigned char *buf
, size_t len
)
410 XilinxAXIDMAStreamSlave
*ds
= XILINX_AXI_DMA_DATA_STREAM(obj
);
411 struct Stream
*s
= &ds
->dma
->streams
[1];
414 ret
= stream_process_s2mem(s
, buf
, len
);
415 stream_update_irq(s
);
419 static uint64_t axidma_read(void *opaque
, hwaddr addr
,
422 XilinxAXIDMA
*d
= opaque
;
427 sid
= streamid_from_addr(addr
);
428 s
= &d
->streams
[sid
];
434 /* Simulate one cycles reset delay. */
435 s
->regs
[addr
] &= ~DMACR_RESET
;
439 s
->regs
[addr
] &= 0xffff;
440 s
->regs
[addr
] |= (s
->complete_cnt
& 0xff) << 16;
441 s
->regs
[addr
] |= (ptimer_get_count(s
->ptimer
) & 0xff) << 24;
446 D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx
" v=%x\n",
447 __func__
, sid
, addr
* 4, r
));
454 static void axidma_write(void *opaque
, hwaddr addr
,
455 uint64_t value
, unsigned size
)
457 XilinxAXIDMA
*d
= opaque
;
461 sid
= streamid_from_addr(addr
);
462 s
= &d
->streams
[sid
];
468 /* Tailptr mode is always on. */
469 value
|= DMACR_TAILPTR_MODE
;
470 /* Remember our previous reset state. */
471 value
|= (s
->regs
[addr
] & DMACR_RESET
);
472 s
->regs
[addr
] = value
;
474 if (value
& DMACR_RESET
) {
478 if ((value
& 1) && !stream_resetting(s
)) {
479 /* Start processing. */
480 s
->regs
[R_DMASR
] &= ~(DMASR_HALTED
| DMASR_IDLE
);
482 stream_reload_complete_cnt(s
);
486 /* Mask away write to clear irq lines. */
487 value
&= ~(value
& DMASR_IRQ_MASK
);
488 s
->regs
[addr
] = value
;
492 s
->regs
[addr
] = value
;
493 s
->regs
[R_DMASR
] &= ~DMASR_IDLE
; /* Not idle. */
495 stream_process_mem2s(s
, d
->tx_data_dev
, d
->tx_control_dev
);
499 D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx
" v=%x\n",
500 __func__
, sid
, addr
* 4, (unsigned)value
));
501 s
->regs
[addr
] = value
;
504 if (sid
== 1 && d
->notify
) {
505 StreamCanPushNotifyFn notifytmp
= d
->notify
;
507 notifytmp(d
->notify_opaque
);
509 stream_update_irq(s
);
512 static const MemoryRegionOps axidma_ops
= {
514 .write
= axidma_write
,
515 .endianness
= DEVICE_NATIVE_ENDIAN
,
518 static void xilinx_axidma_realize(DeviceState
*dev
, Error
**errp
)
520 XilinxAXIDMA
*s
= XILINX_AXI_DMA(dev
);
521 XilinxAXIDMAStreamSlave
*ds
= XILINX_AXI_DMA_DATA_STREAM(&s
->rx_data_dev
);
522 XilinxAXIDMAStreamSlave
*cs
= XILINX_AXI_DMA_CONTROL_STREAM(
524 Error
*local_err
= NULL
;
526 object_property_add_link(OBJECT(ds
), "dma", TYPE_XILINX_AXI_DMA
,
528 object_property_allow_set_link
,
529 OBJ_PROP_LINK_STRONG
,
531 object_property_add_link(OBJECT(cs
), "dma", TYPE_XILINX_AXI_DMA
,
533 object_property_allow_set_link
,
534 OBJ_PROP_LINK_STRONG
,
537 goto xilinx_axidma_realize_fail
;
539 object_property_set_link(OBJECT(ds
), OBJECT(s
), "dma", &local_err
);
540 object_property_set_link(OBJECT(cs
), OBJECT(s
), "dma", &local_err
);
542 goto xilinx_axidma_realize_fail
;
547 for (i
= 0; i
< 2; i
++) {
548 struct Stream
*st
= &s
->streams
[i
];
551 st
->bh
= qemu_bh_new(timer_hit
, st
);
552 st
->ptimer
= ptimer_init(st
->bh
, PTIMER_POLICY_DEFAULT
);
553 ptimer_set_freq(st
->ptimer
, s
->freqhz
);
557 xilinx_axidma_realize_fail
:
558 error_propagate(errp
, local_err
);
561 static void xilinx_axidma_init(Object
*obj
)
563 XilinxAXIDMA
*s
= XILINX_AXI_DMA(obj
);
564 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
566 object_initialize(&s
->rx_data_dev
, sizeof(s
->rx_data_dev
),
567 TYPE_XILINX_AXI_DMA_DATA_STREAM
);
568 object_initialize(&s
->rx_control_dev
, sizeof(s
->rx_control_dev
),
569 TYPE_XILINX_AXI_DMA_CONTROL_STREAM
);
570 object_property_add_child(OBJECT(s
), "axistream-connected-target",
571 (Object
*)&s
->rx_data_dev
, &error_abort
);
572 object_property_add_child(OBJECT(s
), "axistream-control-connected-target",
573 (Object
*)&s
->rx_control_dev
, &error_abort
);
575 sysbus_init_irq(sbd
, &s
->streams
[0].irq
);
576 sysbus_init_irq(sbd
, &s
->streams
[1].irq
);
578 memory_region_init_io(&s
->iomem
, obj
, &axidma_ops
, s
,
579 "xlnx.axi-dma", R_MAX
* 4 * 2);
580 sysbus_init_mmio(sbd
, &s
->iomem
);
583 static Property axidma_properties
[] = {
584 DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA
, freqhz
, 50000000),
585 DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA
,
586 tx_data_dev
, TYPE_STREAM_SLAVE
, StreamSlave
*),
587 DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIDMA
,
588 tx_control_dev
, TYPE_STREAM_SLAVE
, StreamSlave
*),
589 DEFINE_PROP_END_OF_LIST(),
592 static void axidma_class_init(ObjectClass
*klass
, void *data
)
594 DeviceClass
*dc
= DEVICE_CLASS(klass
);
596 dc
->realize
= xilinx_axidma_realize
,
597 dc
->reset
= xilinx_axidma_reset
;
598 dc
->props
= axidma_properties
;
601 static StreamSlaveClass xilinx_axidma_data_stream_class
= {
602 .push
= xilinx_axidma_data_stream_push
,
603 .can_push
= xilinx_axidma_data_stream_can_push
,
606 static StreamSlaveClass xilinx_axidma_control_stream_class
= {
607 .push
= xilinx_axidma_control_stream_push
,
610 static void xilinx_axidma_stream_class_init(ObjectClass
*klass
, void *data
)
612 StreamSlaveClass
*ssc
= STREAM_SLAVE_CLASS(klass
);
614 ssc
->push
= ((StreamSlaveClass
*)data
)->push
;
615 ssc
->can_push
= ((StreamSlaveClass
*)data
)->can_push
;
618 static const TypeInfo axidma_info
= {
619 .name
= TYPE_XILINX_AXI_DMA
,
620 .parent
= TYPE_SYS_BUS_DEVICE
,
621 .instance_size
= sizeof(XilinxAXIDMA
),
622 .class_init
= axidma_class_init
,
623 .instance_init
= xilinx_axidma_init
,
626 static const TypeInfo xilinx_axidma_data_stream_info
= {
627 .name
= TYPE_XILINX_AXI_DMA_DATA_STREAM
,
628 .parent
= TYPE_OBJECT
,
629 .instance_size
= sizeof(struct XilinxAXIDMAStreamSlave
),
630 .class_init
= xilinx_axidma_stream_class_init
,
631 .class_data
= &xilinx_axidma_data_stream_class
,
632 .interfaces
= (InterfaceInfo
[]) {
633 { TYPE_STREAM_SLAVE
},
638 static const TypeInfo xilinx_axidma_control_stream_info
= {
639 .name
= TYPE_XILINX_AXI_DMA_CONTROL_STREAM
,
640 .parent
= TYPE_OBJECT
,
641 .instance_size
= sizeof(struct XilinxAXIDMAStreamSlave
),
642 .class_init
= xilinx_axidma_stream_class_init
,
643 .class_data
= &xilinx_axidma_control_stream_class
,
644 .interfaces
= (InterfaceInfo
[]) {
645 { TYPE_STREAM_SLAVE
},
650 static void xilinx_axidma_register_types(void)
652 type_register_static(&axidma_info
);
653 type_register_static(&xilinx_axidma_data_stream_info
);
654 type_register_static(&xilinx_axidma_control_stream_info
);
657 type_init(xilinx_axidma_register_types
)