2 * TriCore emulation for qemu: main CPU struct.
4 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "exec/cpu-defs.h"
25 #include "tricore-defs.h"
27 struct tricore_boot_info
;
29 typedef struct tricore_def_t tricore_def_t
;
31 typedef struct CPUArchState
{
37 /* Frequently accessed PSW_USB bits are stored separately for efficiency.
38 This contains all the other bits. Use psw_{read,write} to access
42 /* PSW flag cache for faster execution
45 uint32_t PSW_USB_V
; /* Only if bit 31 set, then flag is set */
46 uint32_t PSW_USB_SV
; /* Only if bit 31 set, then flag is set */
47 uint32_t PSW_USB_AV
; /* Only if bit 31 set, then flag is set. */
48 uint32_t PSW_USB_SAV
; /* Only if bit 31 set, then flag is set. */
62 /* Mem Protection Register */
145 /* Memory Management Registers */
163 /* Debug Registers */
179 /* Floating Point Registers */
180 float_status fp_status
;
183 uint32_t hflags
; /* CPU State */
185 /* Internal CPU feature flags. */
188 const tricore_def_t
*cpu_model
;
190 struct QEMUTimer
*timer
; /* Internal timer */
195 * @env: #CPUTriCoreState
204 CPUNegativeOffsetState neg
;
209 hwaddr
tricore_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
210 void tricore_cpu_dump_state(CPUState
*cpu
, FILE *f
, int flags
);
213 #define MASK_PCXI_PCPN 0xff000000
214 #define MASK_PCXI_PIE_1_3 0x00800000
215 #define MASK_PCXI_PIE_1_6 0x00200000
216 #define MASK_PCXI_UL 0x00400000
217 #define MASK_PCXI_PCXS 0x000f0000
218 #define MASK_PCXI_PCXO 0x0000ffff
220 #define MASK_PSW_USB 0xff000000
221 #define MASK_USB_C 0x80000000
222 #define MASK_USB_V 0x40000000
223 #define MASK_USB_SV 0x20000000
224 #define MASK_USB_AV 0x10000000
225 #define MASK_USB_SAV 0x08000000
226 #define MASK_PSW_PRS 0x00003000
227 #define MASK_PSW_IO 0x00000c00
228 #define MASK_PSW_IS 0x00000200
229 #define MASK_PSW_GW 0x00000100
230 #define MASK_PSW_CDE 0x00000080
231 #define MASK_PSW_CDC 0x0000007f
232 #define MASK_PSW_FPU_RM 0x3000000
234 #define MASK_SYSCON_PRO_TEN 0x2
235 #define MASK_SYSCON_FCD_SF 0x1
237 #define MASK_CPUID_MOD 0xffff0000
238 #define MASK_CPUID_MOD_32B 0x0000ff00
239 #define MASK_CPUID_REV 0x000000ff
241 #define MASK_ICR_PIPN 0x00ff0000
242 #define MASK_ICR_IE_1_3 0x00000100
243 #define MASK_ICR_IE_1_6 0x00008000
244 #define MASK_ICR_CCPN 0x000000ff
246 #define MASK_FCX_FCXS 0x000f0000
247 #define MASK_FCX_FCXO 0x0000ffff
249 #define MASK_LCX_LCXS 0x000f0000
250 #define MASK_LCX_LCX0 0x0000ffff
252 #define MASK_DBGSR_DE 0x1
253 #define MASK_DBGSR_HALT 0x6
254 #define MASK_DBGSR_SUSP 0x10
255 #define MASK_DBGSR_PREVSUSP 0x20
256 #define MASK_DBGSR_PEVT 0x40
257 #define MASK_DBGSR_EVTSRC 0x1f00
259 #define TRICORE_HFLAG_KUU 0x3
260 #define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */
261 #define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */
262 #define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */
264 enum tricore_features
{
271 static inline int tricore_feature(CPUTriCoreState
*env
, int feature
)
273 return (env
->features
& (1ULL << feature
)) != 0;
276 /* TriCore Traps Classes*/
353 uint32_t psw_read(CPUTriCoreState
*env
);
354 void psw_write(CPUTriCoreState
*env
, uint32_t val
);
355 int tricore_cpu_gdb_read_register(CPUState
*cs
, GByteArray
*mem_buf
, int n
);
356 int tricore_cpu_gdb_write_register(CPUState
*cs
, uint8_t *mem_buf
, int n
);
358 void fpu_set_state(CPUTriCoreState
*env
);
360 #define MMU_USER_IDX 2
362 void tricore_cpu_list(void);
364 #define cpu_list tricore_cpu_list
366 static inline int cpu_mmu_index(CPUTriCoreState
*env
, bool ifetch
)
371 #include "exec/cpu-all.h"
373 void cpu_state_reset(CPUTriCoreState
*s
);
374 void tricore_tcg_init(void);
376 static inline void cpu_get_tb_cpu_state(CPUTriCoreState
*env
, target_ulong
*pc
,
377 target_ulong
*cs_base
, uint32_t *flags
)
384 #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
385 #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
386 #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU
389 bool tricore_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
390 MMUAccessType access_type
, int mmu_idx
,
391 bool probe
, uintptr_t retaddr
);
393 #endif /* TRICORE_CPU_H */