target/tricore/cpu.h

   1 /*
   2  *  TriCore emulation for qemu: main CPU struct.
   3  *
   4  *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef TRICORE_CPU_H
  21 #define TRICORE_CPU_H
  22
  23 #include "cpu-qom.h"
  24 #include "hw/registerfields.h"
  25 #include "exec/cpu-defs.h"
  26 #include "qemu/cpu-float.h"
  27 #include "tricore-defs.h"
  28
  29 typedef struct CPUArchState {
  30     /* GPR Register */
  31     uint32_t gpr_a[16];
  32     uint32_t gpr_d[16];
  33 /* Frequently accessed PSW_USB bits are stored separately for efficiency.
  34        This contains all the other bits.  Use psw_{read,write} to access
  35        the whole PSW.  */
  36     uint32_t PSW;
  37     /* PSW flag cache for faster execution */
  38     uint32_t PSW_USB_C;
  39     uint32_t PSW_USB_V;   /* Only if bit 31 set, then flag is set  */
  40     uint32_t PSW_USB_SV;  /* Only if bit 31 set, then flag is set  */
  41     uint32_t PSW_USB_AV;  /* Only if bit 31 set, then flag is set. */
  42     uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
  43
  44 #define R(ADDR, NAME, FEATURE) uint32_t NAME;
  45 #define A(ADDR, NAME, FEATURE) uint32_t NAME;
  46 #define E(ADDR, NAME, FEATURE) uint32_t NAME;
  47 #include "csfr.h.inc"
  48 #undef R
  49 #undef A
  50 #undef E
  51
  52     /* Floating Point Registers */
  53     float_status fp_status;
  54
  55     /* Internal CPU feature flags.  */
  56     uint64_t features;
  57 } CPUTriCoreState;
  58
  59 /**
  60  * TriCoreCPU:
  61  * @env: #CPUTriCoreState
  62  *
  63  * A TriCore CPU.
  64  */
  65 struct ArchCPU {
  66     CPUState parent_obj;
  67
  68     CPUTriCoreState env;
  69 };
  70
  71 struct TriCoreCPUClass {
  72     CPUClass parent_class;
  73
  74     DeviceRealize parent_realize;
  75     ResettablePhases parent_phases;
  76 };
  77
  78 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
  79 void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
  80
  81 FIELD(PCXI, PCPN_13, 24, 8)
  82 FIELD(PCXI, PCPN_161, 22, 8)
  83 FIELD(PCXI, PIE_13, 23, 1)
  84 FIELD(PCXI, PIE_161, 21, 1)
  85 FIELD(PCXI, UL_13, 22, 1)
  86 FIELD(PCXI, UL_161, 20, 1)
  87 FIELD(PCXI, PCXS, 16, 4)
  88 FIELD(PCXI, PCXO, 0, 16)
  89 uint32_t pcxi_get_ul(CPUTriCoreState *env);
  90 uint32_t pcxi_get_pie(CPUTriCoreState *env);
  91 uint32_t pcxi_get_pcpn(CPUTriCoreState *env);
  92 uint32_t pcxi_get_pcxs(CPUTriCoreState *env);
  93 uint32_t pcxi_get_pcxo(CPUTriCoreState *env);
  94 void pcxi_set_ul(CPUTriCoreState *env, uint32_t val);
  95 void pcxi_set_pie(CPUTriCoreState *env, uint32_t val);
  96 void pcxi_set_pcpn(CPUTriCoreState *env, uint32_t val);
  97
  98 FIELD(ICR, IE_161, 15, 1)
  99 FIELD(ICR, IE_13, 8, 1)
 100 FIELD(ICR, PIPN, 16, 8)
 101 FIELD(ICR, CCPN, 0, 8)
 102
 103 uint32_t icr_get_ie(CPUTriCoreState *env);
 104 uint32_t icr_get_ccpn(CPUTriCoreState *env);
 105
 106 void icr_set_ccpn(CPUTriCoreState *env, uint32_t val);
 107 void icr_set_ie(CPUTriCoreState *env, uint32_t val);
 108
 109 #define MASK_PSW_USB 0xff000000
 110 #define MASK_USB_C   0x80000000
 111 #define MASK_USB_V   0x40000000
 112 #define MASK_USB_SV  0x20000000
 113 #define MASK_USB_AV  0x10000000
 114 #define MASK_USB_SAV 0x08000000
 115 #define MASK_PSW_PRS 0x00003000
 116 #define MASK_PSW_IO  0x00000c00
 117 #define MASK_PSW_IS  0x00000200
 118 #define MASK_PSW_GW  0x00000100
 119 #define MASK_PSW_CDE 0x00000080
 120 #define MASK_PSW_CDC 0x0000007f
 121 #define MASK_PSW_FPU_RM 0x3000000
 122
 123 #define MASK_SYSCON_PRO_TEN 0x2
 124 #define MASK_SYSCON_FCD_SF  0x1
 125
 126 #define MASK_CPUID_MOD     0xffff0000
 127 #define MASK_CPUID_MOD_32B 0x0000ff00
 128 #define MASK_CPUID_REV     0x000000ff
 129
 130
 131 #define MASK_FCX_FCXS 0x000f0000
 132 #define MASK_FCX_FCXO 0x0000ffff
 133
 134 #define MASK_LCX_LCXS 0x000f0000
 135 #define MASK_LCX_LCX0 0x0000ffff
 136
 137 #define MASK_DBGSR_DE 0x1
 138 #define MASK_DBGSR_HALT 0x6
 139 #define MASK_DBGSR_SUSP 0x10
 140 #define MASK_DBGSR_PREVSUSP 0x20
 141 #define MASK_DBGSR_PEVT 0x40
 142 #define MASK_DBGSR_EVTSRC 0x1f00
 143
 144 enum tricore_priv_levels {
 145     TRICORE_PRIV_UM0 = 0x0, /* user mode-0 flag */
 146     TRICORE_PRIV_UM1 = 0x1, /* user mode-1 flag */
 147     TRICORE_PRIV_SM  = 0x2, /* kernel mode flag */
 148 };
 149
 150 enum tricore_features {
 151     TRICORE_FEATURE_13,
 152     TRICORE_FEATURE_131,
 153     TRICORE_FEATURE_16,
 154     TRICORE_FEATURE_161,
 155     TRICORE_FEATURE_162,
 156 };
 157
 158 static inline int tricore_has_feature(CPUTriCoreState *env, int feature)
 159 {
 160     return (env->features & (1ULL << feature)) != 0;
 161 }
 162
 163 /* TriCore Traps Classes*/
 164 enum {
 165     TRAPC_NONE     = -1,
 166     TRAPC_MMU      = 0,
 167     TRAPC_PROT     = 1,
 168     TRAPC_INSN_ERR = 2,
 169     TRAPC_CTX_MNG  = 3,
 170     TRAPC_SYSBUS   = 4,
 171     TRAPC_ASSERT   = 5,
 172     TRAPC_SYSCALL  = 6,
 173     TRAPC_NMI      = 7,
 174     TRAPC_IRQ      = 8
 175 };
 176
 177 /* Class 0 TIN */
 178 enum {
 179     TIN0_VAF = 0,
 180     TIN0_VAP = 1,
 181 };
 182
 183 /* Class 1 TIN */
 184 enum {
 185     TIN1_PRIV = 1,
 186     TIN1_MPR  = 2,
 187     TIN1_MPW  = 3,
 188     TIN1_MPX  = 4,
 189     TIN1_MPP  = 5,
 190     TIN1_MPN  = 6,
 191     TIN1_GRWP = 7,
 192 };
 193
 194 /* Class 2 TIN */
 195 enum {
 196     TIN2_IOPC = 1,
 197     TIN2_UOPC = 2,
 198     TIN2_OPD  = 3,
 199     TIN2_ALN  = 4,
 200     TIN2_MEM  = 5,
 201 };
 202
 203 /* Class 3 TIN */
 204 enum {
 205     TIN3_FCD  = 1,
 206     TIN3_CDO  = 2,
 207     TIN3_CDU  = 3,
 208     TIN3_FCU  = 4,
 209     TIN3_CSU  = 5,
 210     TIN3_CTYP = 6,
 211     TIN3_NEST = 7,
 212 };
 213
 214 /* Class 4 TIN */
 215 enum {
 216     TIN4_PSE = 1,
 217     TIN4_DSE = 2,
 218     TIN4_DAE = 3,
 219     TIN4_CAE = 4,
 220     TIN4_PIE = 5,
 221     TIN4_DIE = 6,
 222 };
 223
 224 /* Class 5 TIN */
 225 enum {
 226     TIN5_OVF  = 1,
 227     TIN5_SOVF = 1,
 228 };
 229
 230 /* Class 6 TIN
 231  *
 232  * Is always TIN6_SYS
 233  */
 234
 235 /* Class 7 TIN */
 236 enum {
 237     TIN7_NMI = 0,
 238 };
 239
 240 uint32_t psw_read(CPUTriCoreState *env);
 241 void psw_write(CPUTriCoreState *env, uint32_t val);
 242 int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
 243 int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
 244
 245 void fpu_set_state(CPUTriCoreState *env);
 246
 247 #define MMU_USER_IDX 2
 248
 249 #include "exec/cpu-all.h"
 250
 251 FIELD(TB_FLAGS, PRIV, 0, 2)
 252
 253 void cpu_state_reset(CPUTriCoreState *s);
 254 void tricore_tcg_init(void);
 255
 256 static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc,
 257                                         uint64_t *cs_base, uint32_t *flags)
 258 {
 259     uint32_t new_flags = 0;
 260     *pc = env->PC;
 261     *cs_base = 0;
 262
 263     new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV,
 264             extract32(env->PSW, 10, 2));
 265     *flags = new_flags;
 266 }
 267
 268 #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU
 269
 270 /* helpers.c */
 271 bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 272                           MMUAccessType access_type, int mmu_idx,
 273                           bool probe, uintptr_t retaddr);
 274
 275 #endif /* TRICORE_CPU_H */