2 * Helpers for loads and stores
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
31 //#define DEBUG_UNASSIGNED
33 //#define DEBUG_CACHE_CONTROL
36 #define DPRINTF_MMU(fmt, ...) \
37 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
39 #define DPRINTF_MMU(fmt, ...) do {} while (0)
43 #define DPRINTF_MXCC(fmt, ...) \
44 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
46 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
50 #define DPRINTF_ASI(fmt, ...) \
51 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
54 #ifdef DEBUG_CACHE_CONTROL
55 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
56 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
58 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
63 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
65 #define AM_CHECK(env1) (1)
69 #define QT0 (env->qt0)
70 #define QT1 (env->qt1)
72 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
73 /* Calculates TSB pointer value for fault page size
74 * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers
75 * UA2005 holds the page size configuration in mmu_ctx registers */
76 static uint64_t ultrasparc_tsb_pointer(CPUSPARCState
*env
,
77 const SparcV9MMU
*mmu
, const int idx
)
79 uint64_t tsb_register
;
81 if (cpu_has_hypervisor(env
)) {
83 int ctx
= mmu
->tag_access
& 0x1fffULL
;
84 uint64_t ctx_register
= mmu
->sun4v_ctx_config
[ctx
? 1 : 0];
86 tsb_index
|= ctx
? 2 : 0;
87 page_size
= idx
? ctx_register
>> 8 : ctx_register
;
89 tsb_register
= mmu
->sun4v_tsb_pointers
[tsb_index
];
92 tsb_register
= mmu
->tsb
;
94 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
95 int tsb_size
= tsb_register
& 0xf;
97 uint64_t tsb_base_mask
= (~0x1fffULL
) << tsb_size
;
99 /* move va bits to correct position,
100 * the context bits will be masked out later */
101 uint64_t va
= mmu
->tag_access
>> (3 * page_size
+ 9);
103 /* calculate tsb_base mask and adjust va if split is in use */
106 va
&= ~(1ULL << (13 + tsb_size
));
108 va
|= (1ULL << (13 + tsb_size
));
113 return ((tsb_register
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
116 /* Calculates tag target register value by reordering bits
117 in tag access register */
118 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
120 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
123 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
124 uint64_t tlb_tag
, uint64_t tlb_tte
,
127 target_ulong mask
, size
, va
, offset
;
129 /* flush page range if translation is valid */
130 if (TTE_IS_VALID(tlb
->tte
)) {
131 CPUState
*cs
= env_cpu(env
);
133 size
= 8192ULL << 3 * TTE_PGSIZE(tlb
->tte
);
136 va
= tlb
->tag
& mask
;
138 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
139 tlb_flush_page(cs
, va
+ offset
);
147 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
148 const char *strmmu
, CPUSPARCState
*env1
)
154 int is_demap_context
= (demap_addr
>> 6) & 1;
157 switch ((demap_addr
>> 4) & 3) {
158 case 0: /* primary */
159 context
= env1
->dmmu
.mmu_primary_context
;
161 case 1: /* secondary */
162 context
= env1
->dmmu
.mmu_secondary_context
;
164 case 2: /* nucleus */
167 case 3: /* reserved */
172 for (i
= 0; i
< 64; i
++) {
173 if (TTE_IS_VALID(tlb
[i
].tte
)) {
175 if (is_demap_context
) {
176 /* will remove non-global entries matching context value */
177 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
178 !tlb_compare_context(&tlb
[i
], context
)) {
183 will remove any entry matching VA */
184 mask
= 0xffffffffffffe000ULL
;
185 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
187 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
191 /* entry should be global or matching context value */
192 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
193 !tlb_compare_context(&tlb
[i
], context
)) {
198 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
200 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
207 static uint64_t sun4v_tte_to_sun4u(CPUSPARCState
*env
, uint64_t tag
,
211 if (!(cpu_has_hypervisor(env
) && (tag
& TLB_UST1_IS_SUN4V_BIT
))) {
212 /* is already in the sun4u format */
215 sun4u_tte
= TTE_PA(sun4v_tte
) | (sun4v_tte
& TTE_VALID_BIT
);
216 sun4u_tte
|= (sun4v_tte
& 3ULL) << 61; /* TTE_PGSIZE */
217 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_NFO_BIT_UA2005
, TTE_NFO_BIT
);
218 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_USED_BIT_UA2005
, TTE_USED_BIT
);
219 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_W_OK_BIT_UA2005
, TTE_W_OK_BIT
);
220 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_SIDEEFFECT_BIT_UA2005
,
222 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_PRIV_BIT_UA2005
, TTE_PRIV_BIT
);
223 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_LOCKED_BIT_UA2005
, TTE_LOCKED_BIT
);
227 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
228 uint64_t tlb_tag
, uint64_t tlb_tte
,
229 const char *strmmu
, CPUSPARCState
*env1
,
232 unsigned int i
, replace_used
;
234 tlb_tte
= sun4v_tte_to_sun4u(env1
, addr
, tlb_tte
);
235 if (cpu_has_hypervisor(env1
)) {
236 uint64_t new_vaddr
= tlb_tag
& ~0x1fffULL
;
237 uint64_t new_size
= 8192ULL << 3 * TTE_PGSIZE(tlb_tte
);
238 uint32_t new_ctx
= tlb_tag
& 0x1fffU
;
239 for (i
= 0; i
< 64; i
++) {
240 uint32_t ctx
= tlb
[i
].tag
& 0x1fffU
;
241 /* check if new mapping overlaps an existing one */
242 if (new_ctx
== ctx
) {
243 uint64_t vaddr
= tlb
[i
].tag
& ~0x1fffULL
;
244 uint64_t size
= 8192ULL << 3 * TTE_PGSIZE(tlb
[i
].tte
);
245 if (new_vaddr
== vaddr
246 || (new_vaddr
< vaddr
+ size
247 && vaddr
< new_vaddr
+ new_size
)) {
248 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i
, vaddr
,
250 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
257 /* Try replacing invalid entry */
258 for (i
= 0; i
< 64; i
++) {
259 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
260 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
262 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
269 /* All entries are valid, try replacing unlocked entry */
271 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
273 /* Used entries are not replaced on first pass */
275 for (i
= 0; i
< 64; i
++) {
276 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
278 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
280 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
281 strmmu
, (replace_used
? "used" : "unused"), i
);
288 /* Now reset used bit and search for unused entries again */
290 for (i
= 0; i
< 64; i
++) {
291 TTE_SET_UNUSED(tlb
[i
].tte
);
296 DPRINTF_MMU("%s lru replacement: no free entries available, "
297 "replacing the last one\n", strmmu
);
299 /* corner case: the last entry is replaced anyway */
300 replace_tlb_entry(&tlb
[63], tlb_tag
, tlb_tte
, env1
);
305 #ifdef TARGET_SPARC64
306 /* returns true if access using this ASI is to have address translated by MMU
307 otherwise access is to raw physical address */
308 /* TODO: check sparc32 bits */
309 static inline int is_translating_asi(int asi
)
311 /* Ultrasparc IIi translating asi
312 - note this list is defined by cpu implementation
329 static inline target_ulong
address_mask(CPUSPARCState
*env1
, target_ulong addr
)
331 if (AM_CHECK(env1
)) {
332 addr
&= 0xffffffffULL
;
337 static inline target_ulong
asi_address_mask(CPUSPARCState
*env
,
338 int asi
, target_ulong addr
)
340 if (is_translating_asi(asi
)) {
341 addr
= address_mask(env
, addr
);
346 #ifndef CONFIG_USER_ONLY
347 static inline void do_check_asi(CPUSPARCState
*env
, int asi
, uintptr_t ra
)
349 /* ASIs >= 0x80 are user mode.
350 * ASIs >= 0x30 are hyper mode (or super if hyper is not available).
351 * ASIs <= 0x2f are super mode.
354 && !cpu_hypervisor_mode(env
)
355 && (!cpu_supervisor_mode(env
)
356 || (asi
>= 0x30 && cpu_has_hypervisor(env
)))) {
357 cpu_raise_exception_ra(env
, TT_PRIV_ACT
, ra
);
360 #endif /* !CONFIG_USER_ONLY */
363 static void do_check_align(CPUSPARCState
*env
, target_ulong addr
,
364 uint32_t align
, uintptr_t ra
)
367 cpu_raise_exception_ra(env
, TT_UNALIGNED
, ra
);
371 void helper_check_align(CPUSPARCState
*env
, target_ulong addr
, uint32_t align
)
373 do_check_align(env
, addr
, align
, GETPC());
376 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
378 static void dump_mxcc(CPUSPARCState
*env
)
380 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
382 env
->mxccdata
[0], env
->mxccdata
[1],
383 env
->mxccdata
[2], env
->mxccdata
[3]);
384 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
386 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
388 env
->mxccregs
[0], env
->mxccregs
[1],
389 env
->mxccregs
[2], env
->mxccregs
[3],
390 env
->mxccregs
[4], env
->mxccregs
[5],
391 env
->mxccregs
[6], env
->mxccregs
[7]);
395 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
396 && defined(DEBUG_ASI)
397 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
402 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
403 addr
, asi
, r1
& 0xff);
406 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
407 addr
, asi
, r1
& 0xffff);
410 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
411 addr
, asi
, r1
& 0xffffffff);
414 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
421 #ifndef CONFIG_USER_ONLY
422 #ifndef TARGET_SPARC64
423 static void sparc_raise_mmu_fault(CPUState
*cs
, hwaddr addr
,
424 bool is_write
, bool is_exec
, int is_asi
,
425 unsigned size
, uintptr_t retaddr
)
427 SPARCCPU
*cpu
= SPARC_CPU(cs
);
428 CPUSPARCState
*env
= &cpu
->env
;
431 #ifdef DEBUG_UNASSIGNED
433 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
434 " asi 0x%02x from " TARGET_FMT_lx
"\n",
435 is_exec
? "exec" : is_write
? "write" : "read", size
,
436 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
438 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
439 " from " TARGET_FMT_lx
"\n",
440 is_exec
? "exec" : is_write
? "write" : "read", size
,
441 size
== 1 ? "" : "s", addr
, env
->pc
);
444 /* Don't overwrite translation and access faults */
445 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
446 if ((fault_type
> 4) || (fault_type
== 0)) {
447 env
->mmuregs
[3] = 0; /* Fault status register */
449 env
->mmuregs
[3] |= 1 << 16;
452 env
->mmuregs
[3] |= 1 << 5;
455 env
->mmuregs
[3] |= 1 << 6;
458 env
->mmuregs
[3] |= 1 << 7;
460 env
->mmuregs
[3] |= (5 << 2) | 2;
461 /* SuperSPARC will never place instruction fault addresses in the FAR */
463 env
->mmuregs
[4] = addr
; /* Fault address register */
466 /* overflow (same type fault was not read before another fault) */
467 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
468 env
->mmuregs
[3] |= 1;
471 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
472 int tt
= is_exec
? TT_CODE_ACCESS
: TT_DATA_ACCESS
;
473 cpu_raise_exception_ra(env
, tt
, retaddr
);
477 * flush neverland mappings created during no-fault mode,
478 * so the sequential MMU faults report proper fault types
480 if (env
->mmuregs
[0] & MMU_NF
) {
485 static void sparc_raise_mmu_fault(CPUState
*cs
, hwaddr addr
,
486 bool is_write
, bool is_exec
, int is_asi
,
487 unsigned size
, uintptr_t retaddr
)
489 SPARCCPU
*cpu
= SPARC_CPU(cs
);
490 CPUSPARCState
*env
= &cpu
->env
;
492 #ifdef DEBUG_UNASSIGNED
493 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
494 "\n", addr
, env
->pc
);
497 if (is_exec
) { /* XXX has_hypervisor */
498 if (env
->lsu
& (IMMU_E
)) {
499 cpu_raise_exception_ra(env
, TT_CODE_ACCESS
, retaddr
);
500 } else if (cpu_has_hypervisor(env
) && !(env
->hpstate
& HS_PRIV
)) {
501 cpu_raise_exception_ra(env
, TT_INSN_REAL_TRANSLATION_MISS
, retaddr
);
504 if (env
->lsu
& (DMMU_E
)) {
505 cpu_raise_exception_ra(env
, TT_DATA_ACCESS
, retaddr
);
506 } else if (cpu_has_hypervisor(env
) && !(env
->hpstate
& HS_PRIV
)) {
507 cpu_raise_exception_ra(env
, TT_DATA_REAL_TRANSLATION_MISS
, retaddr
);
514 #ifndef TARGET_SPARC64
515 #ifndef CONFIG_USER_ONLY
518 /* Leon3 cache control */
520 static void leon3_cache_control_st(CPUSPARCState
*env
, target_ulong addr
,
521 uint64_t val
, int size
)
523 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64
", size:%d\n",
527 DPRINTF_CACHE_CONTROL("32bits only\n");
532 case 0x00: /* Cache control */
534 /* These values must always be read as zeros */
535 val
&= ~CACHE_CTRL_FD
;
536 val
&= ~CACHE_CTRL_FI
;
537 val
&= ~CACHE_CTRL_IB
;
538 val
&= ~CACHE_CTRL_IP
;
539 val
&= ~CACHE_CTRL_DP
;
541 env
->cache_control
= val
;
543 case 0x04: /* Instruction cache configuration */
544 case 0x08: /* Data cache configuration */
548 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr
);
553 static uint64_t leon3_cache_control_ld(CPUSPARCState
*env
, target_ulong addr
,
559 DPRINTF_CACHE_CONTROL("32bits only\n");
564 case 0x00: /* Cache control */
565 ret
= env
->cache_control
;
568 /* Configuration registers are read and only always keep those
571 case 0x04: /* Instruction cache configuration */
574 case 0x08: /* Data cache configuration */
578 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr
);
581 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64
", size:%d\n",
586 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
,
587 int asi
, uint32_t memop
)
589 int size
= 1 << (memop
& MO_SIZE
);
590 int sign
= memop
& MO_SIGN
;
591 CPUState
*cs
= env_cpu(env
);
593 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
594 uint32_t last_addr
= addr
;
597 do_check_align(env
, addr
, size
- 1, GETPC());
599 case ASI_M_MXCC
: /* SuperSparc MXCC registers, or... */
600 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
602 case 0x00: /* Leon3 Cache Control */
603 case 0x08: /* Leon3 Instruction Cache config */
604 case 0x0C: /* Leon3 Date Cache config */
605 if (env
->def
.features
& CPU_FEATURE_CACHE_CTRL
) {
606 ret
= leon3_cache_control_ld(env
, addr
, size
);
609 case 0x01c00a00: /* MXCC control register */
611 ret
= env
->mxccregs
[3];
613 qemu_log_mask(LOG_UNIMP
,
614 "%08x: unimplemented access size: %d\n", addr
,
618 case 0x01c00a04: /* MXCC control register */
620 ret
= env
->mxccregs
[3];
622 qemu_log_mask(LOG_UNIMP
,
623 "%08x: unimplemented access size: %d\n", addr
,
627 case 0x01c00c00: /* Module reset register */
629 ret
= env
->mxccregs
[5];
630 /* should we do something here? */
632 qemu_log_mask(LOG_UNIMP
,
633 "%08x: unimplemented access size: %d\n", addr
,
637 case 0x01c00f00: /* MBus port address register */
639 ret
= env
->mxccregs
[7];
641 qemu_log_mask(LOG_UNIMP
,
642 "%08x: unimplemented access size: %d\n", addr
,
647 qemu_log_mask(LOG_UNIMP
,
648 "%08x: unimplemented address, size: %d\n", addr
,
652 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
653 "addr = %08x -> ret = %" PRIx64
","
654 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
659 case ASI_M_FLUSH_PROBE
: /* SuperSparc MMU probe */
660 case ASI_LEON_MMUFLUSH
: /* LEON3 MMU probe */
664 mmulev
= (addr
>> 8) & 15;
668 ret
= mmu_probe(env
, addr
, mmulev
);
670 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
674 case ASI_M_MMUREGS
: /* SuperSparc MMU regs */
675 case ASI_LEON_MMUREGS
: /* LEON3 MMU regs */
677 int reg
= (addr
>> 8) & 0x1f;
679 ret
= env
->mmuregs
[reg
];
680 if (reg
== 3) { /* Fault status cleared on read */
682 } else if (reg
== 0x13) { /* Fault status read */
683 ret
= env
->mmuregs
[3];
684 } else if (reg
== 0x14) { /* Fault address read */
685 ret
= env
->mmuregs
[4];
687 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
690 case ASI_M_TLBDIAG
: /* Turbosparc ITLB Diagnostic */
691 case ASI_M_DIAGS
: /* Turbosparc DTLB Diagnostic */
692 case ASI_M_IODIAG
: /* Turbosparc IOTLB Diagnostic */
694 case ASI_KERNELTXT
: /* Supervisor code access */
697 ret
= cpu_ldub_code(env
, addr
);
700 ret
= cpu_lduw_code(env
, addr
);
704 ret
= cpu_ldl_code(env
, addr
);
707 ret
= cpu_ldq_code(env
, addr
);
711 case ASI_M_TXTC_TAG
: /* SparcStation 5 I-cache tag */
712 case ASI_M_TXTC_DATA
: /* SparcStation 5 I-cache data */
713 case ASI_M_DATAC_TAG
: /* SparcStation 5 D-cache tag */
714 case ASI_M_DATAC_DATA
: /* SparcStation 5 D-cache data */
716 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
719 hwaddr access_addr
= (hwaddr
)addr
| ((hwaddr
)(asi
& 0xf) << 32);
723 ret
= address_space_ldub(cs
->as
, access_addr
,
724 MEMTXATTRS_UNSPECIFIED
, &result
);
727 ret
= address_space_lduw(cs
->as
, access_addr
,
728 MEMTXATTRS_UNSPECIFIED
, &result
);
732 ret
= address_space_ldl(cs
->as
, access_addr
,
733 MEMTXATTRS_UNSPECIFIED
, &result
);
736 ret
= address_space_ldq(cs
->as
, access_addr
,
737 MEMTXATTRS_UNSPECIFIED
, &result
);
741 if (result
!= MEMTX_OK
) {
742 sparc_raise_mmu_fault(cs
, access_addr
, false, false, false,
747 case 0x30: /* Turbosparc secondary cache diagnostic */
748 case 0x31: /* Turbosparc RAM snoop */
749 case 0x32: /* Turbosparc page table descriptor diagnostic */
750 case 0x39: /* data cache diagnostic register */
753 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
755 int reg
= (addr
>> 8) & 3;
758 case 0: /* Breakpoint Value (Addr) */
759 ret
= env
->mmubpregs
[reg
];
761 case 1: /* Breakpoint Mask */
762 ret
= env
->mmubpregs
[reg
];
764 case 2: /* Breakpoint Control */
765 ret
= env
->mmubpregs
[reg
];
767 case 3: /* Breakpoint Status */
768 ret
= env
->mmubpregs
[reg
];
769 env
->mmubpregs
[reg
] = 0ULL;
772 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
776 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
777 ret
= env
->mmubpctrv
;
779 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
780 ret
= env
->mmubpctrc
;
782 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
783 ret
= env
->mmubpctrs
;
785 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
786 ret
= env
->mmubpaction
;
788 case ASI_USERTXT
: /* User code access, XXX */
790 sparc_raise_mmu_fault(cs
, addr
, false, false, asi
, size
, GETPC());
794 case ASI_USERDATA
: /* User data access */
795 case ASI_KERNELDATA
: /* Supervisor data access */
796 case ASI_P
: /* Implicit primary context data access (v9 only?) */
797 case ASI_M_BYPASS
: /* MMU passthrough */
798 case ASI_LEON_BYPASS
: /* LEON MMU passthrough */
799 /* These are always handled inline. */
800 g_assert_not_reached();
818 dump_asi("read ", last_addr
, asi
, size
, ret
);
823 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, uint64_t val
,
824 int asi
, uint32_t memop
)
826 int size
= 1 << (memop
& MO_SIZE
);
827 CPUState
*cs
= env_cpu(env
);
829 do_check_align(env
, addr
, size
- 1, GETPC());
831 case ASI_M_MXCC
: /* SuperSparc MXCC registers, or... */
832 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
834 case 0x00: /* Leon3 Cache Control */
835 case 0x08: /* Leon3 Instruction Cache config */
836 case 0x0C: /* Leon3 Date Cache config */
837 if (env
->def
.features
& CPU_FEATURE_CACHE_CTRL
) {
838 leon3_cache_control_st(env
, addr
, val
, size
);
842 case 0x01c00000: /* MXCC stream data register 0 */
844 env
->mxccdata
[0] = val
;
846 qemu_log_mask(LOG_UNIMP
,
847 "%08x: unimplemented access size: %d\n", addr
,
851 case 0x01c00008: /* MXCC stream data register 1 */
853 env
->mxccdata
[1] = val
;
855 qemu_log_mask(LOG_UNIMP
,
856 "%08x: unimplemented access size: %d\n", addr
,
860 case 0x01c00010: /* MXCC stream data register 2 */
862 env
->mxccdata
[2] = val
;
864 qemu_log_mask(LOG_UNIMP
,
865 "%08x: unimplemented access size: %d\n", addr
,
869 case 0x01c00018: /* MXCC stream data register 3 */
871 env
->mxccdata
[3] = val
;
873 qemu_log_mask(LOG_UNIMP
,
874 "%08x: unimplemented access size: %d\n", addr
,
878 case 0x01c00100: /* MXCC stream source */
883 env
->mxccregs
[0] = val
;
885 qemu_log_mask(LOG_UNIMP
,
886 "%08x: unimplemented access size: %d\n", addr
,
890 for (i
= 0; i
< 4; i
++) {
892 hwaddr access_addr
= (env
->mxccregs
[0] & 0xffffffffULL
) + 8 * i
;
894 env
->mxccdata
[i
] = address_space_ldq(cs
->as
,
896 MEMTXATTRS_UNSPECIFIED
,
898 if (result
!= MEMTX_OK
) {
899 /* TODO: investigate whether this is the right behaviour */
900 sparc_raise_mmu_fault(cs
, access_addr
, false, false,
901 false, size
, GETPC());
906 case 0x01c00200: /* MXCC stream destination */
911 env
->mxccregs
[1] = val
;
913 qemu_log_mask(LOG_UNIMP
,
914 "%08x: unimplemented access size: %d\n", addr
,
918 for (i
= 0; i
< 4; i
++) {
920 hwaddr access_addr
= (env
->mxccregs
[1] & 0xffffffffULL
) + 8 * i
;
922 address_space_stq(cs
->as
, access_addr
, env
->mxccdata
[i
],
923 MEMTXATTRS_UNSPECIFIED
, &result
);
925 if (result
!= MEMTX_OK
) {
926 /* TODO: investigate whether this is the right behaviour */
927 sparc_raise_mmu_fault(cs
, access_addr
, true, false,
928 false, size
, GETPC());
933 case 0x01c00a00: /* MXCC control register */
935 env
->mxccregs
[3] = val
;
937 qemu_log_mask(LOG_UNIMP
,
938 "%08x: unimplemented access size: %d\n", addr
,
942 case 0x01c00a04: /* MXCC control register */
944 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
947 qemu_log_mask(LOG_UNIMP
,
948 "%08x: unimplemented access size: %d\n", addr
,
952 case 0x01c00e00: /* MXCC error register */
953 /* writing a 1 bit clears the error */
955 env
->mxccregs
[6] &= ~val
;
957 qemu_log_mask(LOG_UNIMP
,
958 "%08x: unimplemented access size: %d\n", addr
,
962 case 0x01c00f00: /* MBus port address register */
964 env
->mxccregs
[7] = val
;
966 qemu_log_mask(LOG_UNIMP
,
967 "%08x: unimplemented access size: %d\n", addr
,
972 qemu_log_mask(LOG_UNIMP
,
973 "%08x: unimplemented address, size: %d\n", addr
,
977 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
978 asi
, size
, addr
, val
);
983 case ASI_M_FLUSH_PROBE
: /* SuperSparc MMU flush */
984 case ASI_LEON_MMUFLUSH
: /* LEON3 MMU flush */
988 mmulev
= (addr
>> 8) & 15;
989 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
991 case 0: /* flush page */
992 tlb_flush_page(cs
, addr
& 0xfffff000);
994 case 1: /* flush segment (256k) */
995 case 2: /* flush region (16M) */
996 case 3: /* flush context (4G) */
997 case 4: /* flush entire */
1008 case ASI_M_MMUREGS
: /* write MMU regs */
1009 case ASI_LEON_MMUREGS
: /* LEON3 write MMU regs */
1011 int reg
= (addr
>> 8) & 0x1f;
1014 oldreg
= env
->mmuregs
[reg
];
1016 case 0: /* Control Register */
1017 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
1019 /* Mappings generated during no-fault mode
1020 are invalid in normal mode. */
1021 if ((oldreg
^ env
->mmuregs
[reg
])
1022 & (MMU_NF
| env
->def
.mmu_bm
)) {
1026 case 1: /* Context Table Pointer Register */
1027 env
->mmuregs
[reg
] = val
& env
->def
.mmu_ctpr_mask
;
1029 case 2: /* Context Register */
1030 env
->mmuregs
[reg
] = val
& env
->def
.mmu_cxr_mask
;
1031 if (oldreg
!= env
->mmuregs
[reg
]) {
1032 /* we flush when the MMU context changes because
1033 QEMU has no MMU context support */
1037 case 3: /* Synchronous Fault Status Register with Clear */
1038 case 4: /* Synchronous Fault Address Register */
1040 case 0x10: /* TLB Replacement Control Register */
1041 env
->mmuregs
[reg
] = val
& env
->def
.mmu_trcr_mask
;
1043 case 0x13: /* Synchronous Fault Status Register with Read
1045 env
->mmuregs
[3] = val
& env
->def
.mmu_sfsr_mask
;
1047 case 0x14: /* Synchronous Fault Address Register */
1048 env
->mmuregs
[4] = val
;
1051 env
->mmuregs
[reg
] = val
;
1054 if (oldreg
!= env
->mmuregs
[reg
]) {
1055 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1056 reg
, oldreg
, env
->mmuregs
[reg
]);
1063 case ASI_M_TLBDIAG
: /* Turbosparc ITLB Diagnostic */
1064 case ASI_M_DIAGS
: /* Turbosparc DTLB Diagnostic */
1065 case ASI_M_IODIAG
: /* Turbosparc IOTLB Diagnostic */
1067 case ASI_M_TXTC_TAG
: /* I-cache tag */
1068 case ASI_M_TXTC_DATA
: /* I-cache data */
1069 case ASI_M_DATAC_TAG
: /* D-cache tag */
1070 case ASI_M_DATAC_DATA
: /* D-cache data */
1071 case ASI_M_FLUSH_PAGE
: /* I/D-cache flush page */
1072 case ASI_M_FLUSH_SEG
: /* I/D-cache flush segment */
1073 case ASI_M_FLUSH_REGION
: /* I/D-cache flush region */
1074 case ASI_M_FLUSH_CTX
: /* I/D-cache flush context */
1075 case ASI_M_FLUSH_USER
: /* I/D-cache flush user */
1077 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1080 hwaddr access_addr
= (hwaddr
)addr
| ((hwaddr
)(asi
& 0xf) << 32);
1084 address_space_stb(cs
->as
, access_addr
, val
,
1085 MEMTXATTRS_UNSPECIFIED
, &result
);
1088 address_space_stw(cs
->as
, access_addr
, val
,
1089 MEMTXATTRS_UNSPECIFIED
, &result
);
1093 address_space_stl(cs
->as
, access_addr
, val
,
1094 MEMTXATTRS_UNSPECIFIED
, &result
);
1097 address_space_stq(cs
->as
, access_addr
, val
,
1098 MEMTXATTRS_UNSPECIFIED
, &result
);
1101 if (result
!= MEMTX_OK
) {
1102 sparc_raise_mmu_fault(cs
, access_addr
, true, false, false,
1107 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1108 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1109 Turbosparc snoop RAM */
1110 case 0x32: /* store buffer control or Turbosparc page table
1111 descriptor diagnostic */
1112 case 0x36: /* I-cache flash clear */
1113 case 0x37: /* D-cache flash clear */
1115 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1117 int reg
= (addr
>> 8) & 3;
1120 case 0: /* Breakpoint Value (Addr) */
1121 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1123 case 1: /* Breakpoint Mask */
1124 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1126 case 2: /* Breakpoint Control */
1127 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
1129 case 3: /* Breakpoint Status */
1130 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
1133 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
1137 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1138 env
->mmubpctrv
= val
& 0xffffffff;
1140 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1141 env
->mmubpctrc
= val
& 0x3;
1143 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1144 env
->mmubpctrs
= val
& 0x3;
1146 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1147 env
->mmubpaction
= val
& 0x1fff;
1149 case ASI_USERTXT
: /* User code access, XXX */
1150 case ASI_KERNELTXT
: /* Supervisor code access, XXX */
1152 sparc_raise_mmu_fault(cs
, addr
, true, false, asi
, size
, GETPC());
1155 case ASI_USERDATA
: /* User data access */
1156 case ASI_KERNELDATA
: /* Supervisor data access */
1158 case ASI_M_BYPASS
: /* MMU passthrough */
1159 case ASI_LEON_BYPASS
: /* LEON MMU passthrough */
1160 case ASI_M_BCOPY
: /* Block copy, sta access */
1161 case ASI_M_BFILL
: /* Block fill, stda access */
1162 /* These are always handled inline. */
1163 g_assert_not_reached();
1166 dump_asi("write", addr
, asi
, size
, val
);
1170 #endif /* CONFIG_USER_ONLY */
1171 #else /* TARGET_SPARC64 */
1173 #ifdef CONFIG_USER_ONLY
1174 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
,
1175 int asi
, uint32_t memop
)
1177 int size
= 1 << (memop
& MO_SIZE
);
1178 int sign
= memop
& MO_SIGN
;
1182 cpu_raise_exception_ra(env
, TT_PRIV_ACT
, GETPC());
1184 do_check_align(env
, addr
, size
- 1, GETPC());
1185 addr
= asi_address_mask(env
, asi
, addr
);
1188 case ASI_PNF
: /* Primary no-fault */
1189 case ASI_PNFL
: /* Primary no-fault LE */
1190 case ASI_SNF
: /* Secondary no-fault */
1191 case ASI_SNFL
: /* Secondary no-fault LE */
1192 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1198 ret
= cpu_ldub_data(env
, addr
);
1201 ret
= cpu_lduw_data(env
, addr
);
1204 ret
= cpu_ldl_data(env
, addr
);
1207 ret
= cpu_ldq_data(env
, addr
);
1210 g_assert_not_reached();
1215 case ASI_P
: /* Primary */
1216 case ASI_PL
: /* Primary LE */
1217 case ASI_S
: /* Secondary */
1218 case ASI_SL
: /* Secondary LE */
1219 /* These are always handled inline. */
1220 g_assert_not_reached();
1223 cpu_raise_exception_ra(env
, TT_DATA_ACCESS
, GETPC());
1226 /* Convert from little endian */
1228 case ASI_PNFL
: /* Primary no-fault LE */
1229 case ASI_SNFL
: /* Secondary no-fault LE */
1243 /* Convert to signed number */
1250 ret
= (int16_t) ret
;
1253 ret
= (int32_t) ret
;
1258 dump_asi("read", addr
, asi
, size
, ret
);
1263 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1264 int asi
, uint32_t memop
)
1266 int size
= 1 << (memop
& MO_SIZE
);
1268 dump_asi("write", addr
, asi
, size
, val
);
1271 cpu_raise_exception_ra(env
, TT_PRIV_ACT
, GETPC());
1273 do_check_align(env
, addr
, size
- 1, GETPC());
1276 case ASI_P
: /* Primary */
1277 case ASI_PL
: /* Primary LE */
1278 case ASI_S
: /* Secondary */
1279 case ASI_SL
: /* Secondary LE */
1280 /* These are always handled inline. */
1281 g_assert_not_reached();
1283 case ASI_PNF
: /* Primary no-fault, RO */
1284 case ASI_SNF
: /* Secondary no-fault, RO */
1285 case ASI_PNFL
: /* Primary no-fault LE, RO */
1286 case ASI_SNFL
: /* Secondary no-fault LE, RO */
1288 cpu_raise_exception_ra(env
, TT_DATA_ACCESS
, GETPC());
1292 #else /* CONFIG_USER_ONLY */
1294 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
,
1295 int asi
, uint32_t memop
)
1297 int size
= 1 << (memop
& MO_SIZE
);
1298 int sign
= memop
& MO_SIGN
;
1299 CPUState
*cs
= env_cpu(env
);
1301 #if defined(DEBUG_ASI)
1302 target_ulong last_addr
= addr
;
1307 do_check_asi(env
, asi
, GETPC());
1308 do_check_align(env
, addr
, size
- 1, GETPC());
1309 addr
= asi_address_mask(env
, asi
, addr
);
1318 int idx
= (env
->pstate
& PS_PRIV
1319 ? (asi
& 1 ? MMU_KERNEL_SECONDARY_IDX
: MMU_KERNEL_IDX
)
1320 : (asi
& 1 ? MMU_USER_SECONDARY_IDX
: MMU_USER_IDX
));
1322 if (cpu_get_phys_page_nofault(env
, addr
, idx
) == -1ULL) {
1324 dump_asi("read ", last_addr
, asi
, size
, ret
);
1326 /* exception_index is set in get_physical_address_data. */
1327 cpu_raise_exception_ra(env
, cs
->exception_index
, GETPC());
1329 oi
= make_memop_idx(memop
, idx
);
1332 ret
= cpu_ldb_mmu(env
, addr
, oi
, GETPC());
1336 ret
= cpu_ldw_le_mmu(env
, addr
, oi
, GETPC());
1338 ret
= cpu_ldw_be_mmu(env
, addr
, oi
, GETPC());
1343 ret
= cpu_ldl_le_mmu(env
, addr
, oi
, GETPC());
1345 ret
= cpu_ldl_be_mmu(env
, addr
, oi
, GETPC());
1350 ret
= cpu_ldq_le_mmu(env
, addr
, oi
, GETPC());
1352 ret
= cpu_ldq_be_mmu(env
, addr
, oi
, GETPC());
1356 g_assert_not_reached();
1361 case ASI_AIUP
: /* As if user primary */
1362 case ASI_AIUS
: /* As if user secondary */
1363 case ASI_AIUPL
: /* As if user primary LE */
1364 case ASI_AIUSL
: /* As if user secondary LE */
1365 case ASI_P
: /* Primary */
1366 case ASI_S
: /* Secondary */
1367 case ASI_PL
: /* Primary LE */
1368 case ASI_SL
: /* Secondary LE */
1369 case ASI_REAL
: /* Bypass */
1370 case ASI_REAL_IO
: /* Bypass, non-cacheable */
1371 case ASI_REAL_L
: /* Bypass LE */
1372 case ASI_REAL_IO_L
: /* Bypass, non-cacheable LE */
1373 case ASI_N
: /* Nucleus */
1374 case ASI_NL
: /* Nucleus Little Endian (LE) */
1375 case ASI_NUCLEUS_QUAD_LDD
: /* Nucleus quad LDD 128 bit atomic */
1376 case ASI_NUCLEUS_QUAD_LDD_L
: /* Nucleus quad LDD 128 bit atomic LE */
1377 case ASI_TWINX_AIUP
: /* As if user primary, twinx */
1378 case ASI_TWINX_AIUS
: /* As if user secondary, twinx */
1379 case ASI_TWINX_REAL
: /* Real address, twinx */
1380 case ASI_TWINX_AIUP_L
: /* As if user primary, twinx, LE */
1381 case ASI_TWINX_AIUS_L
: /* As if user secondary, twinx, LE */
1382 case ASI_TWINX_REAL_L
: /* Real address, twinx, LE */
1383 case ASI_TWINX_N
: /* Nucleus, twinx */
1384 case ASI_TWINX_NL
: /* Nucleus, twinx, LE */
1385 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1386 case ASI_TWINX_P
: /* Primary, twinx */
1387 case ASI_TWINX_PL
: /* Primary, twinx, LE */
1388 case ASI_TWINX_S
: /* Secondary, twinx */
1389 case ASI_TWINX_SL
: /* Secondary, twinx, LE */
1390 /* These are always handled inline. */
1391 g_assert_not_reached();
1393 case ASI_UPA_CONFIG
: /* UPA config */
1396 case ASI_LSU_CONTROL
: /* LSU */
1399 case ASI_IMMU
: /* I-MMU regs */
1401 int reg
= (addr
>> 3) & 0xf;
1404 /* 0x00 I-TSB Tag Target register */
1405 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
1408 ret
= env
->immu
.sfsr
;
1410 case 5: /* TSB access */
1411 ret
= env
->immu
.tsb
;
1414 /* 0x30 I-TSB Tag Access register */
1415 ret
= env
->immu
.tag_access
;
1418 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1423 case ASI_IMMU_TSB_8KB_PTR
: /* I-MMU 8k TSB pointer */
1425 /* env->immuregs[5] holds I-MMU TSB register value
1426 env->immuregs[6] holds I-MMU Tag Access register value */
1427 ret
= ultrasparc_tsb_pointer(env
, &env
->immu
, 0);
1430 case ASI_IMMU_TSB_64KB_PTR
: /* I-MMU 64k TSB pointer */
1432 /* env->immuregs[5] holds I-MMU TSB register value
1433 env->immuregs[6] holds I-MMU Tag Access register value */
1434 ret
= ultrasparc_tsb_pointer(env
, &env
->immu
, 1);
1437 case ASI_ITLB_DATA_ACCESS
: /* I-MMU data access */
1439 int reg
= (addr
>> 3) & 0x3f;
1441 ret
= env
->itlb
[reg
].tte
;
1444 case ASI_ITLB_TAG_READ
: /* I-MMU tag read */
1446 int reg
= (addr
>> 3) & 0x3f;
1448 ret
= env
->itlb
[reg
].tag
;
1451 case ASI_DMMU
: /* D-MMU regs */
1453 int reg
= (addr
>> 3) & 0xf;
1456 /* 0x00 D-TSB Tag Target register */
1457 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
1459 case 1: /* 0x08 Primary Context */
1460 ret
= env
->dmmu
.mmu_primary_context
;
1462 case 2: /* 0x10 Secondary Context */
1463 ret
= env
->dmmu
.mmu_secondary_context
;
1466 ret
= env
->dmmu
.sfsr
;
1468 case 4: /* 0x20 SFAR */
1469 ret
= env
->dmmu
.sfar
;
1471 case 5: /* 0x28 TSB access */
1472 ret
= env
->dmmu
.tsb
;
1474 case 6: /* 0x30 D-TSB Tag Access register */
1475 ret
= env
->dmmu
.tag_access
;
1478 ret
= env
->dmmu
.virtual_watchpoint
;
1481 ret
= env
->dmmu
.physical_watchpoint
;
1484 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1489 case ASI_DMMU_TSB_8KB_PTR
: /* D-MMU 8k TSB pointer */
1491 /* env->dmmuregs[5] holds D-MMU TSB register value
1492 env->dmmuregs[6] holds D-MMU Tag Access register value */
1493 ret
= ultrasparc_tsb_pointer(env
, &env
->dmmu
, 0);
1496 case ASI_DMMU_TSB_64KB_PTR
: /* D-MMU 64k TSB pointer */
1498 /* env->dmmuregs[5] holds D-MMU TSB register value
1499 env->dmmuregs[6] holds D-MMU Tag Access register value */
1500 ret
= ultrasparc_tsb_pointer(env
, &env
->dmmu
, 1);
1503 case ASI_DTLB_DATA_ACCESS
: /* D-MMU data access */
1505 int reg
= (addr
>> 3) & 0x3f;
1507 ret
= env
->dtlb
[reg
].tte
;
1510 case ASI_DTLB_TAG_READ
: /* D-MMU tag read */
1512 int reg
= (addr
>> 3) & 0x3f;
1514 ret
= env
->dtlb
[reg
].tag
;
1517 case ASI_INTR_DISPATCH_STAT
: /* Interrupt dispatch, RO */
1519 case ASI_INTR_RECEIVE
: /* Interrupt data receive */
1520 ret
= env
->ivec_status
;
1522 case ASI_INTR_R
: /* Incoming interrupt vector, RO */
1524 int reg
= (addr
>> 4) & 0x3;
1526 ret
= env
->ivec_data
[reg
];
1530 case ASI_SCRATCHPAD
: /* UA2005 privileged scratchpad */
1531 if (unlikely((addr
>= 0x20) && (addr
< 0x30))) {
1532 /* Hyperprivileged access only */
1533 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1536 case ASI_HYP_SCRATCHPAD
: /* UA2005 hyperprivileged scratchpad */
1538 unsigned int i
= (addr
>> 3) & 0x7;
1539 ret
= env
->scratch
[i
];
1542 case ASI_MMU
: /* UA2005 Context ID registers */
1543 switch ((addr
>> 3) & 0x3) {
1545 ret
= env
->dmmu
.mmu_primary_context
;
1548 ret
= env
->dmmu
.mmu_secondary_context
;
1551 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1554 case ASI_DCACHE_DATA
: /* D-cache data */
1555 case ASI_DCACHE_TAG
: /* D-cache tag access */
1556 case ASI_ESTATE_ERROR_EN
: /* E-cache error enable */
1557 case ASI_AFSR
: /* E-cache asynchronous fault status */
1558 case ASI_AFAR
: /* E-cache asynchronous fault address */
1559 case ASI_EC_TAG_DATA
: /* E-cache tag data */
1560 case ASI_IC_INSTR
: /* I-cache instruction access */
1561 case ASI_IC_TAG
: /* I-cache tag access */
1562 case ASI_IC_PRE_DECODE
: /* I-cache predecode */
1563 case ASI_IC_NEXT_FIELD
: /* I-cache LRU etc. */
1564 case ASI_EC_W
: /* E-cache tag */
1565 case ASI_EC_R
: /* E-cache tag */
1567 case ASI_DMMU_TSB_DIRECT_PTR
: /* D-MMU data pointer */
1568 case ASI_ITLB_DATA_IN
: /* I-MMU data in, WO */
1569 case ASI_IMMU_DEMAP
: /* I-MMU demap, WO */
1570 case ASI_DTLB_DATA_IN
: /* D-MMU data in, WO */
1571 case ASI_DMMU_DEMAP
: /* D-MMU demap, WO */
1572 case ASI_INTR_W
: /* Interrupt vector, WO */
1574 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1579 /* Convert to signed number */
1586 ret
= (int16_t) ret
;
1589 ret
= (int32_t) ret
;
1596 dump_asi("read ", last_addr
, asi
, size
, ret
);
1601 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1602 int asi
, uint32_t memop
)
1604 int size
= 1 << (memop
& MO_SIZE
);
1605 CPUState
*cs
= env_cpu(env
);
1608 dump_asi("write", addr
, asi
, size
, val
);
1613 do_check_asi(env
, asi
, GETPC());
1614 do_check_align(env
, addr
, size
- 1, GETPC());
1615 addr
= asi_address_mask(env
, asi
, addr
);
1618 case ASI_AIUP
: /* As if user primary */
1619 case ASI_AIUS
: /* As if user secondary */
1620 case ASI_AIUPL
: /* As if user primary LE */
1621 case ASI_AIUSL
: /* As if user secondary LE */
1622 case ASI_P
: /* Primary */
1623 case ASI_S
: /* Secondary */
1624 case ASI_PL
: /* Primary LE */
1625 case ASI_SL
: /* Secondary LE */
1626 case ASI_REAL
: /* Bypass */
1627 case ASI_REAL_IO
: /* Bypass, non-cacheable */
1628 case ASI_REAL_L
: /* Bypass LE */
1629 case ASI_REAL_IO_L
: /* Bypass, non-cacheable LE */
1630 case ASI_N
: /* Nucleus */
1631 case ASI_NL
: /* Nucleus Little Endian (LE) */
1632 case ASI_NUCLEUS_QUAD_LDD
: /* Nucleus quad LDD 128 bit atomic */
1633 case ASI_NUCLEUS_QUAD_LDD_L
: /* Nucleus quad LDD 128 bit atomic LE */
1634 case ASI_TWINX_AIUP
: /* As if user primary, twinx */
1635 case ASI_TWINX_AIUS
: /* As if user secondary, twinx */
1636 case ASI_TWINX_REAL
: /* Real address, twinx */
1637 case ASI_TWINX_AIUP_L
: /* As if user primary, twinx, LE */
1638 case ASI_TWINX_AIUS_L
: /* As if user secondary, twinx, LE */
1639 case ASI_TWINX_REAL_L
: /* Real address, twinx, LE */
1640 case ASI_TWINX_N
: /* Nucleus, twinx */
1641 case ASI_TWINX_NL
: /* Nucleus, twinx, LE */
1642 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1643 case ASI_TWINX_P
: /* Primary, twinx */
1644 case ASI_TWINX_PL
: /* Primary, twinx, LE */
1645 case ASI_TWINX_S
: /* Secondary, twinx */
1646 case ASI_TWINX_SL
: /* Secondary, twinx, LE */
1647 /* These are always handled inline. */
1648 g_assert_not_reached();
1649 /* these ASIs have different functions on UltraSPARC-IIIi
1650 * and UA2005 CPUs. Use the explicit numbers to avoid confusion
1656 if (cpu_has_hypervisor(env
)) {
1658 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS0
1659 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS1
1660 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0
1661 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1
1663 int idx
= ((asi
& 2) >> 1) | ((asi
& 8) >> 2);
1664 env
->dmmu
.sun4v_tsb_pointers
[idx
] = val
;
1666 helper_raise_exception(env
, TT_ILL_INSN
);
1671 if (cpu_has_hypervisor(env
)) {
1673 * ASI_DMMU_CTX_ZERO_CONFIG
1674 * ASI_DMMU_CTX_NONZERO_CONFIG
1676 env
->dmmu
.sun4v_ctx_config
[(asi
& 8) >> 3] = val
;
1678 helper_raise_exception(env
, TT_ILL_INSN
);
1685 if (cpu_has_hypervisor(env
)) {
1687 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS0
1688 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS1
1689 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0
1690 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1
1692 int idx
= ((asi
& 2) >> 1) | ((asi
& 8) >> 2);
1693 env
->immu
.sun4v_tsb_pointers
[idx
] = val
;
1695 helper_raise_exception(env
, TT_ILL_INSN
);
1700 if (cpu_has_hypervisor(env
)) {
1702 * ASI_IMMU_CTX_ZERO_CONFIG
1703 * ASI_IMMU_CTX_NONZERO_CONFIG
1705 env
->immu
.sun4v_ctx_config
[(asi
& 8) >> 3] = val
;
1707 helper_raise_exception(env
, TT_ILL_INSN
);
1710 case ASI_UPA_CONFIG
: /* UPA config */
1713 case ASI_LSU_CONTROL
: /* LSU */
1714 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
1716 case ASI_IMMU
: /* I-MMU regs */
1718 int reg
= (addr
>> 3) & 0xf;
1721 oldreg
= env
->immu
.mmuregs
[reg
];
1725 case 1: /* Not in I-MMU */
1729 if ((val
& 1) == 0) {
1730 val
= 0; /* Clear SFSR */
1732 env
->immu
.sfsr
= val
;
1736 case 5: /* TSB access */
1737 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
1738 PRIx64
"\n", env
->immu
.tsb
, val
);
1739 env
->immu
.tsb
= val
;
1741 case 6: /* Tag access */
1742 env
->immu
.tag_access
= val
;
1748 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1752 if (oldreg
!= env
->immu
.mmuregs
[reg
]) {
1753 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1754 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
1761 case ASI_ITLB_DATA_IN
: /* I-MMU data in */
1762 /* ignore real translation entries */
1763 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1764 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
,
1765 val
, "immu", env
, addr
);
1768 case ASI_ITLB_DATA_ACCESS
: /* I-MMU data access */
1770 /* TODO: auto demap */
1772 unsigned int i
= (addr
>> 3) & 0x3f;
1774 /* ignore real translation entries */
1775 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1776 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
,
1777 sun4v_tte_to_sun4u(env
, addr
, val
), env
);
1780 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
1785 case ASI_IMMU_DEMAP
: /* I-MMU demap */
1786 demap_tlb(env
->itlb
, addr
, "immu", env
);
1788 case ASI_DMMU
: /* D-MMU regs */
1790 int reg
= (addr
>> 3) & 0xf;
1793 oldreg
= env
->dmmu
.mmuregs
[reg
];
1799 if ((val
& 1) == 0) {
1800 val
= 0; /* Clear SFSR, Fault address */
1803 env
->dmmu
.sfsr
= val
;
1805 case 1: /* Primary context */
1806 env
->dmmu
.mmu_primary_context
= val
;
1807 /* can be optimized to only flush MMU_USER_IDX
1808 and MMU_KERNEL_IDX entries */
1811 case 2: /* Secondary context */
1812 env
->dmmu
.mmu_secondary_context
= val
;
1813 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1814 and MMU_KERNEL_SECONDARY_IDX entries */
1817 case 5: /* TSB access */
1818 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
1819 PRIx64
"\n", env
->dmmu
.tsb
, val
);
1820 env
->dmmu
.tsb
= val
;
1822 case 6: /* Tag access */
1823 env
->dmmu
.tag_access
= val
;
1825 case 7: /* Virtual Watchpoint */
1826 env
->dmmu
.virtual_watchpoint
= val
;
1828 case 8: /* Physical Watchpoint */
1829 env
->dmmu
.physical_watchpoint
= val
;
1832 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1836 if (oldreg
!= env
->dmmu
.mmuregs
[reg
]) {
1837 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1838 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
1845 case ASI_DTLB_DATA_IN
: /* D-MMU data in */
1846 /* ignore real translation entries */
1847 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1848 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
,
1849 val
, "dmmu", env
, addr
);
1852 case ASI_DTLB_DATA_ACCESS
: /* D-MMU data access */
1854 unsigned int i
= (addr
>> 3) & 0x3f;
1856 /* ignore real translation entries */
1857 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1858 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
,
1859 sun4v_tte_to_sun4u(env
, addr
, val
), env
);
1862 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
1867 case ASI_DMMU_DEMAP
: /* D-MMU demap */
1868 demap_tlb(env
->dtlb
, addr
, "dmmu", env
);
1870 case ASI_INTR_RECEIVE
: /* Interrupt data receive */
1871 env
->ivec_status
= val
& 0x20;
1873 case ASI_SCRATCHPAD
: /* UA2005 privileged scratchpad */
1874 if (unlikely((addr
>= 0x20) && (addr
< 0x30))) {
1875 /* Hyperprivileged access only */
1876 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1879 case ASI_HYP_SCRATCHPAD
: /* UA2005 hyperprivileged scratchpad */
1881 unsigned int i
= (addr
>> 3) & 0x7;
1882 env
->scratch
[i
] = val
;
1885 case ASI_MMU
: /* UA2005 Context ID registers */
1887 switch ((addr
>> 3) & 0x3) {
1889 env
->dmmu
.mmu_primary_context
= val
;
1890 env
->immu
.mmu_primary_context
= val
;
1891 tlb_flush_by_mmuidx(cs
,
1892 (1 << MMU_USER_IDX
) | (1 << MMU_KERNEL_IDX
));
1895 env
->dmmu
.mmu_secondary_context
= val
;
1896 env
->immu
.mmu_secondary_context
= val
;
1897 tlb_flush_by_mmuidx(cs
,
1898 (1 << MMU_USER_SECONDARY_IDX
) |
1899 (1 << MMU_KERNEL_SECONDARY_IDX
));
1902 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1906 case ASI_QUEUE
: /* UA2005 CPU mondo queue */
1907 case ASI_DCACHE_DATA
: /* D-cache data */
1908 case ASI_DCACHE_TAG
: /* D-cache tag access */
1909 case ASI_ESTATE_ERROR_EN
: /* E-cache error enable */
1910 case ASI_AFSR
: /* E-cache asynchronous fault status */
1911 case ASI_AFAR
: /* E-cache asynchronous fault address */
1912 case ASI_EC_TAG_DATA
: /* E-cache tag data */
1913 case ASI_IC_INSTR
: /* I-cache instruction access */
1914 case ASI_IC_TAG
: /* I-cache tag access */
1915 case ASI_IC_PRE_DECODE
: /* I-cache predecode */
1916 case ASI_IC_NEXT_FIELD
: /* I-cache LRU etc. */
1917 case ASI_EC_W
: /* E-cache tag */
1918 case ASI_EC_R
: /* E-cache tag */
1920 case ASI_IMMU_TSB_8KB_PTR
: /* I-MMU 8k TSB pointer, RO */
1921 case ASI_IMMU_TSB_64KB_PTR
: /* I-MMU 64k TSB pointer, RO */
1922 case ASI_ITLB_TAG_READ
: /* I-MMU tag read, RO */
1923 case ASI_DMMU_TSB_8KB_PTR
: /* D-MMU 8k TSB pointer, RO */
1924 case ASI_DMMU_TSB_64KB_PTR
: /* D-MMU 64k TSB pointer, RO */
1925 case ASI_DMMU_TSB_DIRECT_PTR
: /* D-MMU data pointer, RO */
1926 case ASI_DTLB_TAG_READ
: /* D-MMU tag read, RO */
1927 case ASI_INTR_DISPATCH_STAT
: /* Interrupt dispatch, RO */
1928 case ASI_INTR_R
: /* Incoming interrupt vector, RO */
1929 case ASI_PNF
: /* Primary no-fault, RO */
1930 case ASI_SNF
: /* Secondary no-fault, RO */
1931 case ASI_PNFL
: /* Primary no-fault LE, RO */
1932 case ASI_SNFL
: /* Secondary no-fault LE, RO */
1934 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1938 #endif /* CONFIG_USER_ONLY */
1939 #endif /* TARGET_SPARC64 */
1941 #if !defined(CONFIG_USER_ONLY)
1943 void sparc_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
1944 vaddr addr
, unsigned size
,
1945 MMUAccessType access_type
,
1946 int mmu_idx
, MemTxAttrs attrs
,
1947 MemTxResult response
, uintptr_t retaddr
)
1949 bool is_write
= access_type
== MMU_DATA_STORE
;
1950 bool is_exec
= access_type
== MMU_INST_FETCH
;
1951 bool is_asi
= false;
1953 sparc_raise_mmu_fault(cs
, physaddr
, is_write
, is_exec
,
1954 is_asi
, size
, retaddr
);