2 * PowerPC memory access emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "qemu/host-utils.h"
24 #include "qemu/main-loop.h"
25 #include "exec/helper-proto.h"
26 #include "helper_regs.h"
27 #include "exec/cpu_ldst.h"
29 #include "qemu/atomic128.h"
31 /* #define DEBUG_OP */
33 static inline bool needs_byteswap(const CPUPPCState
*env
)
36 return FIELD_EX64(env
->msr
, MSR
, LE
);
38 return !FIELD_EX64(env
->msr
, MSR
, LE
);
42 /*****************************************************************************/
43 /* Memory load and stores */
45 static inline target_ulong
addr_add(CPUPPCState
*env
, target_ulong addr
,
48 #if defined(TARGET_PPC64)
49 if (!msr_is_64bit(env
, env
->msr
)) {
50 return (uint32_t)(addr
+ arg
);
58 static void *probe_contiguous(CPUPPCState
*env
, target_ulong addr
, uint32_t nb
,
59 MMUAccessType access_type
, int mmu_idx
,
63 uint32_t nb_pg1
, nb_pg2
;
65 nb_pg1
= -(addr
| TARGET_PAGE_MASK
);
66 if (likely(nb
<= nb_pg1
)) {
67 /* The entire operation is on a single page. */
68 return probe_access(env
, addr
, nb
, access_type
, mmu_idx
, raddr
);
71 /* The operation spans two pages. */
73 host1
= probe_access(env
, addr
, nb_pg1
, access_type
, mmu_idx
, raddr
);
74 addr
= addr_add(env
, addr
, nb_pg1
);
75 host2
= probe_access(env
, addr
, nb_pg2
, access_type
, mmu_idx
, raddr
);
77 /* If the two host pages are contiguous, optimize. */
78 if (host2
== host1
+ nb_pg1
) {
84 void helper_lmw(CPUPPCState
*env
, target_ulong addr
, uint32_t reg
)
86 uintptr_t raddr
= GETPC();
87 int mmu_idx
= cpu_mmu_index(env
, false);
88 void *host
= probe_contiguous(env
, addr
, (32 - reg
) * 4,
89 MMU_DATA_LOAD
, mmu_idx
, raddr
);
92 /* Fast path -- the entire operation is in RAM at host. */
93 for (; reg
< 32; reg
++) {
94 env
->gpr
[reg
] = (uint32_t)ldl_be_p(host
);
98 /* Slow path -- at least some of the operation requires i/o. */
99 for (; reg
< 32; reg
++) {
100 env
->gpr
[reg
] = cpu_ldl_mmuidx_ra(env
, addr
, mmu_idx
, raddr
);
101 addr
= addr_add(env
, addr
, 4);
106 void helper_stmw(CPUPPCState
*env
, target_ulong addr
, uint32_t reg
)
108 uintptr_t raddr
= GETPC();
109 int mmu_idx
= cpu_mmu_index(env
, false);
110 void *host
= probe_contiguous(env
, addr
, (32 - reg
) * 4,
111 MMU_DATA_STORE
, mmu_idx
, raddr
);
114 /* Fast path -- the entire operation is in RAM at host. */
115 for (; reg
< 32; reg
++) {
116 stl_be_p(host
, env
->gpr
[reg
]);
120 /* Slow path -- at least some of the operation requires i/o. */
121 for (; reg
< 32; reg
++) {
122 cpu_stl_mmuidx_ra(env
, addr
, env
->gpr
[reg
], mmu_idx
, raddr
);
123 addr
= addr_add(env
, addr
, 4);
128 static void do_lsw(CPUPPCState
*env
, target_ulong addr
, uint32_t nb
,
129 uint32_t reg
, uintptr_t raddr
)
135 if (unlikely(nb
== 0)) {
139 mmu_idx
= cpu_mmu_index(env
, false);
140 host
= probe_contiguous(env
, addr
, nb
, MMU_DATA_LOAD
, mmu_idx
, raddr
);
143 /* Fast path -- the entire operation is in RAM at host. */
144 for (; nb
> 3; nb
-= 4) {
145 env
->gpr
[reg
] = (uint32_t)ldl_be_p(host
);
146 reg
= (reg
+ 1) % 32;
153 val
= ldub_p(host
) << 24;
156 val
= lduw_be_p(host
) << 16;
159 val
= (lduw_be_p(host
) << 16) | (ldub_p(host
+ 2) << 8);
163 /* Slow path -- at least some of the operation requires i/o. */
164 for (; nb
> 3; nb
-= 4) {
165 env
->gpr
[reg
] = cpu_ldl_mmuidx_ra(env
, addr
, mmu_idx
, raddr
);
166 reg
= (reg
+ 1) % 32;
167 addr
= addr_add(env
, addr
, 4);
173 val
= cpu_ldub_mmuidx_ra(env
, addr
, mmu_idx
, raddr
) << 24;
176 val
= cpu_lduw_mmuidx_ra(env
, addr
, mmu_idx
, raddr
) << 16;
179 val
= cpu_lduw_mmuidx_ra(env
, addr
, mmu_idx
, raddr
) << 16;
180 addr
= addr_add(env
, addr
, 2);
181 val
|= cpu_ldub_mmuidx_ra(env
, addr
, mmu_idx
, raddr
) << 8;
188 void helper_lsw(CPUPPCState
*env
, target_ulong addr
,
189 uint32_t nb
, uint32_t reg
)
191 do_lsw(env
, addr
, nb
, reg
, GETPC());
195 * PPC32 specification says we must generate an exception if rA is in
196 * the range of registers to be loaded. In an other hand, IBM says
197 * this is valid, but rA won't be loaded. For now, I'll follow the
200 void helper_lswx(CPUPPCState
*env
, target_ulong addr
, uint32_t reg
,
201 uint32_t ra
, uint32_t rb
)
203 if (likely(xer_bc
!= 0)) {
204 int num_used_regs
= DIV_ROUND_UP(xer_bc
, 4);
205 if (unlikely((ra
!= 0 && lsw_reg_in_range(reg
, num_used_regs
, ra
)) ||
206 lsw_reg_in_range(reg
, num_used_regs
, rb
))) {
207 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
209 POWERPC_EXCP_INVAL_LSWX
, GETPC());
211 do_lsw(env
, addr
, xer_bc
, reg
, GETPC());
216 void helper_stsw(CPUPPCState
*env
, target_ulong addr
, uint32_t nb
,
219 uintptr_t raddr
= GETPC();
224 if (unlikely(nb
== 0)) {
228 mmu_idx
= cpu_mmu_index(env
, false);
229 host
= probe_contiguous(env
, addr
, nb
, MMU_DATA_STORE
, mmu_idx
, raddr
);
232 /* Fast path -- the entire operation is in RAM at host. */
233 for (; nb
> 3; nb
-= 4) {
234 stl_be_p(host
, env
->gpr
[reg
]);
235 reg
= (reg
+ 1) % 32;
241 stb_p(host
, val
>> 24);
244 stw_be_p(host
, val
>> 16);
247 stw_be_p(host
, val
>> 16);
248 stb_p(host
+ 2, val
>> 8);
252 for (; nb
> 3; nb
-= 4) {
253 cpu_stl_mmuidx_ra(env
, addr
, env
->gpr
[reg
], mmu_idx
, raddr
);
254 reg
= (reg
+ 1) % 32;
255 addr
= addr_add(env
, addr
, 4);
260 cpu_stb_mmuidx_ra(env
, addr
, val
>> 24, mmu_idx
, raddr
);
263 cpu_stw_mmuidx_ra(env
, addr
, val
>> 16, mmu_idx
, raddr
);
266 cpu_stw_mmuidx_ra(env
, addr
, val
>> 16, mmu_idx
, raddr
);
267 addr
= addr_add(env
, addr
, 2);
268 cpu_stb_mmuidx_ra(env
, addr
, val
>> 8, mmu_idx
, raddr
);
274 static void dcbz_common(CPUPPCState
*env
, target_ulong addr
,
275 uint32_t opcode
, bool epid
, uintptr_t retaddr
)
277 target_ulong mask
, dcbz_size
= env
->dcache_line_size
;
280 int mmu_idx
= epid
? PPC_TLB_EPID_STORE
: cpu_mmu_index(env
, false);
282 #if defined(TARGET_PPC64)
283 /* Check for dcbz vs dcbzl on 970 */
284 if (env
->excp_model
== POWERPC_EXCP_970
&&
285 !(opcode
& 0x00200000) && ((env
->spr
[SPR_970_HID5
] >> 7) & 0x3) == 1) {
291 mask
= ~(dcbz_size
- 1);
294 /* Check reservation */
295 if ((env
->reserve_addr
& mask
) == addr
) {
296 env
->reserve_addr
= (target_ulong
)-1ULL;
299 /* Try fast path translate */
300 haddr
= probe_write(env
, addr
, dcbz_size
, mmu_idx
, retaddr
);
302 memset(haddr
, 0, dcbz_size
);
305 for (i
= 0; i
< dcbz_size
; i
+= 8) {
306 cpu_stq_mmuidx_ra(env
, addr
+ i
, 0, mmu_idx
, retaddr
);
311 void helper_dcbz(CPUPPCState
*env
, target_ulong addr
, uint32_t opcode
)
313 dcbz_common(env
, addr
, opcode
, false, GETPC());
316 void helper_dcbzep(CPUPPCState
*env
, target_ulong addr
, uint32_t opcode
)
318 dcbz_common(env
, addr
, opcode
, true, GETPC());
321 void helper_icbi(CPUPPCState
*env
, target_ulong addr
)
323 addr
&= ~(env
->dcache_line_size
- 1);
325 * Invalidate one cache line :
326 * PowerPC specification says this is to be treated like a load
327 * (not a fetch) by the MMU. To be sure it will be so,
328 * do the load "by hand".
330 cpu_ldl_data_ra(env
, addr
, GETPC());
333 void helper_icbiep(CPUPPCState
*env
, target_ulong addr
)
335 #if !defined(CONFIG_USER_ONLY)
336 /* See comments above */
337 addr
&= ~(env
->dcache_line_size
- 1);
338 cpu_ldl_mmuidx_ra(env
, addr
, PPC_TLB_EPID_LOAD
, GETPC());
342 /* XXX: to be tested */
343 target_ulong
helper_lscbx(CPUPPCState
*env
, target_ulong addr
, uint32_t reg
,
344 uint32_t ra
, uint32_t rb
)
349 for (i
= 0; i
< xer_bc
; i
++) {
350 c
= cpu_ldub_data_ra(env
, addr
, GETPC());
351 addr
= addr_add(env
, addr
, 1);
352 /* ra (if not 0) and rb are never modified */
353 if (likely(reg
!= rb
&& (ra
== 0 || reg
!= ra
))) {
354 env
->gpr
[reg
] = (env
->gpr
[reg
] & ~(0xFF << d
)) | (c
<< d
);
356 if (unlikely(c
== xer_cmp
)) {
359 if (likely(d
!= 0)) {
371 uint64_t helper_lq_le_parallel(CPUPPCState
*env
, target_ulong addr
,
376 /* We will have raised EXCP_ATOMIC from the translator. */
377 assert(HAVE_ATOMIC128
);
378 ret
= cpu_atomic_ldo_le_mmu(env
, addr
, opidx
, GETPC());
379 env
->retxh
= int128_gethi(ret
);
380 return int128_getlo(ret
);
383 uint64_t helper_lq_be_parallel(CPUPPCState
*env
, target_ulong addr
,
388 /* We will have raised EXCP_ATOMIC from the translator. */
389 assert(HAVE_ATOMIC128
);
390 ret
= cpu_atomic_ldo_be_mmu(env
, addr
, opidx
, GETPC());
391 env
->retxh
= int128_gethi(ret
);
392 return int128_getlo(ret
);
395 void helper_stq_le_parallel(CPUPPCState
*env
, target_ulong addr
,
396 uint64_t lo
, uint64_t hi
, uint32_t opidx
)
400 /* We will have raised EXCP_ATOMIC from the translator. */
401 assert(HAVE_ATOMIC128
);
402 val
= int128_make128(lo
, hi
);
403 cpu_atomic_sto_le_mmu(env
, addr
, val
, opidx
, GETPC());
406 void helper_stq_be_parallel(CPUPPCState
*env
, target_ulong addr
,
407 uint64_t lo
, uint64_t hi
, uint32_t opidx
)
411 /* We will have raised EXCP_ATOMIC from the translator. */
412 assert(HAVE_ATOMIC128
);
413 val
= int128_make128(lo
, hi
);
414 cpu_atomic_sto_be_mmu(env
, addr
, val
, opidx
, GETPC());
417 uint32_t helper_stqcx_le_parallel(CPUPPCState
*env
, target_ulong addr
,
418 uint64_t new_lo
, uint64_t new_hi
,
421 bool success
= false;
423 /* We will have raised EXCP_ATOMIC from the translator. */
424 assert(HAVE_CMPXCHG128
);
426 if (likely(addr
== env
->reserve_addr
)) {
427 Int128 oldv
, cmpv
, newv
;
429 cmpv
= int128_make128(env
->reserve_val2
, env
->reserve_val
);
430 newv
= int128_make128(new_lo
, new_hi
);
431 oldv
= cpu_atomic_cmpxchgo_le_mmu(env
, addr
, cmpv
, newv
,
433 success
= int128_eq(oldv
, cmpv
);
435 env
->reserve_addr
= -1;
436 return env
->so
+ success
* CRF_EQ_BIT
;
439 uint32_t helper_stqcx_be_parallel(CPUPPCState
*env
, target_ulong addr
,
440 uint64_t new_lo
, uint64_t new_hi
,
443 bool success
= false;
445 /* We will have raised EXCP_ATOMIC from the translator. */
446 assert(HAVE_CMPXCHG128
);
448 if (likely(addr
== env
->reserve_addr
)) {
449 Int128 oldv
, cmpv
, newv
;
451 cmpv
= int128_make128(env
->reserve_val2
, env
->reserve_val
);
452 newv
= int128_make128(new_lo
, new_hi
);
453 oldv
= cpu_atomic_cmpxchgo_be_mmu(env
, addr
, cmpv
, newv
,
455 success
= int128_eq(oldv
, cmpv
);
457 env
->reserve_addr
= -1;
458 return env
->so
+ success
* CRF_EQ_BIT
;
462 /*****************************************************************************/
463 /* Altivec extension helpers */
473 * We use MSR_LE to determine index ordering in a vector. However,
474 * byteswapping is not simply controlled by MSR_LE. We also need to
475 * take into account endianness of the target. This is done for the
476 * little-endian PPC64 user-mode target.
479 #define LVE(name, access, swap, element) \
480 void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
483 size_t n_elems = ARRAY_SIZE(r->element); \
484 int adjust = HI_IDX * (n_elems - 1); \
485 int sh = sizeof(r->element[0]) >> 1; \
486 int index = (addr & 0xf) >> sh; \
487 if (FIELD_EX64(env->msr, MSR, LE)) { \
488 index = n_elems - index - 1; \
491 if (needs_byteswap(env)) { \
492 r->element[LO_IDX ? index : (adjust - index)] = \
493 swap(access(env, addr, GETPC())); \
495 r->element[LO_IDX ? index : (adjust - index)] = \
496 access(env, addr, GETPC()); \
500 LVE(lvebx
, cpu_ldub_data_ra
, I
, u8
)
501 LVE(lvehx
, cpu_lduw_data_ra
, bswap16
, u16
)
502 LVE(lvewx
, cpu_ldl_data_ra
, bswap32
, u32
)
506 #define STVE(name, access, swap, element) \
507 void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
510 size_t n_elems = ARRAY_SIZE(r->element); \
511 int adjust = HI_IDX * (n_elems - 1); \
512 int sh = sizeof(r->element[0]) >> 1; \
513 int index = (addr & 0xf) >> sh; \
514 if (FIELD_EX64(env->msr, MSR, LE)) { \
515 index = n_elems - index - 1; \
518 if (needs_byteswap(env)) { \
519 access(env, addr, swap(r->element[LO_IDX ? index : \
520 (adjust - index)]), \
523 access(env, addr, r->element[LO_IDX ? index : \
524 (adjust - index)], GETPC()); \
528 STVE(stvebx
, cpu_stb_data_ra
, I
, u8
)
529 STVE(stvehx
, cpu_stw_data_ra
, bswap16
, u16
)
530 STVE(stvewx
, cpu_stl_data_ra
, bswap32
, u32
)
535 #define GET_NB(rb) ((rb >> 56) & 0xFF)
537 #define VSX_LXVL(name, lj) \
538 void helper_##name(CPUPPCState *env, target_ulong addr, \
539 ppc_vsr_t *xt, target_ulong rb) \
542 uint64_t nb = GET_NB(rb); \
545 t.s128 = int128_zero(); \
547 nb = (nb >= 16) ? 16 : nb; \
548 if (FIELD_EX64(env->msr, MSR, LE) && !lj) { \
549 for (i = 16; i > 16 - nb; i--) { \
550 t.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC()); \
551 addr = addr_add(env, addr, 1); \
554 for (i = 0; i < nb; i++) { \
555 t.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC()); \
556 addr = addr_add(env, addr, 1); \
567 #define VSX_STXVL(name, lj) \
568 void helper_##name(CPUPPCState *env, target_ulong addr, \
569 ppc_vsr_t *xt, target_ulong rb) \
571 target_ulong nb = GET_NB(rb); \
578 nb = (nb >= 16) ? 16 : nb; \
579 if (FIELD_EX64(env->msr, MSR, LE) && !lj) { \
580 for (i = 16; i > 16 - nb; i--) { \
581 cpu_stb_data_ra(env, addr, xt->VsrB(i - 1), GETPC()); \
582 addr = addr_add(env, addr, 1); \
585 for (i = 0; i < nb; i++) { \
586 cpu_stb_data_ra(env, addr, xt->VsrB(i), GETPC()); \
587 addr = addr_add(env, addr, 1); \
596 #endif /* TARGET_PPC64 */
601 void helper_tbegin(CPUPPCState
*env
)
604 * As a degenerate implementation, always fail tbegin. The reason
605 * given is "Nesting overflow". The "persistent" bit is set,
606 * providing a hint to the error handler to not retry. The TFIAR
607 * captures the address of the failure, which is this tbegin
608 * instruction. Instruction execution will continue with the next
609 * instruction in memory, which is precisely what we want.
612 env
->spr
[SPR_TEXASR
] =
613 (1ULL << TEXASR_FAILURE_PERSISTENT
) |
614 (1ULL << TEXASR_NESTING_OVERFLOW
) |
615 (FIELD_EX64_HV(env
->msr
) << TEXASR_PRIVILEGE_HV
) |
616 (FIELD_EX64(env
->msr
, MSR
, PR
) << TEXASR_PRIVILEGE_PR
) |
617 (1ULL << TEXASR_FAILURE_SUMMARY
) |
618 (1ULL << TEXASR_TFIAR_EXACT
);
619 env
->spr
[SPR_TFIAR
] = env
->nip
| (FIELD_EX64_HV(env
->msr
) << 1) |
620 FIELD_EX64(env
->msr
, MSR
, PR
);
621 env
->spr
[SPR_TFHAR
] = env
->nip
+ 4;
622 env
->crf
[0] = 0xB; /* 0b1010 = transaction failure */