4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "hw/semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* initialize TCG globals. */
74 void a64_translate_init(void)
78 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
79 offsetof(CPUARMState
, pc
),
81 for (i
= 0; i
< 32; i
++) {
82 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
83 offsetof(CPUARMState
, xregs
[i
]),
87 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
88 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
92 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
94 static int get_a64_user_mem_index(DisasContext
*s
)
97 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
98 * which is the usual mmu_idx for this cpu state.
100 ARMMMUIdx useridx
= s
->mmu_idx
;
104 * We have pre-computed the condition for AccType_UNPRIV.
105 * Therefore we should never get here with a mmu_idx for
106 * which we do not know the corresponding user mmu_idx.
109 case ARMMMUIdx_E10_1
:
110 case ARMMMUIdx_E10_1_PAN
:
111 useridx
= ARMMMUIdx_E10_0
;
113 case ARMMMUIdx_E20_2
:
114 case ARMMMUIdx_E20_2_PAN
:
115 useridx
= ARMMMUIdx_E20_0
;
117 case ARMMMUIdx_SE10_1
:
118 case ARMMMUIdx_SE10_1_PAN
:
119 useridx
= ARMMMUIdx_SE10_0
;
122 g_assert_not_reached();
125 return arm_to_core_mmu_idx(useridx
);
128 static void reset_btype(DisasContext
*s
)
131 TCGv_i32 zero
= tcg_const_i32(0);
132 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
133 tcg_temp_free_i32(zero
);
138 static void set_btype(DisasContext
*s
, int val
)
142 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
143 tcg_debug_assert(val
>= 1 && val
<= 3);
145 tcg_val
= tcg_const_i32(val
);
146 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
147 tcg_temp_free_i32(tcg_val
);
151 void gen_a64_set_pc_im(uint64_t val
)
153 tcg_gen_movi_i64(cpu_pc
, val
);
157 * Handle Top Byte Ignore (TBI) bits.
159 * If address tagging is enabled via the TCR TBI bits:
160 * + for EL2 and EL3 there is only one TBI bit, and if it is set
161 * then the address is zero-extended, clearing bits [63:56]
162 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
163 * and TBI1 controls addressses with bit 55 == 1.
164 * If the appropriate TBI bit is set for the address then
165 * the address is sign-extended from bit 55 into bits [63:56]
167 * Here We have concatenated TBI{1,0} into tbi.
169 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
170 TCGv_i64 src
, int tbi
)
173 /* Load unmodified address */
174 tcg_gen_mov_i64(dst
, src
);
175 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
176 /* Force tag byte to all zero */
177 tcg_gen_extract_i64(dst
, src
, 0, 56);
179 /* Sign-extend from bit 55. */
180 tcg_gen_sextract_i64(dst
, src
, 0, 56);
183 TCGv_i64 tcg_zero
= tcg_const_i64(0);
186 * The two TBI bits differ.
187 * If tbi0, then !tbi1: only use the extension if positive.
188 * if !tbi0, then tbi1: only use the extension if negative.
190 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
191 dst
, dst
, tcg_zero
, dst
, src
);
192 tcg_temp_free_i64(tcg_zero
);
197 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
200 * If address tagging is enabled for instructions via the TCR TBI bits,
201 * then loading an address into the PC will clear out any tag.
203 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
207 * Return a "clean" address for ADDR according to TBID.
208 * This is always a fresh temporary, as we need to be able to
209 * increment this independently of a dirty write-back address.
211 static TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
213 TCGv_i64 clean
= new_tmp_a64(s
);
215 * In order to get the correct value in the FAR_ELx register,
216 * we must present the memory subsystem with the "dirty" address
217 * including the TBI. In system mode we can make this work via
218 * the TLB, dropping the TBI during translation. But for user-only
219 * mode we don't have that option, and must remove the top byte now.
221 #ifdef CONFIG_USER_ONLY
222 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
224 tcg_gen_mov_i64(clean
, addr
);
229 typedef struct DisasCompare64
{
234 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
238 arm_test_cc(&c32
, cc
);
240 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
241 * properly. The NE/EQ comparisons are also fine with this choice. */
242 c64
->cond
= c32
.cond
;
243 c64
->value
= tcg_temp_new_i64();
244 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
249 static void a64_free_cc(DisasCompare64
*c64
)
251 tcg_temp_free_i64(c64
->value
);
254 static void gen_exception_internal(int excp
)
256 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
258 assert(excp_is_internal(excp
));
259 gen_helper_exception_internal(cpu_env
, tcg_excp
);
260 tcg_temp_free_i32(tcg_excp
);
263 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
265 gen_a64_set_pc_im(pc
);
266 gen_exception_internal(excp
);
267 s
->base
.is_jmp
= DISAS_NORETURN
;
270 static void gen_exception_insn(DisasContext
*s
, uint64_t pc
, int excp
,
271 uint32_t syndrome
, uint32_t target_el
)
273 gen_a64_set_pc_im(pc
);
274 gen_exception(excp
, syndrome
, target_el
);
275 s
->base
.is_jmp
= DISAS_NORETURN
;
278 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
282 gen_a64_set_pc_im(s
->pc_curr
);
283 tcg_syn
= tcg_const_i32(syndrome
);
284 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
285 tcg_temp_free_i32(tcg_syn
);
286 s
->base
.is_jmp
= DISAS_NORETURN
;
289 static void gen_step_complete_exception(DisasContext
*s
)
291 /* We just completed step of an insn. Move from Active-not-pending
292 * to Active-pending, and then also take the swstep exception.
293 * This corresponds to making the (IMPDEF) choice to prioritize
294 * swstep exceptions over asynchronous exceptions taken to an exception
295 * level where debug is disabled. This choice has the advantage that
296 * we do not need to maintain internal state corresponding to the
297 * ISV/EX syndrome bits between completion of the step and generation
298 * of the exception, and our syndrome information is always correct.
301 gen_swstep_exception(s
, 1, s
->is_ldex
);
302 s
->base
.is_jmp
= DISAS_NORETURN
;
305 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
307 /* No direct tb linking with singlestep (either QEMU's or the ARM
308 * debug architecture kind) or deterministic io
310 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
311 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
315 #ifndef CONFIG_USER_ONLY
316 /* Only link tbs from inside the same guest page */
317 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
325 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
327 TranslationBlock
*tb
;
330 if (use_goto_tb(s
, n
, dest
)) {
332 gen_a64_set_pc_im(dest
);
333 tcg_gen_exit_tb(tb
, n
);
334 s
->base
.is_jmp
= DISAS_NORETURN
;
336 gen_a64_set_pc_im(dest
);
338 gen_step_complete_exception(s
);
339 } else if (s
->base
.singlestep_enabled
) {
340 gen_exception_internal(EXCP_DEBUG
);
342 tcg_gen_lookup_and_goto_ptr();
343 s
->base
.is_jmp
= DISAS_NORETURN
;
348 void unallocated_encoding(DisasContext
*s
)
350 /* Unallocated and reserved encodings are uncategorized */
351 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(),
352 default_exception_el(s
));
355 static void init_tmp_a64_array(DisasContext
*s
)
357 #ifdef CONFIG_DEBUG_TCG
358 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
360 s
->tmp_a64_count
= 0;
363 static void free_tmp_a64(DisasContext
*s
)
366 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
367 tcg_temp_free_i64(s
->tmp_a64
[i
]);
369 init_tmp_a64_array(s
);
372 TCGv_i64
new_tmp_a64(DisasContext
*s
)
374 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
375 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
378 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
380 TCGv_i64 t
= new_tmp_a64(s
);
381 tcg_gen_movi_i64(t
, 0);
386 * Register access functions
388 * These functions are used for directly accessing a register in where
389 * changes to the final register value are likely to be made. If you
390 * need to use a register for temporary calculation (e.g. index type
391 * operations) use the read_* form.
393 * B1.2.1 Register mappings
395 * In instruction register encoding 31 can refer to ZR (zero register) or
396 * the SP (stack pointer) depending on context. In QEMU's case we map SP
397 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
398 * This is the point of the _sp forms.
400 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
403 return new_tmp_a64_zero(s
);
409 /* register access for when 31 == SP */
410 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
415 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
416 * representing the register contents. This TCGv is an auto-freed
417 * temporary so it need not be explicitly freed, and may be modified.
419 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
421 TCGv_i64 v
= new_tmp_a64(s
);
424 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
426 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
429 tcg_gen_movi_i64(v
, 0);
434 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
436 TCGv_i64 v
= new_tmp_a64(s
);
438 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
440 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
445 /* Return the offset into CPUARMState of a slice (from
446 * the least significant end) of FP register Qn (ie
448 * (Note that this is not the same mapping as for A32; see cpu.h)
450 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
452 return vec_reg_offset(s
, regno
, 0, size
);
455 /* Offset of the high half of the 128 bit vector Qn */
456 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
458 return vec_reg_offset(s
, regno
, 1, MO_64
);
461 /* Convenience accessors for reading and writing single and double
462 * FP registers. Writing clears the upper parts of the associated
463 * 128 bit vector register, as required by the architecture.
464 * Note that unlike the GP register accessors, the values returned
465 * by the read functions must be manually freed.
467 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
469 TCGv_i64 v
= tcg_temp_new_i64();
471 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
475 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
477 TCGv_i32 v
= tcg_temp_new_i32();
479 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
483 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
485 TCGv_i32 v
= tcg_temp_new_i32();
487 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
491 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
492 * If SVE is not enabled, then there are only 128 bits in the vector.
494 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
496 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
497 unsigned vsz
= vec_full_reg_size(s
);
500 TCGv_i64 tcg_zero
= tcg_const_i64(0);
501 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
502 tcg_temp_free_i64(tcg_zero
);
505 tcg_gen_gvec_dup_imm(MO_64
, ofs
+ 16, vsz
- 16, vsz
- 16, 0);
509 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
511 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
513 tcg_gen_st_i64(v
, cpu_env
, ofs
);
514 clear_vec_high(s
, false, reg
);
517 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
519 TCGv_i64 tmp
= tcg_temp_new_i64();
521 tcg_gen_extu_i32_i64(tmp
, v
);
522 write_fp_dreg(s
, reg
, tmp
);
523 tcg_temp_free_i64(tmp
);
526 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
528 TCGv_ptr statusptr
= tcg_temp_new_ptr();
531 /* In A64 all instructions (both FP and Neon) use the FPCR; there
532 * is no equivalent of the A32 Neon "standard FPSCR value".
533 * However half-precision operations operate under a different
534 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
537 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
539 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
541 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
545 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
546 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
547 GVecGen2Fn
*gvec_fn
, int vece
)
549 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
550 is_q
? 16 : 8, vec_full_reg_size(s
));
553 /* Expand a 2-operand + immediate AdvSIMD vector operation using
554 * an expander function.
556 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
557 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
559 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
560 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
563 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
564 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
565 GVecGen3Fn
*gvec_fn
, int vece
)
567 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
568 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
571 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
572 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
573 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
575 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
576 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
577 is_q
? 16 : 8, vec_full_reg_size(s
));
580 /* Expand a 2-operand AdvSIMD vector operation using an op descriptor. */
581 static void gen_gvec_op2(DisasContext
*s
, bool is_q
, int rd
,
582 int rn
, const GVecGen2
*gvec_op
)
584 tcg_gen_gvec_2(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
585 is_q
? 16 : 8, vec_full_reg_size(s
), gvec_op
);
588 /* Expand a 2-operand + immediate AdvSIMD vector operation using
591 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
592 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
594 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
595 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
598 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
599 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
600 int rn
, int rm
, const GVecGen3
*gvec_op
)
602 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
603 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
604 vec_full_reg_size(s
), gvec_op
);
607 /* Expand a 3-operand operation using an out-of-line helper. */
608 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
609 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
611 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
612 vec_full_reg_offset(s
, rn
),
613 vec_full_reg_offset(s
, rm
),
614 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
617 /* Expand a 3-operand + env pointer operation using
618 * an out-of-line helper.
620 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
621 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
623 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
624 vec_full_reg_offset(s
, rn
),
625 vec_full_reg_offset(s
, rm
), cpu_env
,
626 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
629 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
630 * an out-of-line helper.
632 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
633 int rm
, bool is_fp16
, int data
,
634 gen_helper_gvec_3_ptr
*fn
)
636 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
637 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
638 vec_full_reg_offset(s
, rn
),
639 vec_full_reg_offset(s
, rm
), fpst
,
640 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
641 tcg_temp_free_ptr(fpst
);
644 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
645 * than the 32 bit equivalent.
647 static inline void gen_set_NZ64(TCGv_i64 result
)
649 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
650 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
653 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
654 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
657 gen_set_NZ64(result
);
659 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
660 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
662 tcg_gen_movi_i32(cpu_CF
, 0);
663 tcg_gen_movi_i32(cpu_VF
, 0);
666 /* dest = T0 + T1; compute C, N, V and Z flags */
667 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
670 TCGv_i64 result
, flag
, tmp
;
671 result
= tcg_temp_new_i64();
672 flag
= tcg_temp_new_i64();
673 tmp
= tcg_temp_new_i64();
675 tcg_gen_movi_i64(tmp
, 0);
676 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
678 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
680 gen_set_NZ64(result
);
682 tcg_gen_xor_i64(flag
, result
, t0
);
683 tcg_gen_xor_i64(tmp
, t0
, t1
);
684 tcg_gen_andc_i64(flag
, flag
, tmp
);
685 tcg_temp_free_i64(tmp
);
686 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
688 tcg_gen_mov_i64(dest
, result
);
689 tcg_temp_free_i64(result
);
690 tcg_temp_free_i64(flag
);
692 /* 32 bit arithmetic */
693 TCGv_i32 t0_32
= tcg_temp_new_i32();
694 TCGv_i32 t1_32
= tcg_temp_new_i32();
695 TCGv_i32 tmp
= tcg_temp_new_i32();
697 tcg_gen_movi_i32(tmp
, 0);
698 tcg_gen_extrl_i64_i32(t0_32
, t0
);
699 tcg_gen_extrl_i64_i32(t1_32
, t1
);
700 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
701 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
702 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
703 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
704 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
705 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
707 tcg_temp_free_i32(tmp
);
708 tcg_temp_free_i32(t0_32
);
709 tcg_temp_free_i32(t1_32
);
713 /* dest = T0 - T1; compute C, N, V and Z flags */
714 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
717 /* 64 bit arithmetic */
718 TCGv_i64 result
, flag
, tmp
;
720 result
= tcg_temp_new_i64();
721 flag
= tcg_temp_new_i64();
722 tcg_gen_sub_i64(result
, t0
, t1
);
724 gen_set_NZ64(result
);
726 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
727 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
729 tcg_gen_xor_i64(flag
, result
, t0
);
730 tmp
= tcg_temp_new_i64();
731 tcg_gen_xor_i64(tmp
, t0
, t1
);
732 tcg_gen_and_i64(flag
, flag
, tmp
);
733 tcg_temp_free_i64(tmp
);
734 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
735 tcg_gen_mov_i64(dest
, result
);
736 tcg_temp_free_i64(flag
);
737 tcg_temp_free_i64(result
);
739 /* 32 bit arithmetic */
740 TCGv_i32 t0_32
= tcg_temp_new_i32();
741 TCGv_i32 t1_32
= tcg_temp_new_i32();
744 tcg_gen_extrl_i64_i32(t0_32
, t0
);
745 tcg_gen_extrl_i64_i32(t1_32
, t1
);
746 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
747 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
748 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
749 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
750 tmp
= tcg_temp_new_i32();
751 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
752 tcg_temp_free_i32(t0_32
);
753 tcg_temp_free_i32(t1_32
);
754 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
755 tcg_temp_free_i32(tmp
);
756 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
760 /* dest = T0 + T1 + CF; do not compute flags. */
761 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
763 TCGv_i64 flag
= tcg_temp_new_i64();
764 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
765 tcg_gen_add_i64(dest
, t0
, t1
);
766 tcg_gen_add_i64(dest
, dest
, flag
);
767 tcg_temp_free_i64(flag
);
770 tcg_gen_ext32u_i64(dest
, dest
);
774 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
775 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
778 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
779 result
= tcg_temp_new_i64();
780 cf_64
= tcg_temp_new_i64();
781 vf_64
= tcg_temp_new_i64();
782 tmp
= tcg_const_i64(0);
784 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
785 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
786 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
787 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
788 gen_set_NZ64(result
);
790 tcg_gen_xor_i64(vf_64
, result
, t0
);
791 tcg_gen_xor_i64(tmp
, t0
, t1
);
792 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
793 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
795 tcg_gen_mov_i64(dest
, result
);
797 tcg_temp_free_i64(tmp
);
798 tcg_temp_free_i64(vf_64
);
799 tcg_temp_free_i64(cf_64
);
800 tcg_temp_free_i64(result
);
802 TCGv_i32 t0_32
, t1_32
, tmp
;
803 t0_32
= tcg_temp_new_i32();
804 t1_32
= tcg_temp_new_i32();
805 tmp
= tcg_const_i32(0);
807 tcg_gen_extrl_i64_i32(t0_32
, t0
);
808 tcg_gen_extrl_i64_i32(t1_32
, t1
);
809 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
810 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
812 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
813 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
814 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
815 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
816 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
818 tcg_temp_free_i32(tmp
);
819 tcg_temp_free_i32(t1_32
);
820 tcg_temp_free_i32(t0_32
);
825 * Load/Store generators
829 * Store from GPR register to memory.
831 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
832 TCGv_i64 tcg_addr
, int size
, int memidx
,
834 unsigned int iss_srt
,
835 bool iss_sf
, bool iss_ar
)
838 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
843 syn
= syn_data_abort_with_iss(0,
849 0, 0, 0, 0, 0, false);
850 disas_set_insn_syndrome(s
, syn
);
854 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
855 TCGv_i64 tcg_addr
, int size
,
857 unsigned int iss_srt
,
858 bool iss_sf
, bool iss_ar
)
860 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
861 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
865 * Load from memory to GPR register
867 static void do_gpr_ld_memidx(DisasContext
*s
,
868 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
869 int size
, bool is_signed
,
870 bool extend
, int memidx
,
871 bool iss_valid
, unsigned int iss_srt
,
872 bool iss_sf
, bool iss_ar
)
874 MemOp memop
= s
->be_data
+ size
;
882 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
884 if (extend
&& is_signed
) {
886 tcg_gen_ext32u_i64(dest
, dest
);
892 syn
= syn_data_abort_with_iss(0,
898 0, 0, 0, 0, 0, false);
899 disas_set_insn_syndrome(s
, syn
);
903 static void do_gpr_ld(DisasContext
*s
,
904 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
905 int size
, bool is_signed
, bool extend
,
906 bool iss_valid
, unsigned int iss_srt
,
907 bool iss_sf
, bool iss_ar
)
909 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
911 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
915 * Store from FP register to memory
917 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
919 /* This writes the bottom N bits of a 128 bit wide vector to memory */
920 TCGv_i64 tmp
= tcg_temp_new_i64();
921 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
923 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
926 bool be
= s
->be_data
== MO_BE
;
927 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
929 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
930 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
932 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
933 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
935 tcg_temp_free_i64(tcg_hiaddr
);
938 tcg_temp_free_i64(tmp
);
942 * Load from memory to FP register
944 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
946 /* This always zero-extends and writes to a full 128 bit wide vector */
947 TCGv_i64 tmplo
= tcg_temp_new_i64();
951 MemOp memop
= s
->be_data
+ size
;
952 tmphi
= tcg_const_i64(0);
953 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
955 bool be
= s
->be_data
== MO_BE
;
958 tmphi
= tcg_temp_new_i64();
959 tcg_hiaddr
= tcg_temp_new_i64();
961 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
962 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
964 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
966 tcg_temp_free_i64(tcg_hiaddr
);
969 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
970 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
972 tcg_temp_free_i64(tmplo
);
973 tcg_temp_free_i64(tmphi
);
975 clear_vec_high(s
, true, destidx
);
979 * Vector load/store helpers.
981 * The principal difference between this and a FP load is that we don't
982 * zero extend as we are filling a partial chunk of the vector register.
983 * These functions don't support 128 bit loads/stores, which would be
984 * normal load/store operations.
986 * The _i32 versions are useful when operating on 32 bit quantities
987 * (eg for floating point single or using Neon helper functions).
990 /* Get value of an element within a vector register */
991 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
992 int element
, MemOp memop
)
994 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
997 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1000 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1003 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1006 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1009 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1012 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1016 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1019 g_assert_not_reached();
1023 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1024 int element
, MemOp memop
)
1026 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1029 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1032 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1035 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1038 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1042 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1045 g_assert_not_reached();
1049 /* Set value of an element within a vector register */
1050 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1051 int element
, MemOp memop
)
1053 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1056 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1059 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1062 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1065 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1068 g_assert_not_reached();
1072 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1073 int destidx
, int element
, MemOp memop
)
1075 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1078 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1081 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1084 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1087 g_assert_not_reached();
1091 /* Store from vector register to memory */
1092 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1093 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1095 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1097 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1098 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1100 tcg_temp_free_i64(tcg_tmp
);
1103 /* Load from memory to vector register */
1104 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1105 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1107 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1109 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1110 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1112 tcg_temp_free_i64(tcg_tmp
);
1115 /* Check that FP/Neon access is enabled. If it is, return
1116 * true. If not, emit code to generate an appropriate exception,
1117 * and return false; the caller should not emit any code for
1118 * the instruction. Note that this check must happen after all
1119 * unallocated-encoding checks (otherwise the syndrome information
1120 * for the resulting exception will be incorrect).
1122 static inline bool fp_access_check(DisasContext
*s
)
1124 assert(!s
->fp_access_checked
);
1125 s
->fp_access_checked
= true;
1127 if (!s
->fp_excp_el
) {
1131 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1132 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1136 /* Check that SVE access is enabled. If it is, return true.
1137 * If not, emit code to generate an appropriate exception and return false.
1139 bool sve_access_check(DisasContext
*s
)
1141 if (s
->sve_excp_el
) {
1142 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_sve_access_trap(),
1146 return fp_access_check(s
);
1150 * This utility function is for doing register extension with an
1151 * optional shift. You will likely want to pass a temporary for the
1152 * destination register. See DecodeRegExtend() in the ARM ARM.
1154 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1155 int option
, unsigned int shift
)
1157 int extsize
= extract32(option
, 0, 2);
1158 bool is_signed
= extract32(option
, 2, 1);
1163 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1166 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1169 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1172 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1178 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1181 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1184 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1187 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1193 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1197 static inline void gen_check_sp_alignment(DisasContext
*s
)
1199 /* The AArch64 architecture mandates that (if enabled via PSTATE
1200 * or SCTLR bits) there is a check that SP is 16-aligned on every
1201 * SP-relative load or store (with an exception generated if it is not).
1202 * In line with general QEMU practice regarding misaligned accesses,
1203 * we omit these checks for the sake of guest program performance.
1204 * This function is provided as a hook so we can more easily add these
1205 * checks in future (possibly as a "favour catching guest program bugs
1206 * over speed" user selectable option).
1211 * This provides a simple table based table lookup decoder. It is
1212 * intended to be used when the relevant bits for decode are too
1213 * awkwardly placed and switch/if based logic would be confusing and
1214 * deeply nested. Since it's a linear search through the table, tables
1215 * should be kept small.
1217 * It returns the first handler where insn & mask == pattern, or
1218 * NULL if there is no match.
1219 * The table is terminated by an empty mask (i.e. 0)
1221 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1224 const AArch64DecodeTable
*tptr
= table
;
1226 while (tptr
->mask
) {
1227 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1228 return tptr
->disas_fn
;
1236 * The instruction disassembly implemented here matches
1237 * the instruction encoding classifications in chapter C4
1238 * of the ARM Architecture Reference Manual (DDI0487B_a);
1239 * classification names and decode diagrams here should generally
1240 * match up with those in the manual.
1243 /* Unconditional branch (immediate)
1245 * +----+-----------+-------------------------------------+
1246 * | op | 0 0 1 0 1 | imm26 |
1247 * +----+-----------+-------------------------------------+
1249 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1251 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1253 if (insn
& (1U << 31)) {
1254 /* BL Branch with link */
1255 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1258 /* B Branch / BL Branch with link */
1260 gen_goto_tb(s
, 0, addr
);
1263 /* Compare and branch (immediate)
1264 * 31 30 25 24 23 5 4 0
1265 * +----+-------------+----+---------------------+--------+
1266 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1267 * +----+-------------+----+---------------------+--------+
1269 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1271 unsigned int sf
, op
, rt
;
1273 TCGLabel
*label_match
;
1276 sf
= extract32(insn
, 31, 1);
1277 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1278 rt
= extract32(insn
, 0, 5);
1279 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1281 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1282 label_match
= gen_new_label();
1285 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1286 tcg_cmp
, 0, label_match
);
1288 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1289 gen_set_label(label_match
);
1290 gen_goto_tb(s
, 1, addr
);
1293 /* Test and branch (immediate)
1294 * 31 30 25 24 23 19 18 5 4 0
1295 * +----+-------------+----+-------+-------------+------+
1296 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1297 * +----+-------------+----+-------+-------------+------+
1299 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1301 unsigned int bit_pos
, op
, rt
;
1303 TCGLabel
*label_match
;
1306 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1307 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1308 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1309 rt
= extract32(insn
, 0, 5);
1311 tcg_cmp
= tcg_temp_new_i64();
1312 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1313 label_match
= gen_new_label();
1316 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1317 tcg_cmp
, 0, label_match
);
1318 tcg_temp_free_i64(tcg_cmp
);
1319 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1320 gen_set_label(label_match
);
1321 gen_goto_tb(s
, 1, addr
);
1324 /* Conditional branch (immediate)
1325 * 31 25 24 23 5 4 3 0
1326 * +---------------+----+---------------------+----+------+
1327 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1328 * +---------------+----+---------------------+----+------+
1330 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1335 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1336 unallocated_encoding(s
);
1339 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1340 cond
= extract32(insn
, 0, 4);
1344 /* genuinely conditional branches */
1345 TCGLabel
*label_match
= gen_new_label();
1346 arm_gen_test_cc(cond
, label_match
);
1347 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1348 gen_set_label(label_match
);
1349 gen_goto_tb(s
, 1, addr
);
1351 /* 0xe and 0xf are both "always" conditions */
1352 gen_goto_tb(s
, 0, addr
);
1356 /* HINT instruction group, including various allocated HINTs */
1357 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1358 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1360 unsigned int selector
= crm
<< 3 | op2
;
1363 unallocated_encoding(s
);
1368 case 0b00000: /* NOP */
1370 case 0b00011: /* WFI */
1371 s
->base
.is_jmp
= DISAS_WFI
;
1373 case 0b00001: /* YIELD */
1374 /* When running in MTTCG we don't generate jumps to the yield and
1375 * WFE helpers as it won't affect the scheduling of other vCPUs.
1376 * If we wanted to more completely model WFE/SEV so we don't busy
1377 * spin unnecessarily we would need to do something more involved.
1379 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1380 s
->base
.is_jmp
= DISAS_YIELD
;
1383 case 0b00010: /* WFE */
1384 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1385 s
->base
.is_jmp
= DISAS_WFE
;
1388 case 0b00100: /* SEV */
1389 case 0b00101: /* SEVL */
1390 /* we treat all as NOP at least for now */
1392 case 0b00111: /* XPACLRI */
1393 if (s
->pauth_active
) {
1394 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1397 case 0b01000: /* PACIA1716 */
1398 if (s
->pauth_active
) {
1399 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1402 case 0b01010: /* PACIB1716 */
1403 if (s
->pauth_active
) {
1404 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1407 case 0b01100: /* AUTIA1716 */
1408 if (s
->pauth_active
) {
1409 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1412 case 0b01110: /* AUTIB1716 */
1413 if (s
->pauth_active
) {
1414 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1417 case 0b11000: /* PACIAZ */
1418 if (s
->pauth_active
) {
1419 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1420 new_tmp_a64_zero(s
));
1423 case 0b11001: /* PACIASP */
1424 if (s
->pauth_active
) {
1425 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1428 case 0b11010: /* PACIBZ */
1429 if (s
->pauth_active
) {
1430 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1431 new_tmp_a64_zero(s
));
1434 case 0b11011: /* PACIBSP */
1435 if (s
->pauth_active
) {
1436 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1439 case 0b11100: /* AUTIAZ */
1440 if (s
->pauth_active
) {
1441 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1442 new_tmp_a64_zero(s
));
1445 case 0b11101: /* AUTIASP */
1446 if (s
->pauth_active
) {
1447 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1450 case 0b11110: /* AUTIBZ */
1451 if (s
->pauth_active
) {
1452 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1453 new_tmp_a64_zero(s
));
1456 case 0b11111: /* AUTIBSP */
1457 if (s
->pauth_active
) {
1458 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1462 /* default specified as NOP equivalent */
1467 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1469 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1472 /* CLREX, DSB, DMB, ISB */
1473 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1474 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1479 unallocated_encoding(s
);
1490 case 1: /* MBReqTypes_Reads */
1491 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1493 case 2: /* MBReqTypes_Writes */
1494 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1496 default: /* MBReqTypes_All */
1497 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1503 /* We need to break the TB after this insn to execute
1504 * a self-modified code correctly and also to take
1505 * any pending interrupts immediately.
1508 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1512 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1513 goto do_unallocated
;
1516 * TODO: There is no speculation barrier opcode for TCG;
1517 * MB and end the TB instead.
1519 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1520 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1525 unallocated_encoding(s
);
1530 static void gen_xaflag(void)
1532 TCGv_i32 z
= tcg_temp_new_i32();
1534 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1543 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1544 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1547 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1548 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1550 /* (!C & Z) << 31 -> -(Z & ~C) */
1551 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1552 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1555 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1557 tcg_temp_free_i32(z
);
1560 static void gen_axflag(void)
1562 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1563 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1565 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1566 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1568 tcg_gen_movi_i32(cpu_NF
, 0);
1569 tcg_gen_movi_i32(cpu_VF
, 0);
1572 /* MSR (immediate) - move immediate to processor state field */
1573 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1574 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1577 int op
= op1
<< 3 | op2
;
1579 /* End the TB by default, chaining is ok. */
1580 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1583 case 0x00: /* CFINV */
1584 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1585 goto do_unallocated
;
1587 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1588 s
->base
.is_jmp
= DISAS_NEXT
;
1591 case 0x01: /* XAFlag */
1592 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1593 goto do_unallocated
;
1596 s
->base
.is_jmp
= DISAS_NEXT
;
1599 case 0x02: /* AXFlag */
1600 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1601 goto do_unallocated
;
1604 s
->base
.is_jmp
= DISAS_NEXT
;
1607 case 0x03: /* UAO */
1608 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1609 goto do_unallocated
;
1612 set_pstate_bits(PSTATE_UAO
);
1614 clear_pstate_bits(PSTATE_UAO
);
1616 t1
= tcg_const_i32(s
->current_el
);
1617 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1618 tcg_temp_free_i32(t1
);
1621 case 0x04: /* PAN */
1622 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1623 goto do_unallocated
;
1626 set_pstate_bits(PSTATE_PAN
);
1628 clear_pstate_bits(PSTATE_PAN
);
1630 t1
= tcg_const_i32(s
->current_el
);
1631 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1632 tcg_temp_free_i32(t1
);
1635 case 0x05: /* SPSel */
1636 if (s
->current_el
== 0) {
1637 goto do_unallocated
;
1639 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1640 gen_helper_msr_i_spsel(cpu_env
, t1
);
1641 tcg_temp_free_i32(t1
);
1644 case 0x1e: /* DAIFSet */
1645 t1
= tcg_const_i32(crm
);
1646 gen_helper_msr_i_daifset(cpu_env
, t1
);
1647 tcg_temp_free_i32(t1
);
1650 case 0x1f: /* DAIFClear */
1651 t1
= tcg_const_i32(crm
);
1652 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1653 tcg_temp_free_i32(t1
);
1654 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1655 s
->base
.is_jmp
= DISAS_UPDATE
;
1660 unallocated_encoding(s
);
1665 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1667 TCGv_i32 tmp
= tcg_temp_new_i32();
1668 TCGv_i32 nzcv
= tcg_temp_new_i32();
1670 /* build bit 31, N */
1671 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1672 /* build bit 30, Z */
1673 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1674 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1675 /* build bit 29, C */
1676 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1677 /* build bit 28, V */
1678 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1679 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1680 /* generate result */
1681 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1683 tcg_temp_free_i32(nzcv
);
1684 tcg_temp_free_i32(tmp
);
1687 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1689 TCGv_i32 nzcv
= tcg_temp_new_i32();
1691 /* take NZCV from R[t] */
1692 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1695 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1697 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1698 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1700 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1701 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1703 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1704 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1705 tcg_temp_free_i32(nzcv
);
1708 /* MRS - move from system register
1709 * MSR (register) - move to system register
1712 * These are all essentially the same insn in 'read' and 'write'
1713 * versions, with varying op0 fields.
1715 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1716 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1717 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1719 const ARMCPRegInfo
*ri
;
1722 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1723 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1724 crn
, crm
, op0
, op1
, op2
));
1727 /* Unknown register; this might be a guest error or a QEMU
1728 * unimplemented feature.
1730 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1731 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1732 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1733 unallocated_encoding(s
);
1737 /* Check access permissions */
1738 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1739 unallocated_encoding(s
);
1744 /* Emit code to perform further access permissions checks at
1745 * runtime; this may result in an exception.
1748 TCGv_i32 tcg_syn
, tcg_isread
;
1751 gen_a64_set_pc_im(s
->pc_curr
);
1752 tmpptr
= tcg_const_ptr(ri
);
1753 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1754 tcg_syn
= tcg_const_i32(syndrome
);
1755 tcg_isread
= tcg_const_i32(isread
);
1756 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1757 tcg_temp_free_ptr(tmpptr
);
1758 tcg_temp_free_i32(tcg_syn
);
1759 tcg_temp_free_i32(tcg_isread
);
1760 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1762 * The readfn or writefn might raise an exception;
1763 * synchronize the CPU state in case it does.
1765 gen_a64_set_pc_im(s
->pc_curr
);
1768 /* Handle special cases first */
1769 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1773 tcg_rt
= cpu_reg(s
, rt
);
1775 gen_get_nzcv(tcg_rt
);
1777 gen_set_nzcv(tcg_rt
);
1780 case ARM_CP_CURRENTEL
:
1781 /* Reads as current EL value from pstate, which is
1782 * guaranteed to be constant by the tb flags.
1784 tcg_rt
= cpu_reg(s
, rt
);
1785 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1788 /* Writes clear the aligned block of memory which rt points into. */
1789 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1790 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1795 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1797 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1801 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1805 tcg_rt
= cpu_reg(s
, rt
);
1808 if (ri
->type
& ARM_CP_CONST
) {
1809 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1810 } else if (ri
->readfn
) {
1812 tmpptr
= tcg_const_ptr(ri
);
1813 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1814 tcg_temp_free_ptr(tmpptr
);
1816 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1819 if (ri
->type
& ARM_CP_CONST
) {
1820 /* If not forbidden by access permissions, treat as WI */
1822 } else if (ri
->writefn
) {
1824 tmpptr
= tcg_const_ptr(ri
);
1825 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1826 tcg_temp_free_ptr(tmpptr
);
1828 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1832 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1833 /* I/O operations must end the TB here (whether read or write) */
1834 s
->base
.is_jmp
= DISAS_UPDATE
;
1836 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1838 * A write to any coprocessor regiser that ends a TB
1839 * must rebuild the hflags for the next TB.
1841 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
1842 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
1843 tcg_temp_free_i32(tcg_el
);
1845 * We default to ending the TB on a coprocessor register write,
1846 * but allow this to be suppressed by the register definition
1847 * (usually only necessary to work around guest bugs).
1849 s
->base
.is_jmp
= DISAS_UPDATE
;
1854 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1855 * +---------------------+---+-----+-----+-------+-------+-----+------+
1856 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1857 * +---------------------+---+-----+-----+-------+-------+-----+------+
1859 static void disas_system(DisasContext
*s
, uint32_t insn
)
1861 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1862 l
= extract32(insn
, 21, 1);
1863 op0
= extract32(insn
, 19, 2);
1864 op1
= extract32(insn
, 16, 3);
1865 crn
= extract32(insn
, 12, 4);
1866 crm
= extract32(insn
, 8, 4);
1867 op2
= extract32(insn
, 5, 3);
1868 rt
= extract32(insn
, 0, 5);
1871 if (l
|| rt
!= 31) {
1872 unallocated_encoding(s
);
1876 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1877 handle_hint(s
, insn
, op1
, op2
, crm
);
1879 case 3: /* CLREX, DSB, DMB, ISB */
1880 handle_sync(s
, insn
, op1
, op2
, crm
);
1882 case 4: /* MSR (immediate) */
1883 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1886 unallocated_encoding(s
);
1891 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1894 /* Exception generation
1896 * 31 24 23 21 20 5 4 2 1 0
1897 * +-----------------+-----+------------------------+-----+----+
1898 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1899 * +-----------------------+------------------------+----------+
1901 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1903 int opc
= extract32(insn
, 21, 3);
1904 int op2_ll
= extract32(insn
, 0, 5);
1905 int imm16
= extract32(insn
, 5, 16);
1910 /* For SVC, HVC and SMC we advance the single-step state
1911 * machine before taking the exception. This is architecturally
1912 * mandated, to ensure that single-stepping a system call
1913 * instruction works properly.
1918 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
1919 syn_aa64_svc(imm16
), default_exception_el(s
));
1922 if (s
->current_el
== 0) {
1923 unallocated_encoding(s
);
1926 /* The pre HVC helper handles cases when HVC gets trapped
1927 * as an undefined insn by runtime configuration.
1929 gen_a64_set_pc_im(s
->pc_curr
);
1930 gen_helper_pre_hvc(cpu_env
);
1932 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
1933 syn_aa64_hvc(imm16
), 2);
1936 if (s
->current_el
== 0) {
1937 unallocated_encoding(s
);
1940 gen_a64_set_pc_im(s
->pc_curr
);
1941 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1942 gen_helper_pre_smc(cpu_env
, tmp
);
1943 tcg_temp_free_i32(tmp
);
1945 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
1946 syn_aa64_smc(imm16
), 3);
1949 unallocated_encoding(s
);
1955 unallocated_encoding(s
);
1959 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
1963 unallocated_encoding(s
);
1966 /* HLT. This has two purposes.
1967 * Architecturally, it is an external halting debug instruction.
1968 * Since QEMU doesn't implement external debug, we treat this as
1969 * it is required for halting debug disabled: it will UNDEF.
1970 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1972 if (semihosting_enabled() && imm16
== 0xf000) {
1973 #ifndef CONFIG_USER_ONLY
1974 /* In system mode, don't allow userspace access to semihosting,
1975 * to provide some semblance of security (and for consistency
1976 * with our 32-bit semihosting).
1978 if (s
->current_el
== 0) {
1979 unsupported_encoding(s
, insn
);
1983 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
1985 unsupported_encoding(s
, insn
);
1989 if (op2_ll
< 1 || op2_ll
> 3) {
1990 unallocated_encoding(s
);
1993 /* DCPS1, DCPS2, DCPS3 */
1994 unsupported_encoding(s
, insn
);
1997 unallocated_encoding(s
);
2002 /* Unconditional branch (register)
2003 * 31 25 24 21 20 16 15 10 9 5 4 0
2004 * +---------------+-------+-------+-------+------+-------+
2005 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2006 * +---------------+-------+-------+-------+------+-------+
2008 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2010 unsigned int opc
, op2
, op3
, rn
, op4
;
2011 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2015 opc
= extract32(insn
, 21, 4);
2016 op2
= extract32(insn
, 16, 5);
2017 op3
= extract32(insn
, 10, 6);
2018 rn
= extract32(insn
, 5, 5);
2019 op4
= extract32(insn
, 0, 5);
2022 goto do_unallocated
;
2034 goto do_unallocated
;
2036 dst
= cpu_reg(s
, rn
);
2041 if (!dc_isar_feature(aa64_pauth
, s
)) {
2042 goto do_unallocated
;
2046 if (rn
!= 0x1f || op4
!= 0x1f) {
2047 goto do_unallocated
;
2050 modifier
= cpu_X
[31];
2052 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2054 goto do_unallocated
;
2056 modifier
= new_tmp_a64_zero(s
);
2058 if (s
->pauth_active
) {
2059 dst
= new_tmp_a64(s
);
2061 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2063 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2066 dst
= cpu_reg(s
, rn
);
2071 goto do_unallocated
;
2073 gen_a64_set_pc(s
, dst
);
2074 /* BLR also needs to load return address */
2076 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2082 if (!dc_isar_feature(aa64_pauth
, s
)) {
2083 goto do_unallocated
;
2085 if ((op3
& ~1) != 2) {
2086 goto do_unallocated
;
2088 btype_mod
= opc
& 1;
2089 if (s
->pauth_active
) {
2090 dst
= new_tmp_a64(s
);
2091 modifier
= cpu_reg_sp(s
, op4
);
2093 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2095 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2098 dst
= cpu_reg(s
, rn
);
2100 gen_a64_set_pc(s
, dst
);
2101 /* BLRAA also needs to load return address */
2103 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2108 if (s
->current_el
== 0) {
2109 goto do_unallocated
;
2114 goto do_unallocated
;
2116 dst
= tcg_temp_new_i64();
2117 tcg_gen_ld_i64(dst
, cpu_env
,
2118 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2121 case 2: /* ERETAA */
2122 case 3: /* ERETAB */
2123 if (!dc_isar_feature(aa64_pauth
, s
)) {
2124 goto do_unallocated
;
2126 if (rn
!= 0x1f || op4
!= 0x1f) {
2127 goto do_unallocated
;
2129 dst
= tcg_temp_new_i64();
2130 tcg_gen_ld_i64(dst
, cpu_env
,
2131 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2132 if (s
->pauth_active
) {
2133 modifier
= cpu_X
[31];
2135 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2137 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2143 goto do_unallocated
;
2145 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2149 gen_helper_exception_return(cpu_env
, dst
);
2150 tcg_temp_free_i64(dst
);
2151 /* Must exit loop to check un-masked IRQs */
2152 s
->base
.is_jmp
= DISAS_EXIT
;
2156 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2157 goto do_unallocated
;
2159 unsupported_encoding(s
, insn
);
2165 unallocated_encoding(s
);
2169 switch (btype_mod
) {
2171 if (dc_isar_feature(aa64_bti
, s
)) {
2172 /* BR to {x16,x17} or !guard -> 1, else 3. */
2173 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2178 if (dc_isar_feature(aa64_bti
, s
)) {
2179 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2184 default: /* RET or none of the above. */
2185 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2189 s
->base
.is_jmp
= DISAS_JUMP
;
2192 /* Branches, exception generating and system instructions */
2193 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2195 switch (extract32(insn
, 25, 7)) {
2196 case 0x0a: case 0x0b:
2197 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2198 disas_uncond_b_imm(s
, insn
);
2200 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2201 disas_comp_b_imm(s
, insn
);
2203 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2204 disas_test_b_imm(s
, insn
);
2206 case 0x2a: /* Conditional branch (immediate) */
2207 disas_cond_b_imm(s
, insn
);
2209 case 0x6a: /* Exception generation / System */
2210 if (insn
& (1 << 24)) {
2211 if (extract32(insn
, 22, 2) == 0) {
2212 disas_system(s
, insn
);
2214 unallocated_encoding(s
);
2220 case 0x6b: /* Unconditional branch (register) */
2221 disas_uncond_b_reg(s
, insn
);
2224 unallocated_encoding(s
);
2230 * Load/Store exclusive instructions are implemented by remembering
2231 * the value/address loaded, and seeing if these are the same
2232 * when the store is performed. This is not actually the architecturally
2233 * mandated semantics, but it works for typical guest code sequences
2234 * and avoids having to monitor regular stores.
2236 * The store exclusive uses the atomic cmpxchg primitives to avoid
2237 * races in multi-threaded linux-user and when MTTCG softmmu is
2240 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2241 TCGv_i64 addr
, int size
, bool is_pair
)
2243 int idx
= get_mem_index(s
);
2244 MemOp memop
= s
->be_data
;
2246 g_assert(size
<= 3);
2248 g_assert(size
>= 2);
2250 /* The pair must be single-copy atomic for the doubleword. */
2251 memop
|= MO_64
| MO_ALIGN
;
2252 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2253 if (s
->be_data
== MO_LE
) {
2254 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2255 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2257 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2258 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2261 /* The pair must be single-copy atomic for *each* doubleword, not
2262 the entire quadword, however it must be quadword aligned. */
2264 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2265 memop
| MO_ALIGN_16
);
2267 TCGv_i64 addr2
= tcg_temp_new_i64();
2268 tcg_gen_addi_i64(addr2
, addr
, 8);
2269 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2270 tcg_temp_free_i64(addr2
);
2272 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2273 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2276 memop
|= size
| MO_ALIGN
;
2277 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2278 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2280 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2283 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2284 TCGv_i64 addr
, int size
, int is_pair
)
2286 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2287 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2290 * [addr + datasize] = {Rt2};
2296 * env->exclusive_addr = -1;
2298 TCGLabel
*fail_label
= gen_new_label();
2299 TCGLabel
*done_label
= gen_new_label();
2302 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2304 tmp
= tcg_temp_new_i64();
2307 if (s
->be_data
== MO_LE
) {
2308 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2310 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2312 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2313 cpu_exclusive_val
, tmp
,
2315 MO_64
| MO_ALIGN
| s
->be_data
);
2316 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2317 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2318 if (!HAVE_CMPXCHG128
) {
2319 gen_helper_exit_atomic(cpu_env
);
2320 s
->base
.is_jmp
= DISAS_NORETURN
;
2321 } else if (s
->be_data
== MO_LE
) {
2322 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2327 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2332 } else if (s
->be_data
== MO_LE
) {
2333 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2334 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2336 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2337 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2340 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2341 cpu_reg(s
, rt
), get_mem_index(s
),
2342 size
| MO_ALIGN
| s
->be_data
);
2343 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2345 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2346 tcg_temp_free_i64(tmp
);
2347 tcg_gen_br(done_label
);
2349 gen_set_label(fail_label
);
2350 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2351 gen_set_label(done_label
);
2352 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2355 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2358 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2359 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2360 int memidx
= get_mem_index(s
);
2361 TCGv_i64 clean_addr
;
2364 gen_check_sp_alignment(s
);
2366 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2367 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2368 size
| MO_ALIGN
| s
->be_data
);
2371 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2374 TCGv_i64 s1
= cpu_reg(s
, rs
);
2375 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2376 TCGv_i64 t1
= cpu_reg(s
, rt
);
2377 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2378 TCGv_i64 clean_addr
;
2379 int memidx
= get_mem_index(s
);
2382 gen_check_sp_alignment(s
);
2384 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2387 TCGv_i64 cmp
= tcg_temp_new_i64();
2388 TCGv_i64 val
= tcg_temp_new_i64();
2390 if (s
->be_data
== MO_LE
) {
2391 tcg_gen_concat32_i64(val
, t1
, t2
);
2392 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2394 tcg_gen_concat32_i64(val
, t2
, t1
);
2395 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2398 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2399 MO_64
| MO_ALIGN
| s
->be_data
);
2400 tcg_temp_free_i64(val
);
2402 if (s
->be_data
== MO_LE
) {
2403 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2405 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2407 tcg_temp_free_i64(cmp
);
2408 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2409 if (HAVE_CMPXCHG128
) {
2410 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2411 if (s
->be_data
== MO_LE
) {
2412 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2413 clean_addr
, t1
, t2
);
2415 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2416 clean_addr
, t1
, t2
);
2418 tcg_temp_free_i32(tcg_rs
);
2420 gen_helper_exit_atomic(cpu_env
);
2421 s
->base
.is_jmp
= DISAS_NORETURN
;
2424 TCGv_i64 d1
= tcg_temp_new_i64();
2425 TCGv_i64 d2
= tcg_temp_new_i64();
2426 TCGv_i64 a2
= tcg_temp_new_i64();
2427 TCGv_i64 c1
= tcg_temp_new_i64();
2428 TCGv_i64 c2
= tcg_temp_new_i64();
2429 TCGv_i64 zero
= tcg_const_i64(0);
2431 /* Load the two words, in memory order. */
2432 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2433 MO_64
| MO_ALIGN_16
| s
->be_data
);
2434 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2435 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2437 /* Compare the two words, also in memory order. */
2438 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2439 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2440 tcg_gen_and_i64(c2
, c2
, c1
);
2442 /* If compare equal, write back new data, else write back old data. */
2443 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2444 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2445 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2446 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2447 tcg_temp_free_i64(a2
);
2448 tcg_temp_free_i64(c1
);
2449 tcg_temp_free_i64(c2
);
2450 tcg_temp_free_i64(zero
);
2452 /* Write back the data from memory to Rs. */
2453 tcg_gen_mov_i64(s1
, d1
);
2454 tcg_gen_mov_i64(s2
, d2
);
2455 tcg_temp_free_i64(d1
);
2456 tcg_temp_free_i64(d2
);
2460 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2461 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2463 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2465 int opc0
= extract32(opc
, 0, 1);
2469 regsize
= opc0
? 32 : 64;
2471 regsize
= size
== 3 ? 64 : 32;
2473 return regsize
== 64;
2476 /* Load/store exclusive
2478 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2479 * +-----+-------------+----+---+----+------+----+-------+------+------+
2480 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2481 * +-----+-------------+----+---+----+------+----+-------+------+------+
2483 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2484 * L: 0 -> store, 1 -> load
2485 * o2: 0 -> exclusive, 1 -> not
2486 * o1: 0 -> single register, 1 -> register pair
2487 * o0: 1 -> load-acquire/store-release, 0 -> not
2489 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2491 int rt
= extract32(insn
, 0, 5);
2492 int rn
= extract32(insn
, 5, 5);
2493 int rt2
= extract32(insn
, 10, 5);
2494 int rs
= extract32(insn
, 16, 5);
2495 int is_lasr
= extract32(insn
, 15, 1);
2496 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2497 int size
= extract32(insn
, 30, 2);
2498 TCGv_i64 clean_addr
;
2500 switch (o2_L_o1_o0
) {
2501 case 0x0: /* STXR */
2502 case 0x1: /* STLXR */
2504 gen_check_sp_alignment(s
);
2507 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2509 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2510 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2513 case 0x4: /* LDXR */
2514 case 0x5: /* LDAXR */
2516 gen_check_sp_alignment(s
);
2518 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2520 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2522 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2526 case 0x8: /* STLLR */
2527 if (!dc_isar_feature(aa64_lor
, s
)) {
2530 /* StoreLORelease is the same as Store-Release for QEMU. */
2532 case 0x9: /* STLR */
2533 /* Generate ISS for non-exclusive accesses including LASR. */
2535 gen_check_sp_alignment(s
);
2537 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2538 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2539 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2540 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2543 case 0xc: /* LDLAR */
2544 if (!dc_isar_feature(aa64_lor
, s
)) {
2547 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2549 case 0xd: /* LDAR */
2550 /* Generate ISS for non-exclusive accesses including LASR. */
2552 gen_check_sp_alignment(s
);
2554 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2555 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2556 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2557 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2560 case 0x2: case 0x3: /* CASP / STXP */
2561 if (size
& 2) { /* STXP / STLXP */
2563 gen_check_sp_alignment(s
);
2566 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2568 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2569 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2573 && ((rt
| rs
) & 1) == 0
2574 && dc_isar_feature(aa64_atomics
, s
)) {
2576 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2581 case 0x6: case 0x7: /* CASPA / LDXP */
2582 if (size
& 2) { /* LDXP / LDAXP */
2584 gen_check_sp_alignment(s
);
2586 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2588 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2590 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2595 && ((rt
| rs
) & 1) == 0
2596 && dc_isar_feature(aa64_atomics
, s
)) {
2597 /* CASPA / CASPAL */
2598 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2604 case 0xb: /* CASL */
2605 case 0xe: /* CASA */
2606 case 0xf: /* CASAL */
2607 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2608 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2613 unallocated_encoding(s
);
2617 * Load register (literal)
2619 * 31 30 29 27 26 25 24 23 5 4 0
2620 * +-----+-------+---+-----+-------------------+-------+
2621 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2622 * +-----+-------+---+-----+-------------------+-------+
2624 * V: 1 -> vector (simd/fp)
2625 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2626 * 10-> 32 bit signed, 11 -> prefetch
2627 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2629 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2631 int rt
= extract32(insn
, 0, 5);
2632 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2633 bool is_vector
= extract32(insn
, 26, 1);
2634 int opc
= extract32(insn
, 30, 2);
2635 bool is_signed
= false;
2637 TCGv_i64 tcg_rt
, clean_addr
;
2641 unallocated_encoding(s
);
2645 if (!fp_access_check(s
)) {
2650 /* PRFM (literal) : prefetch */
2653 size
= 2 + extract32(opc
, 0, 1);
2654 is_signed
= extract32(opc
, 1, 1);
2657 tcg_rt
= cpu_reg(s
, rt
);
2659 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2661 do_fp_ld(s
, rt
, clean_addr
, size
);
2663 /* Only unsigned 32bit loads target 32bit registers. */
2664 bool iss_sf
= opc
!= 0;
2666 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2667 true, rt
, iss_sf
, false);
2669 tcg_temp_free_i64(clean_addr
);
2673 * LDNP (Load Pair - non-temporal hint)
2674 * LDP (Load Pair - non vector)
2675 * LDPSW (Load Pair Signed Word - non vector)
2676 * STNP (Store Pair - non-temporal hint)
2677 * STP (Store Pair - non vector)
2678 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2679 * LDP (Load Pair of SIMD&FP)
2680 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2681 * STP (Store Pair of SIMD&FP)
2683 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2684 * +-----+-------+---+---+-------+---+-----------------------------+
2685 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2686 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2688 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2690 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2691 * V: 0 -> GPR, 1 -> Vector
2692 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2693 * 10 -> signed offset, 11 -> pre-index
2694 * L: 0 -> Store 1 -> Load
2696 * Rt, Rt2 = GPR or SIMD registers to be stored
2697 * Rn = general purpose register containing address
2698 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2700 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2702 int rt
= extract32(insn
, 0, 5);
2703 int rn
= extract32(insn
, 5, 5);
2704 int rt2
= extract32(insn
, 10, 5);
2705 uint64_t offset
= sextract64(insn
, 15, 7);
2706 int index
= extract32(insn
, 23, 2);
2707 bool is_vector
= extract32(insn
, 26, 1);
2708 bool is_load
= extract32(insn
, 22, 1);
2709 int opc
= extract32(insn
, 30, 2);
2711 bool is_signed
= false;
2712 bool postindex
= false;
2715 TCGv_i64 clean_addr
, dirty_addr
;
2720 unallocated_encoding(s
);
2727 size
= 2 + extract32(opc
, 1, 1);
2728 is_signed
= extract32(opc
, 0, 1);
2729 if (!is_load
&& is_signed
) {
2730 unallocated_encoding(s
);
2736 case 1: /* post-index */
2741 /* signed offset with "non-temporal" hint. Since we don't emulate
2742 * caches we don't care about hints to the cache system about
2743 * data access patterns, and handle this identically to plain
2747 /* There is no non-temporal-hint version of LDPSW */
2748 unallocated_encoding(s
);
2753 case 2: /* signed offset, rn not updated */
2756 case 3: /* pre-index */
2762 if (is_vector
&& !fp_access_check(s
)) {
2769 gen_check_sp_alignment(s
);
2772 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2774 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2776 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2780 do_fp_ld(s
, rt
, clean_addr
, size
);
2782 do_fp_st(s
, rt
, clean_addr
, size
);
2784 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2786 do_fp_ld(s
, rt2
, clean_addr
, size
);
2788 do_fp_st(s
, rt2
, clean_addr
, size
);
2791 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2792 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2795 TCGv_i64 tmp
= tcg_temp_new_i64();
2797 /* Do not modify tcg_rt before recognizing any exception
2798 * from the second load.
2800 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2801 false, 0, false, false);
2802 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2803 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2804 false, 0, false, false);
2806 tcg_gen_mov_i64(tcg_rt
, tmp
);
2807 tcg_temp_free_i64(tmp
);
2809 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2810 false, 0, false, false);
2811 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2812 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2813 false, 0, false, false);
2819 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2821 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2826 * Load/store (immediate post-indexed)
2827 * Load/store (immediate pre-indexed)
2828 * Load/store (unscaled immediate)
2830 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2831 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2832 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2833 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2835 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2837 * V = 0 -> non-vector
2838 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2839 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2841 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2847 int rn
= extract32(insn
, 5, 5);
2848 int imm9
= sextract32(insn
, 12, 9);
2849 int idx
= extract32(insn
, 10, 2);
2850 bool is_signed
= false;
2851 bool is_store
= false;
2852 bool is_extended
= false;
2853 bool is_unpriv
= (idx
== 2);
2854 bool iss_valid
= !is_vector
;
2858 TCGv_i64 clean_addr
, dirty_addr
;
2861 size
|= (opc
& 2) << 1;
2862 if (size
> 4 || is_unpriv
) {
2863 unallocated_encoding(s
);
2866 is_store
= ((opc
& 1) == 0);
2867 if (!fp_access_check(s
)) {
2871 if (size
== 3 && opc
== 2) {
2872 /* PRFM - prefetch */
2874 unallocated_encoding(s
);
2879 if (opc
== 3 && size
> 1) {
2880 unallocated_encoding(s
);
2883 is_store
= (opc
== 0);
2884 is_signed
= extract32(opc
, 1, 1);
2885 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2903 g_assert_not_reached();
2907 gen_check_sp_alignment(s
);
2910 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2912 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2914 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2918 do_fp_st(s
, rt
, clean_addr
, size
);
2920 do_fp_ld(s
, rt
, clean_addr
, size
);
2923 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2924 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2925 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2928 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
2929 iss_valid
, rt
, iss_sf
, false);
2931 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
2932 is_signed
, is_extended
, memidx
,
2933 iss_valid
, rt
, iss_sf
, false);
2938 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2940 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2942 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
2947 * Load/store (register offset)
2949 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2950 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2951 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2952 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2955 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2956 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2958 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2959 * opc<0>: 0 -> store, 1 -> load
2960 * V: 1 -> vector/simd
2961 * opt: extend encoding (see DecodeRegExtend)
2962 * S: if S=1 then scale (essentially index by sizeof(size))
2963 * Rt: register to transfer into/out of
2964 * Rn: address register or SP for base
2965 * Rm: offset register or ZR for offset
2967 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2973 int rn
= extract32(insn
, 5, 5);
2974 int shift
= extract32(insn
, 12, 1);
2975 int rm
= extract32(insn
, 16, 5);
2976 int opt
= extract32(insn
, 13, 3);
2977 bool is_signed
= false;
2978 bool is_store
= false;
2979 bool is_extended
= false;
2981 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
2983 if (extract32(opt
, 1, 1) == 0) {
2984 unallocated_encoding(s
);
2989 size
|= (opc
& 2) << 1;
2991 unallocated_encoding(s
);
2994 is_store
= !extract32(opc
, 0, 1);
2995 if (!fp_access_check(s
)) {
2999 if (size
== 3 && opc
== 2) {
3000 /* PRFM - prefetch */
3003 if (opc
== 3 && size
> 1) {
3004 unallocated_encoding(s
);
3007 is_store
= (opc
== 0);
3008 is_signed
= extract32(opc
, 1, 1);
3009 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3013 gen_check_sp_alignment(s
);
3015 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3017 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3018 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3020 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3021 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3025 do_fp_st(s
, rt
, clean_addr
, size
);
3027 do_fp_ld(s
, rt
, clean_addr
, size
);
3030 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3031 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3033 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3034 true, rt
, iss_sf
, false);
3036 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3037 is_signed
, is_extended
,
3038 true, rt
, iss_sf
, false);
3044 * Load/store (unsigned immediate)
3046 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3047 * +----+-------+---+-----+-----+------------+-------+------+
3048 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3049 * +----+-------+---+-----+-----+------------+-------+------+
3052 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3053 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3055 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3056 * opc<0>: 0 -> store, 1 -> load
3057 * Rn: base address register (inc SP)
3058 * Rt: target register
3060 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3066 int rn
= extract32(insn
, 5, 5);
3067 unsigned int imm12
= extract32(insn
, 10, 12);
3068 unsigned int offset
;
3070 TCGv_i64 clean_addr
, dirty_addr
;
3073 bool is_signed
= false;
3074 bool is_extended
= false;
3077 size
|= (opc
& 2) << 1;
3079 unallocated_encoding(s
);
3082 is_store
= !extract32(opc
, 0, 1);
3083 if (!fp_access_check(s
)) {
3087 if (size
== 3 && opc
== 2) {
3088 /* PRFM - prefetch */
3091 if (opc
== 3 && size
> 1) {
3092 unallocated_encoding(s
);
3095 is_store
= (opc
== 0);
3096 is_signed
= extract32(opc
, 1, 1);
3097 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3101 gen_check_sp_alignment(s
);
3103 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3104 offset
= imm12
<< size
;
3105 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3106 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3110 do_fp_st(s
, rt
, clean_addr
, size
);
3112 do_fp_ld(s
, rt
, clean_addr
, size
);
3115 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3116 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3118 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3119 true, rt
, iss_sf
, false);
3121 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3122 true, rt
, iss_sf
, false);
3127 /* Atomic memory operations
3129 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3130 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3131 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3132 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3134 * Rt: the result register
3135 * Rn: base address or SP
3136 * Rs: the source register for the operation
3137 * V: vector flag (always 0 as of v8.3)
3141 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3142 int size
, int rt
, bool is_vector
)
3144 int rs
= extract32(insn
, 16, 5);
3145 int rn
= extract32(insn
, 5, 5);
3146 int o3_opc
= extract32(insn
, 12, 4);
3147 bool r
= extract32(insn
, 22, 1);
3148 bool a
= extract32(insn
, 23, 1);
3149 TCGv_i64 tcg_rs
, clean_addr
;
3150 AtomicThreeOpFn
*fn
;
3152 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3153 unallocated_encoding(s
);
3157 case 000: /* LDADD */
3158 fn
= tcg_gen_atomic_fetch_add_i64
;
3160 case 001: /* LDCLR */
3161 fn
= tcg_gen_atomic_fetch_and_i64
;
3163 case 002: /* LDEOR */
3164 fn
= tcg_gen_atomic_fetch_xor_i64
;
3166 case 003: /* LDSET */
3167 fn
= tcg_gen_atomic_fetch_or_i64
;
3169 case 004: /* LDSMAX */
3170 fn
= tcg_gen_atomic_fetch_smax_i64
;
3172 case 005: /* LDSMIN */
3173 fn
= tcg_gen_atomic_fetch_smin_i64
;
3175 case 006: /* LDUMAX */
3176 fn
= tcg_gen_atomic_fetch_umax_i64
;
3178 case 007: /* LDUMIN */
3179 fn
= tcg_gen_atomic_fetch_umin_i64
;
3182 fn
= tcg_gen_atomic_xchg_i64
;
3184 case 014: /* LDAPR, LDAPRH, LDAPRB */
3185 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3186 rs
!= 31 || a
!= 1 || r
!= 0) {
3187 unallocated_encoding(s
);
3192 unallocated_encoding(s
);
3197 gen_check_sp_alignment(s
);
3199 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
3201 if (o3_opc
== 014) {
3203 * LDAPR* are a special case because they are a simple load, not a
3204 * fetch-and-do-something op.
3205 * The architectural consistency requirements here are weaker than
3206 * full load-acquire (we only need "load-acquire processor consistent"),
3207 * but we choose to implement them as full LDAQ.
3209 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false,
3210 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3211 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3215 tcg_rs
= read_cpu_reg(s
, rs
, true);
3217 if (o3_opc
== 1) { /* LDCLR */
3218 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3221 /* The tcg atomic primitives are all full barriers. Therefore we
3222 * can ignore the Acquire and Release bits of this instruction.
3224 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3225 s
->be_data
| size
| MO_ALIGN
);
3229 * PAC memory operations
3231 * 31 30 27 26 24 22 21 12 11 10 5 0
3232 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3233 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3234 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3236 * Rt: the result register
3237 * Rn: base address or SP
3238 * V: vector flag (always 0 as of v8.3)
3239 * M: clear for key DA, set for key DB
3240 * W: pre-indexing flag
3243 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3244 int size
, int rt
, bool is_vector
)
3246 int rn
= extract32(insn
, 5, 5);
3247 bool is_wback
= extract32(insn
, 11, 1);
3248 bool use_key_a
= !extract32(insn
, 23, 1);
3250 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3252 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3253 unallocated_encoding(s
);
3258 gen_check_sp_alignment(s
);
3260 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3262 if (s
->pauth_active
) {
3264 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3266 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3270 /* Form the 10-bit signed, scaled offset. */
3271 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3272 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3273 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3275 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3276 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3278 tcg_rt
= cpu_reg(s
, rt
);
3279 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3280 /* extend */ false, /* iss_valid */ !is_wback
,
3281 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3284 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3289 * LDAPR/STLR (unscaled immediate)
3291 * 31 30 24 22 21 12 10 5 0
3292 * +------+-------------+-----+---+--------+-----+----+-----+
3293 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3294 * +------+-------------+-----+---+--------+-----+----+-----+
3296 * Rt: source or destination register
3298 * imm9: unscaled immediate offset
3299 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3300 * size: size of load/store
3302 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3304 int rt
= extract32(insn
, 0, 5);
3305 int rn
= extract32(insn
, 5, 5);
3306 int offset
= sextract32(insn
, 12, 9);
3307 int opc
= extract32(insn
, 22, 2);
3308 int size
= extract32(insn
, 30, 2);
3309 TCGv_i64 clean_addr
, dirty_addr
;
3310 bool is_store
= false;
3311 bool is_signed
= false;
3312 bool extend
= false;
3315 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3316 unallocated_encoding(s
);
3321 case 0: /* STLURB */
3324 case 1: /* LDAPUR* */
3326 case 2: /* LDAPURS* 64-bit variant */
3328 unallocated_encoding(s
);
3333 case 3: /* LDAPURS* 32-bit variant */
3335 unallocated_encoding(s
);
3339 extend
= true; /* zero-extend 32->64 after signed load */
3342 g_assert_not_reached();
3345 iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3348 gen_check_sp_alignment(s
);
3351 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3352 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3353 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3356 /* Store-Release semantics */
3357 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3358 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
, iss_sf
, true);
3361 * Load-AcquirePC semantics; we implement as the slightly more
3362 * restrictive Load-Acquire.
3364 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, is_signed
, extend
,
3365 true, rt
, iss_sf
, true);
3366 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3370 /* Load/store register (all forms) */
3371 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3373 int rt
= extract32(insn
, 0, 5);
3374 int opc
= extract32(insn
, 22, 2);
3375 bool is_vector
= extract32(insn
, 26, 1);
3376 int size
= extract32(insn
, 30, 2);
3378 switch (extract32(insn
, 24, 2)) {
3380 if (extract32(insn
, 21, 1) == 0) {
3381 /* Load/store register (unscaled immediate)
3382 * Load/store immediate pre/post-indexed
3383 * Load/store register unprivileged
3385 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3388 switch (extract32(insn
, 10, 2)) {
3390 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3393 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3396 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3401 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3404 unallocated_encoding(s
);
3407 /* AdvSIMD load/store multiple structures
3409 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3410 * +---+---+---------------+---+-------------+--------+------+------+------+
3411 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3412 * +---+---+---------------+---+-------------+--------+------+------+------+
3414 * AdvSIMD load/store multiple structures (post-indexed)
3416 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3417 * +---+---+---------------+---+---+---------+--------+------+------+------+
3418 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3419 * +---+---+---------------+---+---+---------+--------+------+------+------+
3421 * Rt: first (or only) SIMD&FP register to be transferred
3422 * Rn: base address or SP
3423 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3425 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3427 int rt
= extract32(insn
, 0, 5);
3428 int rn
= extract32(insn
, 5, 5);
3429 int rm
= extract32(insn
, 16, 5);
3430 int size
= extract32(insn
, 10, 2);
3431 int opcode
= extract32(insn
, 12, 4);
3432 bool is_store
= !extract32(insn
, 22, 1);
3433 bool is_postidx
= extract32(insn
, 23, 1);
3434 bool is_q
= extract32(insn
, 30, 1);
3435 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3436 MemOp endian
= s
->be_data
;
3438 int ebytes
; /* bytes per element */
3439 int elements
; /* elements per vector */
3440 int rpt
; /* num iterations */
3441 int selem
; /* structure elements */
3444 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3445 unallocated_encoding(s
);
3449 if (!is_postidx
&& rm
!= 0) {
3450 unallocated_encoding(s
);
3454 /* From the shared decode logic */
3485 unallocated_encoding(s
);
3489 if (size
== 3 && !is_q
&& selem
!= 1) {
3491 unallocated_encoding(s
);
3495 if (!fp_access_check(s
)) {
3500 gen_check_sp_alignment(s
);
3503 /* For our purposes, bytes are always little-endian. */
3508 /* Consecutive little-endian elements from a single register
3509 * can be promoted to a larger little-endian operation.
3511 if (selem
== 1 && endian
== MO_LE
) {
3515 elements
= (is_q
? 16 : 8) / ebytes
;
3517 tcg_rn
= cpu_reg_sp(s
, rn
);
3518 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3519 tcg_ebytes
= tcg_const_i64(ebytes
);
3521 for (r
= 0; r
< rpt
; r
++) {
3523 for (e
= 0; e
< elements
; e
++) {
3525 for (xs
= 0; xs
< selem
; xs
++) {
3526 int tt
= (rt
+ r
+ xs
) % 32;
3528 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3530 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3532 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3536 tcg_temp_free_i64(tcg_ebytes
);
3539 /* For non-quad operations, setting a slice of the low
3540 * 64 bits of the register clears the high 64 bits (in
3541 * the ARM ARM pseudocode this is implicit in the fact
3542 * that 'rval' is a 64 bit wide variable).
3543 * For quad operations, we might still need to zero the
3546 for (r
= 0; r
< rpt
* selem
; r
++) {
3547 int tt
= (rt
+ r
) % 32;
3548 clear_vec_high(s
, is_q
, tt
);
3554 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, rpt
* elements
* selem
* ebytes
);
3556 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3561 /* AdvSIMD load/store single structure
3563 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3564 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3565 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3566 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3568 * AdvSIMD load/store single structure (post-indexed)
3570 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3571 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3572 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3573 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3575 * Rt: first (or only) SIMD&FP register to be transferred
3576 * Rn: base address or SP
3577 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3578 * index = encoded in Q:S:size dependent on size
3580 * lane_size = encoded in R, opc
3581 * transfer width = encoded in opc, S, size
3583 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3585 int rt
= extract32(insn
, 0, 5);
3586 int rn
= extract32(insn
, 5, 5);
3587 int rm
= extract32(insn
, 16, 5);
3588 int size
= extract32(insn
, 10, 2);
3589 int S
= extract32(insn
, 12, 1);
3590 int opc
= extract32(insn
, 13, 3);
3591 int R
= extract32(insn
, 21, 1);
3592 int is_load
= extract32(insn
, 22, 1);
3593 int is_postidx
= extract32(insn
, 23, 1);
3594 int is_q
= extract32(insn
, 30, 1);
3596 int scale
= extract32(opc
, 1, 2);
3597 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3598 bool replicate
= false;
3599 int index
= is_q
<< 3 | S
<< 2 | size
;
3601 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3603 if (extract32(insn
, 31, 1)) {
3604 unallocated_encoding(s
);
3607 if (!is_postidx
&& rm
!= 0) {
3608 unallocated_encoding(s
);
3614 if (!is_load
|| S
) {
3615 unallocated_encoding(s
);
3624 if (extract32(size
, 0, 1)) {
3625 unallocated_encoding(s
);
3631 if (extract32(size
, 1, 1)) {
3632 unallocated_encoding(s
);
3635 if (!extract32(size
, 0, 1)) {
3639 unallocated_encoding(s
);
3647 g_assert_not_reached();
3650 if (!fp_access_check(s
)) {
3654 ebytes
= 1 << scale
;
3657 gen_check_sp_alignment(s
);
3660 tcg_rn
= cpu_reg_sp(s
, rn
);
3661 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3662 tcg_ebytes
= tcg_const_i64(ebytes
);
3664 for (xs
= 0; xs
< selem
; xs
++) {
3666 /* Load and replicate to all elements */
3667 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3669 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3670 get_mem_index(s
), s
->be_data
+ scale
);
3671 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3672 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3674 tcg_temp_free_i64(tcg_tmp
);
3676 /* Load/store one element per register */
3678 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3680 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3683 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3686 tcg_temp_free_i64(tcg_ebytes
);
3690 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, selem
* ebytes
);
3692 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3697 /* Loads and stores */
3698 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3700 switch (extract32(insn
, 24, 6)) {
3701 case 0x08: /* Load/store exclusive */
3702 disas_ldst_excl(s
, insn
);
3704 case 0x18: case 0x1c: /* Load register (literal) */
3705 disas_ld_lit(s
, insn
);
3707 case 0x28: case 0x29:
3708 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3709 disas_ldst_pair(s
, insn
);
3711 case 0x38: case 0x39:
3712 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3713 disas_ldst_reg(s
, insn
);
3715 case 0x0c: /* AdvSIMD load/store multiple structures */
3716 disas_ldst_multiple_struct(s
, insn
);
3718 case 0x0d: /* AdvSIMD load/store single structure */
3719 disas_ldst_single_struct(s
, insn
);
3721 case 0x19: /* LDAPR/STLR (unscaled immediate) */
3722 if (extract32(insn
, 10, 2) != 0 ||
3723 extract32(insn
, 21, 1) != 0) {
3724 unallocated_encoding(s
);
3727 disas_ldst_ldapr_stlr(s
, insn
);
3730 unallocated_encoding(s
);
3735 /* PC-rel. addressing
3736 * 31 30 29 28 24 23 5 4 0
3737 * +----+-------+-----------+-------------------+------+
3738 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3739 * +----+-------+-----------+-------------------+------+
3741 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3743 unsigned int page
, rd
;
3747 page
= extract32(insn
, 31, 1);
3748 /* SignExtend(immhi:immlo) -> offset */
3749 offset
= sextract64(insn
, 5, 19);
3750 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3751 rd
= extract32(insn
, 0, 5);
3755 /* ADRP (page based) */
3760 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3764 * Add/subtract (immediate)
3766 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3767 * +--+--+--+-----------+-----+-------------+-----+-----+
3768 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3769 * +--+--+--+-----------+-----+-------------+-----+-----+
3771 * sf: 0 -> 32bit, 1 -> 64bit
3772 * op: 0 -> add , 1 -> sub
3774 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3776 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3778 int rd
= extract32(insn
, 0, 5);
3779 int rn
= extract32(insn
, 5, 5);
3780 uint64_t imm
= extract32(insn
, 10, 12);
3781 int shift
= extract32(insn
, 22, 2);
3782 bool setflags
= extract32(insn
, 29, 1);
3783 bool sub_op
= extract32(insn
, 30, 1);
3784 bool is_64bit
= extract32(insn
, 31, 1);
3786 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3787 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3788 TCGv_i64 tcg_result
;
3797 unallocated_encoding(s
);
3801 tcg_result
= tcg_temp_new_i64();
3804 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3806 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3809 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3811 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3813 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3815 tcg_temp_free_i64(tcg_imm
);
3819 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3821 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3824 tcg_temp_free_i64(tcg_result
);
3827 /* The input should be a value in the bottom e bits (with higher
3828 * bits zero); returns that value replicated into every element
3829 * of size e in a 64 bit integer.
3831 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3841 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3842 static inline uint64_t bitmask64(unsigned int length
)
3844 assert(length
> 0 && length
<= 64);
3845 return ~0ULL >> (64 - length
);
3848 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3849 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3850 * value (ie should cause a guest UNDEF exception), and true if they are
3851 * valid, in which case the decoded bit pattern is written to result.
3853 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3854 unsigned int imms
, unsigned int immr
)
3857 unsigned e
, levels
, s
, r
;
3860 assert(immn
< 2 && imms
< 64 && immr
< 64);
3862 /* The bit patterns we create here are 64 bit patterns which
3863 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3864 * 64 bits each. Each element contains the same value: a run
3865 * of between 1 and e-1 non-zero bits, rotated within the
3866 * element by between 0 and e-1 bits.
3868 * The element size and run length are encoded into immn (1 bit)
3869 * and imms (6 bits) as follows:
3870 * 64 bit elements: immn = 1, imms = <length of run - 1>
3871 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3872 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3873 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3874 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3875 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3876 * Notice that immn = 0, imms = 11111x is the only combination
3877 * not covered by one of the above options; this is reserved.
3878 * Further, <length of run - 1> all-ones is a reserved pattern.
3880 * In all cases the rotation is by immr % e (and immr is 6 bits).
3883 /* First determine the element size */
3884 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3886 /* This is the immn == 0, imms == 0x11111x case */
3896 /* <length of run - 1> mustn't be all-ones. */
3900 /* Create the value of one element: s+1 set bits rotated
3901 * by r within the element (which is e bits wide)...
3903 mask
= bitmask64(s
+ 1);
3905 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3906 mask
&= bitmask64(e
);
3908 /* ...then replicate the element over the whole 64 bit value */
3909 mask
= bitfield_replicate(mask
, e
);
3914 /* Logical (immediate)
3915 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3916 * +----+-----+-------------+---+------+------+------+------+
3917 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3918 * +----+-----+-------------+---+------+------+------+------+
3920 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3922 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3923 TCGv_i64 tcg_rd
, tcg_rn
;
3925 bool is_and
= false;
3927 sf
= extract32(insn
, 31, 1);
3928 opc
= extract32(insn
, 29, 2);
3929 is_n
= extract32(insn
, 22, 1);
3930 immr
= extract32(insn
, 16, 6);
3931 imms
= extract32(insn
, 10, 6);
3932 rn
= extract32(insn
, 5, 5);
3933 rd
= extract32(insn
, 0, 5);
3936 unallocated_encoding(s
);
3940 if (opc
== 0x3) { /* ANDS */
3941 tcg_rd
= cpu_reg(s
, rd
);
3943 tcg_rd
= cpu_reg_sp(s
, rd
);
3945 tcg_rn
= cpu_reg(s
, rn
);
3947 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3948 /* some immediate field values are reserved */
3949 unallocated_encoding(s
);
3954 wmask
&= 0xffffffff;
3958 case 0x3: /* ANDS */
3960 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3964 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3967 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3970 assert(FALSE
); /* must handle all above */
3974 if (!sf
&& !is_and
) {
3975 /* zero extend final result; we know we can skip this for AND
3976 * since the immediate had the high 32 bits clear.
3978 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3981 if (opc
== 3) { /* ANDS */
3982 gen_logic_CC(sf
, tcg_rd
);
3987 * Move wide (immediate)
3989 * 31 30 29 28 23 22 21 20 5 4 0
3990 * +--+-----+-------------+-----+----------------+------+
3991 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3992 * +--+-----+-------------+-----+----------------+------+
3994 * sf: 0 -> 32 bit, 1 -> 64 bit
3995 * opc: 00 -> N, 10 -> Z, 11 -> K
3996 * hw: shift/16 (0,16, and sf only 32, 48)
3998 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
4000 int rd
= extract32(insn
, 0, 5);
4001 uint64_t imm
= extract32(insn
, 5, 16);
4002 int sf
= extract32(insn
, 31, 1);
4003 int opc
= extract32(insn
, 29, 2);
4004 int pos
= extract32(insn
, 21, 2) << 4;
4005 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4008 if (!sf
&& (pos
>= 32)) {
4009 unallocated_encoding(s
);
4023 tcg_gen_movi_i64(tcg_rd
, imm
);
4026 tcg_imm
= tcg_const_i64(imm
);
4027 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
4028 tcg_temp_free_i64(tcg_imm
);
4030 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4034 unallocated_encoding(s
);
4040 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4041 * +----+-----+-------------+---+------+------+------+------+
4042 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4043 * +----+-----+-------------+---+------+------+------+------+
4045 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4047 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4048 TCGv_i64 tcg_rd
, tcg_tmp
;
4050 sf
= extract32(insn
, 31, 1);
4051 opc
= extract32(insn
, 29, 2);
4052 n
= extract32(insn
, 22, 1);
4053 ri
= extract32(insn
, 16, 6);
4054 si
= extract32(insn
, 10, 6);
4055 rn
= extract32(insn
, 5, 5);
4056 rd
= extract32(insn
, 0, 5);
4057 bitsize
= sf
? 64 : 32;
4059 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4060 unallocated_encoding(s
);
4064 tcg_rd
= cpu_reg(s
, rd
);
4066 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4067 to be smaller than bitsize, we'll never reference data outside the
4068 low 32-bits anyway. */
4069 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4071 /* Recognize simple(r) extractions. */
4073 /* Wd<s-r:0> = Wn<s:r> */
4074 len
= (si
- ri
) + 1;
4075 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4076 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4078 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4079 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4082 /* opc == 1, BFXIL fall through to deposit */
4083 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4086 /* Handle the ri > si case with a deposit
4087 * Wd<32+s-r,32-r> = Wn<s:0>
4090 pos
= (bitsize
- ri
) & (bitsize
- 1);
4093 if (opc
== 0 && len
< ri
) {
4094 /* SBFM: sign extend the destination field from len to fill
4095 the balance of the word. Let the deposit below insert all
4096 of those sign bits. */
4097 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4101 if (opc
== 1) { /* BFM, BFXIL */
4102 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4104 /* SBFM or UBFM: We start with zero, and we haven't modified
4105 any bits outside bitsize, therefore the zero-extension
4106 below is unneeded. */
4107 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4112 if (!sf
) { /* zero extend final result */
4113 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4118 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4119 * +----+------+-------------+---+----+------+--------+------+------+
4120 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4121 * +----+------+-------------+---+----+------+--------+------+------+
4123 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4125 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4127 sf
= extract32(insn
, 31, 1);
4128 n
= extract32(insn
, 22, 1);
4129 rm
= extract32(insn
, 16, 5);
4130 imm
= extract32(insn
, 10, 6);
4131 rn
= extract32(insn
, 5, 5);
4132 rd
= extract32(insn
, 0, 5);
4133 op21
= extract32(insn
, 29, 2);
4134 op0
= extract32(insn
, 21, 1);
4135 bitsize
= sf
? 64 : 32;
4137 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4138 unallocated_encoding(s
);
4140 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4142 tcg_rd
= cpu_reg(s
, rd
);
4144 if (unlikely(imm
== 0)) {
4145 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4146 * so an extract from bit 0 is a special case.
4149 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4151 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4154 tcg_rm
= cpu_reg(s
, rm
);
4155 tcg_rn
= cpu_reg(s
, rn
);
4158 /* Specialization to ROR happens in EXTRACT2. */
4159 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4161 TCGv_i32 t0
= tcg_temp_new_i32();
4163 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4165 tcg_gen_rotri_i32(t0
, t0
, imm
);
4167 TCGv_i32 t1
= tcg_temp_new_i32();
4168 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4169 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4170 tcg_temp_free_i32(t1
);
4172 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4173 tcg_temp_free_i32(t0
);
4179 /* Data processing - immediate */
4180 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4182 switch (extract32(insn
, 23, 6)) {
4183 case 0x20: case 0x21: /* PC-rel. addressing */
4184 disas_pc_rel_adr(s
, insn
);
4186 case 0x22: case 0x23: /* Add/subtract (immediate) */
4187 disas_add_sub_imm(s
, insn
);
4189 case 0x24: /* Logical (immediate) */
4190 disas_logic_imm(s
, insn
);
4192 case 0x25: /* Move wide (immediate) */
4193 disas_movw_imm(s
, insn
);
4195 case 0x26: /* Bitfield */
4196 disas_bitfield(s
, insn
);
4198 case 0x27: /* Extract */
4199 disas_extract(s
, insn
);
4202 unallocated_encoding(s
);
4207 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4208 * Note that it is the caller's responsibility to ensure that the
4209 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4210 * mandated semantics for out of range shifts.
4212 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4213 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4215 switch (shift_type
) {
4216 case A64_SHIFT_TYPE_LSL
:
4217 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4219 case A64_SHIFT_TYPE_LSR
:
4220 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4222 case A64_SHIFT_TYPE_ASR
:
4224 tcg_gen_ext32s_i64(dst
, src
);
4226 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4228 case A64_SHIFT_TYPE_ROR
:
4230 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4233 t0
= tcg_temp_new_i32();
4234 t1
= tcg_temp_new_i32();
4235 tcg_gen_extrl_i64_i32(t0
, src
);
4236 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4237 tcg_gen_rotr_i32(t0
, t0
, t1
);
4238 tcg_gen_extu_i32_i64(dst
, t0
);
4239 tcg_temp_free_i32(t0
);
4240 tcg_temp_free_i32(t1
);
4244 assert(FALSE
); /* all shift types should be handled */
4248 if (!sf
) { /* zero extend final result */
4249 tcg_gen_ext32u_i64(dst
, dst
);
4253 /* Shift a TCGv src by immediate, put result in dst.
4254 * The shift amount must be in range (this should always be true as the
4255 * relevant instructions will UNDEF on bad shift immediates).
4257 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4258 enum a64_shift_type shift_type
, unsigned int shift_i
)
4260 assert(shift_i
< (sf
? 64 : 32));
4263 tcg_gen_mov_i64(dst
, src
);
4265 TCGv_i64 shift_const
;
4267 shift_const
= tcg_const_i64(shift_i
);
4268 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4269 tcg_temp_free_i64(shift_const
);
4273 /* Logical (shifted register)
4274 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4275 * +----+-----+-----------+-------+---+------+--------+------+------+
4276 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4277 * +----+-----+-----------+-------+---+------+--------+------+------+
4279 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4281 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4282 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4284 sf
= extract32(insn
, 31, 1);
4285 opc
= extract32(insn
, 29, 2);
4286 shift_type
= extract32(insn
, 22, 2);
4287 invert
= extract32(insn
, 21, 1);
4288 rm
= extract32(insn
, 16, 5);
4289 shift_amount
= extract32(insn
, 10, 6);
4290 rn
= extract32(insn
, 5, 5);
4291 rd
= extract32(insn
, 0, 5);
4293 if (!sf
&& (shift_amount
& (1 << 5))) {
4294 unallocated_encoding(s
);
4298 tcg_rd
= cpu_reg(s
, rd
);
4300 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4301 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4302 * register-register MOV and MVN, so it is worth special casing.
4304 tcg_rm
= cpu_reg(s
, rm
);
4306 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4308 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4312 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4314 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4320 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4323 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4326 tcg_rn
= cpu_reg(s
, rn
);
4328 switch (opc
| (invert
<< 2)) {
4331 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4334 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4337 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4341 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4344 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4347 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4355 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4359 gen_logic_CC(sf
, tcg_rd
);
4364 * Add/subtract (extended register)
4366 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4367 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4368 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4369 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4371 * sf: 0 -> 32bit, 1 -> 64bit
4372 * op: 0 -> add , 1 -> sub
4375 * option: extension type (see DecodeRegExtend)
4376 * imm3: optional shift to Rm
4378 * Rd = Rn + LSL(extend(Rm), amount)
4380 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4382 int rd
= extract32(insn
, 0, 5);
4383 int rn
= extract32(insn
, 5, 5);
4384 int imm3
= extract32(insn
, 10, 3);
4385 int option
= extract32(insn
, 13, 3);
4386 int rm
= extract32(insn
, 16, 5);
4387 int opt
= extract32(insn
, 22, 2);
4388 bool setflags
= extract32(insn
, 29, 1);
4389 bool sub_op
= extract32(insn
, 30, 1);
4390 bool sf
= extract32(insn
, 31, 1);
4392 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4394 TCGv_i64 tcg_result
;
4396 if (imm3
> 4 || opt
!= 0) {
4397 unallocated_encoding(s
);
4401 /* non-flag setting ops may use SP */
4403 tcg_rd
= cpu_reg_sp(s
, rd
);
4405 tcg_rd
= cpu_reg(s
, rd
);
4407 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4409 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4410 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4412 tcg_result
= tcg_temp_new_i64();
4416 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4418 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4422 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4424 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4429 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4431 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4434 tcg_temp_free_i64(tcg_result
);
4438 * Add/subtract (shifted register)
4440 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4441 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4442 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4443 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4445 * sf: 0 -> 32bit, 1 -> 64bit
4446 * op: 0 -> add , 1 -> sub
4448 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4449 * imm6: Shift amount to apply to Rm before the add/sub
4451 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4453 int rd
= extract32(insn
, 0, 5);
4454 int rn
= extract32(insn
, 5, 5);
4455 int imm6
= extract32(insn
, 10, 6);
4456 int rm
= extract32(insn
, 16, 5);
4457 int shift_type
= extract32(insn
, 22, 2);
4458 bool setflags
= extract32(insn
, 29, 1);
4459 bool sub_op
= extract32(insn
, 30, 1);
4460 bool sf
= extract32(insn
, 31, 1);
4462 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4463 TCGv_i64 tcg_rn
, tcg_rm
;
4464 TCGv_i64 tcg_result
;
4466 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4467 unallocated_encoding(s
);
4471 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4472 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4474 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4476 tcg_result
= tcg_temp_new_i64();
4480 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4482 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4486 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4488 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4493 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4495 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4498 tcg_temp_free_i64(tcg_result
);
4501 /* Data-processing (3 source)
4503 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4504 * +--+------+-----------+------+------+----+------+------+------+
4505 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4506 * +--+------+-----------+------+------+----+------+------+------+
4508 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4510 int rd
= extract32(insn
, 0, 5);
4511 int rn
= extract32(insn
, 5, 5);
4512 int ra
= extract32(insn
, 10, 5);
4513 int rm
= extract32(insn
, 16, 5);
4514 int op_id
= (extract32(insn
, 29, 3) << 4) |
4515 (extract32(insn
, 21, 3) << 1) |
4516 extract32(insn
, 15, 1);
4517 bool sf
= extract32(insn
, 31, 1);
4518 bool is_sub
= extract32(op_id
, 0, 1);
4519 bool is_high
= extract32(op_id
, 2, 1);
4520 bool is_signed
= false;
4525 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4527 case 0x42: /* SMADDL */
4528 case 0x43: /* SMSUBL */
4529 case 0x44: /* SMULH */
4532 case 0x0: /* MADD (32bit) */
4533 case 0x1: /* MSUB (32bit) */
4534 case 0x40: /* MADD (64bit) */
4535 case 0x41: /* MSUB (64bit) */
4536 case 0x4a: /* UMADDL */
4537 case 0x4b: /* UMSUBL */
4538 case 0x4c: /* UMULH */
4541 unallocated_encoding(s
);
4546 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4547 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4548 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4549 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4552 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4554 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4557 tcg_temp_free_i64(low_bits
);
4561 tcg_op1
= tcg_temp_new_i64();
4562 tcg_op2
= tcg_temp_new_i64();
4563 tcg_tmp
= tcg_temp_new_i64();
4566 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4567 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4570 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4571 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4573 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4574 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4578 if (ra
== 31 && !is_sub
) {
4579 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4580 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4582 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4584 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4586 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4591 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4594 tcg_temp_free_i64(tcg_op1
);
4595 tcg_temp_free_i64(tcg_op2
);
4596 tcg_temp_free_i64(tcg_tmp
);
4599 /* Add/subtract (with carry)
4600 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4601 * +--+--+--+------------------------+------+-------------+------+-----+
4602 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4603 * +--+--+--+------------------------+------+-------------+------+-----+
4606 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4608 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4609 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4611 sf
= extract32(insn
, 31, 1);
4612 op
= extract32(insn
, 30, 1);
4613 setflags
= extract32(insn
, 29, 1);
4614 rm
= extract32(insn
, 16, 5);
4615 rn
= extract32(insn
, 5, 5);
4616 rd
= extract32(insn
, 0, 5);
4618 tcg_rd
= cpu_reg(s
, rd
);
4619 tcg_rn
= cpu_reg(s
, rn
);
4622 tcg_y
= new_tmp_a64(s
);
4623 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4625 tcg_y
= cpu_reg(s
, rm
);
4629 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4631 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4636 * Rotate right into flags
4637 * 31 30 29 21 15 10 5 4 0
4638 * +--+--+--+-----------------+--------+-----------+------+--+------+
4639 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
4640 * +--+--+--+-----------------+--------+-----------+------+--+------+
4642 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
4644 int mask
= extract32(insn
, 0, 4);
4645 int o2
= extract32(insn
, 4, 1);
4646 int rn
= extract32(insn
, 5, 5);
4647 int imm6
= extract32(insn
, 15, 6);
4648 int sf_op_s
= extract32(insn
, 29, 3);
4652 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
4653 unallocated_encoding(s
);
4657 tcg_rn
= read_cpu_reg(s
, rn
, 1);
4658 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
4660 nzcv
= tcg_temp_new_i32();
4661 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
4663 if (mask
& 8) { /* N */
4664 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
4666 if (mask
& 4) { /* Z */
4667 tcg_gen_not_i32(cpu_ZF
, nzcv
);
4668 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
4670 if (mask
& 2) { /* C */
4671 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
4673 if (mask
& 1) { /* V */
4674 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
4677 tcg_temp_free_i32(nzcv
);
4681 * Evaluate into flags
4682 * 31 30 29 21 15 14 10 5 4 0
4683 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4684 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
4685 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4687 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
4689 int o3_mask
= extract32(insn
, 0, 5);
4690 int rn
= extract32(insn
, 5, 5);
4691 int o2
= extract32(insn
, 15, 6);
4692 int sz
= extract32(insn
, 14, 1);
4693 int sf_op_s
= extract32(insn
, 29, 3);
4697 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
4698 !dc_isar_feature(aa64_condm_4
, s
)) {
4699 unallocated_encoding(s
);
4702 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
4704 tmp
= tcg_temp_new_i32();
4705 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
4706 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
4707 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
4708 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
4709 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
4710 tcg_temp_free_i32(tmp
);
4713 /* Conditional compare (immediate / register)
4714 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4715 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4716 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4717 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4720 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4722 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4723 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4724 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4727 if (!extract32(insn
, 29, 1)) {
4728 unallocated_encoding(s
);
4731 if (insn
& (1 << 10 | 1 << 4)) {
4732 unallocated_encoding(s
);
4735 sf
= extract32(insn
, 31, 1);
4736 op
= extract32(insn
, 30, 1);
4737 is_imm
= extract32(insn
, 11, 1);
4738 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4739 cond
= extract32(insn
, 12, 4);
4740 rn
= extract32(insn
, 5, 5);
4741 nzcv
= extract32(insn
, 0, 4);
4743 /* Set T0 = !COND. */
4744 tcg_t0
= tcg_temp_new_i32();
4745 arm_test_cc(&c
, cond
);
4746 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4749 /* Load the arguments for the new comparison. */
4751 tcg_y
= new_tmp_a64(s
);
4752 tcg_gen_movi_i64(tcg_y
, y
);
4754 tcg_y
= cpu_reg(s
, y
);
4756 tcg_rn
= cpu_reg(s
, rn
);
4758 /* Set the flags for the new comparison. */
4759 tcg_tmp
= tcg_temp_new_i64();
4761 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4763 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4765 tcg_temp_free_i64(tcg_tmp
);
4767 /* If COND was false, force the flags to #nzcv. Compute two masks
4768 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4769 * For tcg hosts that support ANDC, we can make do with just T1.
4770 * In either case, allow the tcg optimizer to delete any unused mask.
4772 tcg_t1
= tcg_temp_new_i32();
4773 tcg_t2
= tcg_temp_new_i32();
4774 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4775 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4777 if (nzcv
& 8) { /* N */
4778 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4780 if (TCG_TARGET_HAS_andc_i32
) {
4781 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4783 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4786 if (nzcv
& 4) { /* Z */
4787 if (TCG_TARGET_HAS_andc_i32
) {
4788 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4790 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4793 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4795 if (nzcv
& 2) { /* C */
4796 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4798 if (TCG_TARGET_HAS_andc_i32
) {
4799 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4801 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4804 if (nzcv
& 1) { /* V */
4805 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4807 if (TCG_TARGET_HAS_andc_i32
) {
4808 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4810 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4813 tcg_temp_free_i32(tcg_t0
);
4814 tcg_temp_free_i32(tcg_t1
);
4815 tcg_temp_free_i32(tcg_t2
);
4818 /* Conditional select
4819 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4820 * +----+----+---+-----------------+------+------+-----+------+------+
4821 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4822 * +----+----+---+-----------------+------+------+-----+------+------+
4824 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4826 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4827 TCGv_i64 tcg_rd
, zero
;
4830 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4831 /* S == 1 or op2<1> == 1 */
4832 unallocated_encoding(s
);
4835 sf
= extract32(insn
, 31, 1);
4836 else_inv
= extract32(insn
, 30, 1);
4837 rm
= extract32(insn
, 16, 5);
4838 cond
= extract32(insn
, 12, 4);
4839 else_inc
= extract32(insn
, 10, 1);
4840 rn
= extract32(insn
, 5, 5);
4841 rd
= extract32(insn
, 0, 5);
4843 tcg_rd
= cpu_reg(s
, rd
);
4845 a64_test_cc(&c
, cond
);
4846 zero
= tcg_const_i64(0);
4848 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4850 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4852 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4855 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4856 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4857 if (else_inv
&& else_inc
) {
4858 tcg_gen_neg_i64(t_false
, t_false
);
4859 } else if (else_inv
) {
4860 tcg_gen_not_i64(t_false
, t_false
);
4861 } else if (else_inc
) {
4862 tcg_gen_addi_i64(t_false
, t_false
, 1);
4864 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4867 tcg_temp_free_i64(zero
);
4871 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4875 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4876 unsigned int rn
, unsigned int rd
)
4878 TCGv_i64 tcg_rd
, tcg_rn
;
4879 tcg_rd
= cpu_reg(s
, rd
);
4880 tcg_rn
= cpu_reg(s
, rn
);
4883 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4885 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4886 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4887 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4888 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4889 tcg_temp_free_i32(tcg_tmp32
);
4893 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4894 unsigned int rn
, unsigned int rd
)
4896 TCGv_i64 tcg_rd
, tcg_rn
;
4897 tcg_rd
= cpu_reg(s
, rd
);
4898 tcg_rn
= cpu_reg(s
, rn
);
4901 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4903 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4904 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4905 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4906 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4907 tcg_temp_free_i32(tcg_tmp32
);
4911 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4912 unsigned int rn
, unsigned int rd
)
4914 TCGv_i64 tcg_rd
, tcg_rn
;
4915 tcg_rd
= cpu_reg(s
, rd
);
4916 tcg_rn
= cpu_reg(s
, rn
);
4919 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4921 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4922 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4923 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4924 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4925 tcg_temp_free_i32(tcg_tmp32
);
4929 /* REV with sf==1, opcode==3 ("REV64") */
4930 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4931 unsigned int rn
, unsigned int rd
)
4934 unallocated_encoding(s
);
4937 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4940 /* REV with sf==0, opcode==2
4941 * REV32 (sf==1, opcode==2)
4943 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4944 unsigned int rn
, unsigned int rd
)
4946 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4949 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4950 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4952 /* bswap32_i64 requires zero high word */
4953 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4954 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4955 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4956 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4957 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4959 tcg_temp_free_i64(tcg_tmp
);
4961 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4962 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4966 /* REV16 (opcode==1) */
4967 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4968 unsigned int rn
, unsigned int rd
)
4970 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4971 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4972 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4973 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4975 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4976 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4977 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4978 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4979 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4981 tcg_temp_free_i64(mask
);
4982 tcg_temp_free_i64(tcg_tmp
);
4985 /* Data-processing (1 source)
4986 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4987 * +----+---+---+-----------------+---------+--------+------+------+
4988 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4989 * +----+---+---+-----------------+---------+--------+------+------+
4991 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4993 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
4996 if (extract32(insn
, 29, 1)) {
4997 unallocated_encoding(s
);
5001 sf
= extract32(insn
, 31, 1);
5002 opcode
= extract32(insn
, 10, 6);
5003 opcode2
= extract32(insn
, 16, 5);
5004 rn
= extract32(insn
, 5, 5);
5005 rd
= extract32(insn
, 0, 5);
5007 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
5009 switch (MAP(sf
, opcode2
, opcode
)) {
5010 case MAP(0, 0x00, 0x00): /* RBIT */
5011 case MAP(1, 0x00, 0x00):
5012 handle_rbit(s
, sf
, rn
, rd
);
5014 case MAP(0, 0x00, 0x01): /* REV16 */
5015 case MAP(1, 0x00, 0x01):
5016 handle_rev16(s
, sf
, rn
, rd
);
5018 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5019 case MAP(1, 0x00, 0x02):
5020 handle_rev32(s
, sf
, rn
, rd
);
5022 case MAP(1, 0x00, 0x03): /* REV64 */
5023 handle_rev64(s
, sf
, rn
, rd
);
5025 case MAP(0, 0x00, 0x04): /* CLZ */
5026 case MAP(1, 0x00, 0x04):
5027 handle_clz(s
, sf
, rn
, rd
);
5029 case MAP(0, 0x00, 0x05): /* CLS */
5030 case MAP(1, 0x00, 0x05):
5031 handle_cls(s
, sf
, rn
, rd
);
5033 case MAP(1, 0x01, 0x00): /* PACIA */
5034 if (s
->pauth_active
) {
5035 tcg_rd
= cpu_reg(s
, rd
);
5036 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5037 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5038 goto do_unallocated
;
5041 case MAP(1, 0x01, 0x01): /* PACIB */
5042 if (s
->pauth_active
) {
5043 tcg_rd
= cpu_reg(s
, rd
);
5044 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5045 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5046 goto do_unallocated
;
5049 case MAP(1, 0x01, 0x02): /* PACDA */
5050 if (s
->pauth_active
) {
5051 tcg_rd
= cpu_reg(s
, rd
);
5052 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5053 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5054 goto do_unallocated
;
5057 case MAP(1, 0x01, 0x03): /* PACDB */
5058 if (s
->pauth_active
) {
5059 tcg_rd
= cpu_reg(s
, rd
);
5060 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5061 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5062 goto do_unallocated
;
5065 case MAP(1, 0x01, 0x04): /* AUTIA */
5066 if (s
->pauth_active
) {
5067 tcg_rd
= cpu_reg(s
, rd
);
5068 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5069 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5070 goto do_unallocated
;
5073 case MAP(1, 0x01, 0x05): /* AUTIB */
5074 if (s
->pauth_active
) {
5075 tcg_rd
= cpu_reg(s
, rd
);
5076 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5077 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5078 goto do_unallocated
;
5081 case MAP(1, 0x01, 0x06): /* AUTDA */
5082 if (s
->pauth_active
) {
5083 tcg_rd
= cpu_reg(s
, rd
);
5084 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5085 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5086 goto do_unallocated
;
5089 case MAP(1, 0x01, 0x07): /* AUTDB */
5090 if (s
->pauth_active
) {
5091 tcg_rd
= cpu_reg(s
, rd
);
5092 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5093 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5094 goto do_unallocated
;
5097 case MAP(1, 0x01, 0x08): /* PACIZA */
5098 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5099 goto do_unallocated
;
5100 } else if (s
->pauth_active
) {
5101 tcg_rd
= cpu_reg(s
, rd
);
5102 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5105 case MAP(1, 0x01, 0x09): /* PACIZB */
5106 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5107 goto do_unallocated
;
5108 } else if (s
->pauth_active
) {
5109 tcg_rd
= cpu_reg(s
, rd
);
5110 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5113 case MAP(1, 0x01, 0x0a): /* PACDZA */
5114 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5115 goto do_unallocated
;
5116 } else if (s
->pauth_active
) {
5117 tcg_rd
= cpu_reg(s
, rd
);
5118 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5121 case MAP(1, 0x01, 0x0b): /* PACDZB */
5122 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5123 goto do_unallocated
;
5124 } else if (s
->pauth_active
) {
5125 tcg_rd
= cpu_reg(s
, rd
);
5126 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5129 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5130 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5131 goto do_unallocated
;
5132 } else if (s
->pauth_active
) {
5133 tcg_rd
= cpu_reg(s
, rd
);
5134 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5137 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5138 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5139 goto do_unallocated
;
5140 } else if (s
->pauth_active
) {
5141 tcg_rd
= cpu_reg(s
, rd
);
5142 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5145 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5146 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5147 goto do_unallocated
;
5148 } else if (s
->pauth_active
) {
5149 tcg_rd
= cpu_reg(s
, rd
);
5150 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5153 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5154 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5155 goto do_unallocated
;
5156 } else if (s
->pauth_active
) {
5157 tcg_rd
= cpu_reg(s
, rd
);
5158 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5161 case MAP(1, 0x01, 0x10): /* XPACI */
5162 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5163 goto do_unallocated
;
5164 } else if (s
->pauth_active
) {
5165 tcg_rd
= cpu_reg(s
, rd
);
5166 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5169 case MAP(1, 0x01, 0x11): /* XPACD */
5170 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5171 goto do_unallocated
;
5172 } else if (s
->pauth_active
) {
5173 tcg_rd
= cpu_reg(s
, rd
);
5174 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5179 unallocated_encoding(s
);
5186 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5187 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5189 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5190 tcg_rd
= cpu_reg(s
, rd
);
5192 if (!sf
&& is_signed
) {
5193 tcg_n
= new_tmp_a64(s
);
5194 tcg_m
= new_tmp_a64(s
);
5195 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5196 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5198 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5199 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5203 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5205 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5208 if (!sf
) { /* zero extend final result */
5209 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5213 /* LSLV, LSRV, ASRV, RORV */
5214 static void handle_shift_reg(DisasContext
*s
,
5215 enum a64_shift_type shift_type
, unsigned int sf
,
5216 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5218 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5219 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5220 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5222 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5223 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5224 tcg_temp_free_i64(tcg_shift
);
5227 /* CRC32[BHWX], CRC32C[BHWX] */
5228 static void handle_crc32(DisasContext
*s
,
5229 unsigned int sf
, unsigned int sz
, bool crc32c
,
5230 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5232 TCGv_i64 tcg_acc
, tcg_val
;
5235 if (!dc_isar_feature(aa64_crc32
, s
)
5236 || (sf
== 1 && sz
!= 3)
5237 || (sf
== 0 && sz
== 3)) {
5238 unallocated_encoding(s
);
5243 tcg_val
= cpu_reg(s
, rm
);
5257 g_assert_not_reached();
5259 tcg_val
= new_tmp_a64(s
);
5260 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5263 tcg_acc
= cpu_reg(s
, rn
);
5264 tcg_bytes
= tcg_const_i32(1 << sz
);
5267 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5269 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5272 tcg_temp_free_i32(tcg_bytes
);
5275 /* Data-processing (2 source)
5276 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5277 * +----+---+---+-----------------+------+--------+------+------+
5278 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5279 * +----+---+---+-----------------+------+--------+------+------+
5281 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5283 unsigned int sf
, rm
, opcode
, rn
, rd
;
5284 sf
= extract32(insn
, 31, 1);
5285 rm
= extract32(insn
, 16, 5);
5286 opcode
= extract32(insn
, 10, 6);
5287 rn
= extract32(insn
, 5, 5);
5288 rd
= extract32(insn
, 0, 5);
5290 if (extract32(insn
, 29, 1)) {
5291 unallocated_encoding(s
);
5297 handle_div(s
, false, sf
, rm
, rn
, rd
);
5300 handle_div(s
, true, sf
, rm
, rn
, rd
);
5303 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5306 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5309 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5312 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5314 case 12: /* PACGA */
5315 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5316 goto do_unallocated
;
5318 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5319 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5328 case 23: /* CRC32 */
5330 int sz
= extract32(opcode
, 0, 2);
5331 bool crc32c
= extract32(opcode
, 2, 1);
5332 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5337 unallocated_encoding(s
);
5343 * Data processing - register
5344 * 31 30 29 28 25 21 20 16 10 0
5345 * +--+---+--+---+-------+-----+-------+-------+---------+
5346 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5347 * +--+---+--+---+-------+-----+-------+-------+---------+
5349 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5351 int op0
= extract32(insn
, 30, 1);
5352 int op1
= extract32(insn
, 28, 1);
5353 int op2
= extract32(insn
, 21, 4);
5354 int op3
= extract32(insn
, 10, 6);
5359 /* Add/sub (extended register) */
5360 disas_add_sub_ext_reg(s
, insn
);
5362 /* Add/sub (shifted register) */
5363 disas_add_sub_reg(s
, insn
);
5366 /* Logical (shifted register) */
5367 disas_logic_reg(s
, insn
);
5375 case 0x00: /* Add/subtract (with carry) */
5376 disas_adc_sbc(s
, insn
);
5379 case 0x01: /* Rotate right into flags */
5381 disas_rotate_right_into_flags(s
, insn
);
5384 case 0x02: /* Evaluate into flags */
5388 disas_evaluate_into_flags(s
, insn
);
5392 goto do_unallocated
;
5396 case 0x2: /* Conditional compare */
5397 disas_cc(s
, insn
); /* both imm and reg forms */
5400 case 0x4: /* Conditional select */
5401 disas_cond_select(s
, insn
);
5404 case 0x6: /* Data-processing */
5405 if (op0
) { /* (1 source) */
5406 disas_data_proc_1src(s
, insn
);
5407 } else { /* (2 source) */
5408 disas_data_proc_2src(s
, insn
);
5411 case 0x8 ... 0xf: /* (3 source) */
5412 disas_data_proc_3src(s
, insn
);
5417 unallocated_encoding(s
);
5422 static void handle_fp_compare(DisasContext
*s
, int size
,
5423 unsigned int rn
, unsigned int rm
,
5424 bool cmp_with_zero
, bool signal_all_nans
)
5426 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5427 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5429 if (size
== MO_64
) {
5430 TCGv_i64 tcg_vn
, tcg_vm
;
5432 tcg_vn
= read_fp_dreg(s
, rn
);
5433 if (cmp_with_zero
) {
5434 tcg_vm
= tcg_const_i64(0);
5436 tcg_vm
= read_fp_dreg(s
, rm
);
5438 if (signal_all_nans
) {
5439 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5441 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5443 tcg_temp_free_i64(tcg_vn
);
5444 tcg_temp_free_i64(tcg_vm
);
5446 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5447 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5449 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5450 if (cmp_with_zero
) {
5451 tcg_gen_movi_i32(tcg_vm
, 0);
5453 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5458 if (signal_all_nans
) {
5459 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5461 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5465 if (signal_all_nans
) {
5466 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5468 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5472 g_assert_not_reached();
5475 tcg_temp_free_i32(tcg_vn
);
5476 tcg_temp_free_i32(tcg_vm
);
5479 tcg_temp_free_ptr(fpst
);
5481 gen_set_nzcv(tcg_flags
);
5483 tcg_temp_free_i64(tcg_flags
);
5486 /* Floating point compare
5487 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5488 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5489 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5490 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5492 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5494 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5497 mos
= extract32(insn
, 29, 3);
5498 type
= extract32(insn
, 22, 2);
5499 rm
= extract32(insn
, 16, 5);
5500 op
= extract32(insn
, 14, 2);
5501 rn
= extract32(insn
, 5, 5);
5502 opc
= extract32(insn
, 3, 2);
5503 op2r
= extract32(insn
, 0, 3);
5505 if (mos
|| op
|| op2r
) {
5506 unallocated_encoding(s
);
5519 if (dc_isar_feature(aa64_fp16
, s
)) {
5524 unallocated_encoding(s
);
5528 if (!fp_access_check(s
)) {
5532 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5535 /* Floating point conditional compare
5536 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5537 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5538 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5539 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5541 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5543 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5545 TCGLabel
*label_continue
= NULL
;
5548 mos
= extract32(insn
, 29, 3);
5549 type
= extract32(insn
, 22, 2);
5550 rm
= extract32(insn
, 16, 5);
5551 cond
= extract32(insn
, 12, 4);
5552 rn
= extract32(insn
, 5, 5);
5553 op
= extract32(insn
, 4, 1);
5554 nzcv
= extract32(insn
, 0, 4);
5557 unallocated_encoding(s
);
5570 if (dc_isar_feature(aa64_fp16
, s
)) {
5575 unallocated_encoding(s
);
5579 if (!fp_access_check(s
)) {
5583 if (cond
< 0x0e) { /* not always */
5584 TCGLabel
*label_match
= gen_new_label();
5585 label_continue
= gen_new_label();
5586 arm_gen_test_cc(cond
, label_match
);
5588 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5589 gen_set_nzcv(tcg_flags
);
5590 tcg_temp_free_i64(tcg_flags
);
5591 tcg_gen_br(label_continue
);
5592 gen_set_label(label_match
);
5595 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5598 gen_set_label(label_continue
);
5602 /* Floating point conditional select
5603 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5604 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5605 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5606 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5608 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5610 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5611 TCGv_i64 t_true
, t_false
, t_zero
;
5615 mos
= extract32(insn
, 29, 3);
5616 type
= extract32(insn
, 22, 2);
5617 rm
= extract32(insn
, 16, 5);
5618 cond
= extract32(insn
, 12, 4);
5619 rn
= extract32(insn
, 5, 5);
5620 rd
= extract32(insn
, 0, 5);
5623 unallocated_encoding(s
);
5636 if (dc_isar_feature(aa64_fp16
, s
)) {
5641 unallocated_encoding(s
);
5645 if (!fp_access_check(s
)) {
5649 /* Zero extend sreg & hreg inputs to 64 bits now. */
5650 t_true
= tcg_temp_new_i64();
5651 t_false
= tcg_temp_new_i64();
5652 read_vec_element(s
, t_true
, rn
, 0, sz
);
5653 read_vec_element(s
, t_false
, rm
, 0, sz
);
5655 a64_test_cc(&c
, cond
);
5656 t_zero
= tcg_const_i64(0);
5657 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5658 tcg_temp_free_i64(t_zero
);
5659 tcg_temp_free_i64(t_false
);
5662 /* Note that sregs & hregs write back zeros to the high bits,
5663 and we've already done the zero-extension. */
5664 write_fp_dreg(s
, rd
, t_true
);
5665 tcg_temp_free_i64(t_true
);
5668 /* Floating-point data-processing (1 source) - half precision */
5669 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5671 TCGv_ptr fpst
= NULL
;
5672 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5673 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5676 case 0x0: /* FMOV */
5677 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5679 case 0x1: /* FABS */
5680 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5682 case 0x2: /* FNEG */
5683 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5685 case 0x3: /* FSQRT */
5686 fpst
= get_fpstatus_ptr(true);
5687 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5689 case 0x8: /* FRINTN */
5690 case 0x9: /* FRINTP */
5691 case 0xa: /* FRINTM */
5692 case 0xb: /* FRINTZ */
5693 case 0xc: /* FRINTA */
5695 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5696 fpst
= get_fpstatus_ptr(true);
5698 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5699 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5701 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5702 tcg_temp_free_i32(tcg_rmode
);
5705 case 0xe: /* FRINTX */
5706 fpst
= get_fpstatus_ptr(true);
5707 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5709 case 0xf: /* FRINTI */
5710 fpst
= get_fpstatus_ptr(true);
5711 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5717 write_fp_sreg(s
, rd
, tcg_res
);
5720 tcg_temp_free_ptr(fpst
);
5722 tcg_temp_free_i32(tcg_op
);
5723 tcg_temp_free_i32(tcg_res
);
5726 /* Floating-point data-processing (1 source) - single precision */
5727 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5729 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
5730 TCGv_i32 tcg_op
, tcg_res
;
5734 tcg_op
= read_fp_sreg(s
, rn
);
5735 tcg_res
= tcg_temp_new_i32();
5738 case 0x0: /* FMOV */
5739 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5741 case 0x1: /* FABS */
5742 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5744 case 0x2: /* FNEG */
5745 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5747 case 0x3: /* FSQRT */
5748 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5750 case 0x8: /* FRINTN */
5751 case 0x9: /* FRINTP */
5752 case 0xa: /* FRINTM */
5753 case 0xb: /* FRINTZ */
5754 case 0xc: /* FRINTA */
5755 rmode
= arm_rmode_to_sf(opcode
& 7);
5756 gen_fpst
= gen_helper_rints
;
5758 case 0xe: /* FRINTX */
5759 gen_fpst
= gen_helper_rints_exact
;
5761 case 0xf: /* FRINTI */
5762 gen_fpst
= gen_helper_rints
;
5764 case 0x10: /* FRINT32Z */
5765 rmode
= float_round_to_zero
;
5766 gen_fpst
= gen_helper_frint32_s
;
5768 case 0x11: /* FRINT32X */
5769 gen_fpst
= gen_helper_frint32_s
;
5771 case 0x12: /* FRINT64Z */
5772 rmode
= float_round_to_zero
;
5773 gen_fpst
= gen_helper_frint64_s
;
5775 case 0x13: /* FRINT64X */
5776 gen_fpst
= gen_helper_frint64_s
;
5779 g_assert_not_reached();
5782 fpst
= get_fpstatus_ptr(false);
5784 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5785 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5786 gen_fpst(tcg_res
, tcg_op
, fpst
);
5787 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5788 tcg_temp_free_i32(tcg_rmode
);
5790 gen_fpst(tcg_res
, tcg_op
, fpst
);
5792 tcg_temp_free_ptr(fpst
);
5795 write_fp_sreg(s
, rd
, tcg_res
);
5796 tcg_temp_free_i32(tcg_op
);
5797 tcg_temp_free_i32(tcg_res
);
5800 /* Floating-point data-processing (1 source) - double precision */
5801 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5803 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
5804 TCGv_i64 tcg_op
, tcg_res
;
5809 case 0x0: /* FMOV */
5810 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5814 tcg_op
= read_fp_dreg(s
, rn
);
5815 tcg_res
= tcg_temp_new_i64();
5818 case 0x1: /* FABS */
5819 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5821 case 0x2: /* FNEG */
5822 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5824 case 0x3: /* FSQRT */
5825 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5827 case 0x8: /* FRINTN */
5828 case 0x9: /* FRINTP */
5829 case 0xa: /* FRINTM */
5830 case 0xb: /* FRINTZ */
5831 case 0xc: /* FRINTA */
5832 rmode
= arm_rmode_to_sf(opcode
& 7);
5833 gen_fpst
= gen_helper_rintd
;
5835 case 0xe: /* FRINTX */
5836 gen_fpst
= gen_helper_rintd_exact
;
5838 case 0xf: /* FRINTI */
5839 gen_fpst
= gen_helper_rintd
;
5841 case 0x10: /* FRINT32Z */
5842 rmode
= float_round_to_zero
;
5843 gen_fpst
= gen_helper_frint32_d
;
5845 case 0x11: /* FRINT32X */
5846 gen_fpst
= gen_helper_frint32_d
;
5848 case 0x12: /* FRINT64Z */
5849 rmode
= float_round_to_zero
;
5850 gen_fpst
= gen_helper_frint64_d
;
5852 case 0x13: /* FRINT64X */
5853 gen_fpst
= gen_helper_frint64_d
;
5856 g_assert_not_reached();
5859 fpst
= get_fpstatus_ptr(false);
5861 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5862 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5863 gen_fpst(tcg_res
, tcg_op
, fpst
);
5864 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5865 tcg_temp_free_i32(tcg_rmode
);
5867 gen_fpst(tcg_res
, tcg_op
, fpst
);
5869 tcg_temp_free_ptr(fpst
);
5872 write_fp_dreg(s
, rd
, tcg_res
);
5873 tcg_temp_free_i64(tcg_op
);
5874 tcg_temp_free_i64(tcg_res
);
5877 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5878 int rd
, int rn
, int dtype
, int ntype
)
5883 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5885 /* Single to double */
5886 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5887 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5888 write_fp_dreg(s
, rd
, tcg_rd
);
5889 tcg_temp_free_i64(tcg_rd
);
5891 /* Single to half */
5892 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5893 TCGv_i32 ahp
= get_ahp_flag();
5894 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5896 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5897 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5898 write_fp_sreg(s
, rd
, tcg_rd
);
5899 tcg_temp_free_i32(tcg_rd
);
5900 tcg_temp_free_i32(ahp
);
5901 tcg_temp_free_ptr(fpst
);
5903 tcg_temp_free_i32(tcg_rn
);
5908 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5909 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5911 /* Double to single */
5912 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5914 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5915 TCGv_i32 ahp
= get_ahp_flag();
5916 /* Double to half */
5917 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5918 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5919 tcg_temp_free_ptr(fpst
);
5920 tcg_temp_free_i32(ahp
);
5922 write_fp_sreg(s
, rd
, tcg_rd
);
5923 tcg_temp_free_i32(tcg_rd
);
5924 tcg_temp_free_i64(tcg_rn
);
5929 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5930 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5931 TCGv_i32 tcg_ahp
= get_ahp_flag();
5932 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5934 /* Half to single */
5935 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5936 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5937 write_fp_sreg(s
, rd
, tcg_rd
);
5938 tcg_temp_free_i32(tcg_rd
);
5940 /* Half to double */
5941 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5942 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5943 write_fp_dreg(s
, rd
, tcg_rd
);
5944 tcg_temp_free_i64(tcg_rd
);
5946 tcg_temp_free_i32(tcg_rn
);
5947 tcg_temp_free_ptr(tcg_fpst
);
5948 tcg_temp_free_i32(tcg_ahp
);
5956 /* Floating point data-processing (1 source)
5957 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5958 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5959 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5960 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5962 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5964 int mos
= extract32(insn
, 29, 3);
5965 int type
= extract32(insn
, 22, 2);
5966 int opcode
= extract32(insn
, 15, 6);
5967 int rn
= extract32(insn
, 5, 5);
5968 int rd
= extract32(insn
, 0, 5);
5971 unallocated_encoding(s
);
5976 case 0x4: case 0x5: case 0x7:
5978 /* FCVT between half, single and double precision */
5979 int dtype
= extract32(opcode
, 0, 2);
5980 if (type
== 2 || dtype
== type
) {
5981 unallocated_encoding(s
);
5984 if (!fp_access_check(s
)) {
5988 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5992 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
5993 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
5994 unallocated_encoding(s
);
6001 /* 32-to-32 and 64-to-64 ops */
6004 if (!fp_access_check(s
)) {
6007 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6010 if (!fp_access_check(s
)) {
6013 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6016 if (!dc_isar_feature(aa64_fp16
, s
)) {
6017 unallocated_encoding(s
);
6021 if (!fp_access_check(s
)) {
6024 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6027 unallocated_encoding(s
);
6032 unallocated_encoding(s
);
6037 /* Floating-point data-processing (2 source) - single precision */
6038 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6039 int rd
, int rn
, int rm
)
6046 tcg_res
= tcg_temp_new_i32();
6047 fpst
= get_fpstatus_ptr(false);
6048 tcg_op1
= read_fp_sreg(s
, rn
);
6049 tcg_op2
= read_fp_sreg(s
, rm
);
6052 case 0x0: /* FMUL */
6053 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6055 case 0x1: /* FDIV */
6056 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6058 case 0x2: /* FADD */
6059 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6061 case 0x3: /* FSUB */
6062 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6064 case 0x4: /* FMAX */
6065 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6067 case 0x5: /* FMIN */
6068 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6070 case 0x6: /* FMAXNM */
6071 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6073 case 0x7: /* FMINNM */
6074 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6076 case 0x8: /* FNMUL */
6077 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6078 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6082 write_fp_sreg(s
, rd
, tcg_res
);
6084 tcg_temp_free_ptr(fpst
);
6085 tcg_temp_free_i32(tcg_op1
);
6086 tcg_temp_free_i32(tcg_op2
);
6087 tcg_temp_free_i32(tcg_res
);
6090 /* Floating-point data-processing (2 source) - double precision */
6091 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6092 int rd
, int rn
, int rm
)
6099 tcg_res
= tcg_temp_new_i64();
6100 fpst
= get_fpstatus_ptr(false);
6101 tcg_op1
= read_fp_dreg(s
, rn
);
6102 tcg_op2
= read_fp_dreg(s
, rm
);
6105 case 0x0: /* FMUL */
6106 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6108 case 0x1: /* FDIV */
6109 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6111 case 0x2: /* FADD */
6112 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6114 case 0x3: /* FSUB */
6115 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6117 case 0x4: /* FMAX */
6118 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6120 case 0x5: /* FMIN */
6121 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6123 case 0x6: /* FMAXNM */
6124 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6126 case 0x7: /* FMINNM */
6127 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6129 case 0x8: /* FNMUL */
6130 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6131 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6135 write_fp_dreg(s
, rd
, tcg_res
);
6137 tcg_temp_free_ptr(fpst
);
6138 tcg_temp_free_i64(tcg_op1
);
6139 tcg_temp_free_i64(tcg_op2
);
6140 tcg_temp_free_i64(tcg_res
);
6143 /* Floating-point data-processing (2 source) - half precision */
6144 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6145 int rd
, int rn
, int rm
)
6152 tcg_res
= tcg_temp_new_i32();
6153 fpst
= get_fpstatus_ptr(true);
6154 tcg_op1
= read_fp_hreg(s
, rn
);
6155 tcg_op2
= read_fp_hreg(s
, rm
);
6158 case 0x0: /* FMUL */
6159 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6161 case 0x1: /* FDIV */
6162 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6164 case 0x2: /* FADD */
6165 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6167 case 0x3: /* FSUB */
6168 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6170 case 0x4: /* FMAX */
6171 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6173 case 0x5: /* FMIN */
6174 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6176 case 0x6: /* FMAXNM */
6177 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6179 case 0x7: /* FMINNM */
6180 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6182 case 0x8: /* FNMUL */
6183 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6184 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6187 g_assert_not_reached();
6190 write_fp_sreg(s
, rd
, tcg_res
);
6192 tcg_temp_free_ptr(fpst
);
6193 tcg_temp_free_i32(tcg_op1
);
6194 tcg_temp_free_i32(tcg_op2
);
6195 tcg_temp_free_i32(tcg_res
);
6198 /* Floating point data-processing (2 source)
6199 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6200 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6201 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6202 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6204 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6206 int mos
= extract32(insn
, 29, 3);
6207 int type
= extract32(insn
, 22, 2);
6208 int rd
= extract32(insn
, 0, 5);
6209 int rn
= extract32(insn
, 5, 5);
6210 int rm
= extract32(insn
, 16, 5);
6211 int opcode
= extract32(insn
, 12, 4);
6213 if (opcode
> 8 || mos
) {
6214 unallocated_encoding(s
);
6220 if (!fp_access_check(s
)) {
6223 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6226 if (!fp_access_check(s
)) {
6229 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6232 if (!dc_isar_feature(aa64_fp16
, s
)) {
6233 unallocated_encoding(s
);
6236 if (!fp_access_check(s
)) {
6239 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6242 unallocated_encoding(s
);
6246 /* Floating-point data-processing (3 source) - single precision */
6247 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6248 int rd
, int rn
, int rm
, int ra
)
6250 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6251 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6252 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6254 tcg_op1
= read_fp_sreg(s
, rn
);
6255 tcg_op2
= read_fp_sreg(s
, rm
);
6256 tcg_op3
= read_fp_sreg(s
, ra
);
6258 /* These are fused multiply-add, and must be done as one
6259 * floating point operation with no rounding between the
6260 * multiplication and addition steps.
6261 * NB that doing the negations here as separate steps is
6262 * correct : an input NaN should come out with its sign bit
6263 * flipped if it is a negated-input.
6266 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6270 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6273 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6275 write_fp_sreg(s
, rd
, tcg_res
);
6277 tcg_temp_free_ptr(fpst
);
6278 tcg_temp_free_i32(tcg_op1
);
6279 tcg_temp_free_i32(tcg_op2
);
6280 tcg_temp_free_i32(tcg_op3
);
6281 tcg_temp_free_i32(tcg_res
);
6284 /* Floating-point data-processing (3 source) - double precision */
6285 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6286 int rd
, int rn
, int rm
, int ra
)
6288 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6289 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6290 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6292 tcg_op1
= read_fp_dreg(s
, rn
);
6293 tcg_op2
= read_fp_dreg(s
, rm
);
6294 tcg_op3
= read_fp_dreg(s
, ra
);
6296 /* These are fused multiply-add, and must be done as one
6297 * floating point operation with no rounding between the
6298 * multiplication and addition steps.
6299 * NB that doing the negations here as separate steps is
6300 * correct : an input NaN should come out with its sign bit
6301 * flipped if it is a negated-input.
6304 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6308 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6311 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6313 write_fp_dreg(s
, rd
, tcg_res
);
6315 tcg_temp_free_ptr(fpst
);
6316 tcg_temp_free_i64(tcg_op1
);
6317 tcg_temp_free_i64(tcg_op2
);
6318 tcg_temp_free_i64(tcg_op3
);
6319 tcg_temp_free_i64(tcg_res
);
6322 /* Floating-point data-processing (3 source) - half precision */
6323 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6324 int rd
, int rn
, int rm
, int ra
)
6326 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6327 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6328 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6330 tcg_op1
= read_fp_hreg(s
, rn
);
6331 tcg_op2
= read_fp_hreg(s
, rm
);
6332 tcg_op3
= read_fp_hreg(s
, ra
);
6334 /* These are fused multiply-add, and must be done as one
6335 * floating point operation with no rounding between the
6336 * multiplication and addition steps.
6337 * NB that doing the negations here as separate steps is
6338 * correct : an input NaN should come out with its sign bit
6339 * flipped if it is a negated-input.
6342 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6346 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6349 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6351 write_fp_sreg(s
, rd
, tcg_res
);
6353 tcg_temp_free_ptr(fpst
);
6354 tcg_temp_free_i32(tcg_op1
);
6355 tcg_temp_free_i32(tcg_op2
);
6356 tcg_temp_free_i32(tcg_op3
);
6357 tcg_temp_free_i32(tcg_res
);
6360 /* Floating point data-processing (3 source)
6361 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6362 * +---+---+---+-----------+------+----+------+----+------+------+------+
6363 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6364 * +---+---+---+-----------+------+----+------+----+------+------+------+
6366 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6368 int mos
= extract32(insn
, 29, 3);
6369 int type
= extract32(insn
, 22, 2);
6370 int rd
= extract32(insn
, 0, 5);
6371 int rn
= extract32(insn
, 5, 5);
6372 int ra
= extract32(insn
, 10, 5);
6373 int rm
= extract32(insn
, 16, 5);
6374 bool o0
= extract32(insn
, 15, 1);
6375 bool o1
= extract32(insn
, 21, 1);
6378 unallocated_encoding(s
);
6384 if (!fp_access_check(s
)) {
6387 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6390 if (!fp_access_check(s
)) {
6393 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6396 if (!dc_isar_feature(aa64_fp16
, s
)) {
6397 unallocated_encoding(s
);
6400 if (!fp_access_check(s
)) {
6403 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6406 unallocated_encoding(s
);
6410 /* Floating point immediate
6411 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6412 * +---+---+---+-----------+------+---+------------+-------+------+------+
6413 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6414 * +---+---+---+-----------+------+---+------------+-------+------+------+
6416 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6418 int rd
= extract32(insn
, 0, 5);
6419 int imm5
= extract32(insn
, 5, 5);
6420 int imm8
= extract32(insn
, 13, 8);
6421 int type
= extract32(insn
, 22, 2);
6422 int mos
= extract32(insn
, 29, 3);
6428 unallocated_encoding(s
);
6441 if (dc_isar_feature(aa64_fp16
, s
)) {
6446 unallocated_encoding(s
);
6450 if (!fp_access_check(s
)) {
6454 imm
= vfp_expand_imm(sz
, imm8
);
6456 tcg_res
= tcg_const_i64(imm
);
6457 write_fp_dreg(s
, rd
, tcg_res
);
6458 tcg_temp_free_i64(tcg_res
);
6461 /* Handle floating point <=> fixed point conversions. Note that we can
6462 * also deal with fp <=> integer conversions as a special case (scale == 64)
6463 * OPTME: consider handling that special case specially or at least skipping
6464 * the call to scalbn in the helpers for zero shifts.
6466 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6467 bool itof
, int rmode
, int scale
, int sf
, int type
)
6469 bool is_signed
= !(opcode
& 1);
6470 TCGv_ptr tcg_fpstatus
;
6471 TCGv_i32 tcg_shift
, tcg_single
;
6472 TCGv_i64 tcg_double
;
6474 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6476 tcg_shift
= tcg_const_i32(64 - scale
);
6479 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6481 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6484 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6486 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6489 tcg_int
= tcg_extend
;
6493 case 1: /* float64 */
6494 tcg_double
= tcg_temp_new_i64();
6496 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6497 tcg_shift
, tcg_fpstatus
);
6499 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6500 tcg_shift
, tcg_fpstatus
);
6502 write_fp_dreg(s
, rd
, tcg_double
);
6503 tcg_temp_free_i64(tcg_double
);
6506 case 0: /* float32 */
6507 tcg_single
= tcg_temp_new_i32();
6509 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6510 tcg_shift
, tcg_fpstatus
);
6512 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6513 tcg_shift
, tcg_fpstatus
);
6515 write_fp_sreg(s
, rd
, tcg_single
);
6516 tcg_temp_free_i32(tcg_single
);
6519 case 3: /* float16 */
6520 tcg_single
= tcg_temp_new_i32();
6522 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6523 tcg_shift
, tcg_fpstatus
);
6525 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6526 tcg_shift
, tcg_fpstatus
);
6528 write_fp_sreg(s
, rd
, tcg_single
);
6529 tcg_temp_free_i32(tcg_single
);
6533 g_assert_not_reached();
6536 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6539 if (extract32(opcode
, 2, 1)) {
6540 /* There are too many rounding modes to all fit into rmode,
6541 * so FCVTA[US] is a special case.
6543 rmode
= FPROUNDING_TIEAWAY
;
6546 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6548 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6551 case 1: /* float64 */
6552 tcg_double
= read_fp_dreg(s
, rn
);
6555 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6556 tcg_shift
, tcg_fpstatus
);
6558 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6559 tcg_shift
, tcg_fpstatus
);
6563 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6564 tcg_shift
, tcg_fpstatus
);
6566 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6567 tcg_shift
, tcg_fpstatus
);
6571 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6573 tcg_temp_free_i64(tcg_double
);
6576 case 0: /* float32 */
6577 tcg_single
= read_fp_sreg(s
, rn
);
6580 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6581 tcg_shift
, tcg_fpstatus
);
6583 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6584 tcg_shift
, tcg_fpstatus
);
6587 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6589 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6590 tcg_shift
, tcg_fpstatus
);
6592 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6593 tcg_shift
, tcg_fpstatus
);
6595 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6596 tcg_temp_free_i32(tcg_dest
);
6598 tcg_temp_free_i32(tcg_single
);
6601 case 3: /* float16 */
6602 tcg_single
= read_fp_sreg(s
, rn
);
6605 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6606 tcg_shift
, tcg_fpstatus
);
6608 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6609 tcg_shift
, tcg_fpstatus
);
6612 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6614 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6615 tcg_shift
, tcg_fpstatus
);
6617 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6618 tcg_shift
, tcg_fpstatus
);
6620 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6621 tcg_temp_free_i32(tcg_dest
);
6623 tcg_temp_free_i32(tcg_single
);
6627 g_assert_not_reached();
6630 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6631 tcg_temp_free_i32(tcg_rmode
);
6634 tcg_temp_free_ptr(tcg_fpstatus
);
6635 tcg_temp_free_i32(tcg_shift
);
6638 /* Floating point <-> fixed point conversions
6639 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6640 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6641 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6642 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6644 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6646 int rd
= extract32(insn
, 0, 5);
6647 int rn
= extract32(insn
, 5, 5);
6648 int scale
= extract32(insn
, 10, 6);
6649 int opcode
= extract32(insn
, 16, 3);
6650 int rmode
= extract32(insn
, 19, 2);
6651 int type
= extract32(insn
, 22, 2);
6652 bool sbit
= extract32(insn
, 29, 1);
6653 bool sf
= extract32(insn
, 31, 1);
6656 if (sbit
|| (!sf
&& scale
< 32)) {
6657 unallocated_encoding(s
);
6662 case 0: /* float32 */
6663 case 1: /* float64 */
6665 case 3: /* float16 */
6666 if (dc_isar_feature(aa64_fp16
, s
)) {
6671 unallocated_encoding(s
);
6675 switch ((rmode
<< 3) | opcode
) {
6676 case 0x2: /* SCVTF */
6677 case 0x3: /* UCVTF */
6680 case 0x18: /* FCVTZS */
6681 case 0x19: /* FCVTZU */
6685 unallocated_encoding(s
);
6689 if (!fp_access_check(s
)) {
6693 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6696 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6698 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6699 * without conversion.
6703 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6709 tmp
= tcg_temp_new_i64();
6710 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6711 write_fp_dreg(s
, rd
, tmp
);
6712 tcg_temp_free_i64(tmp
);
6716 write_fp_dreg(s
, rd
, tcg_rn
);
6719 /* 64 bit to top half. */
6720 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6721 clear_vec_high(s
, true, rd
);
6725 tmp
= tcg_temp_new_i64();
6726 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6727 write_fp_dreg(s
, rd
, tmp
);
6728 tcg_temp_free_i64(tmp
);
6731 g_assert_not_reached();
6734 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6739 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6743 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6746 /* 64 bits from top half */
6747 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6751 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6754 g_assert_not_reached();
6759 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
6761 TCGv_i64 t
= read_fp_dreg(s
, rn
);
6762 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
6764 gen_helper_fjcvtzs(t
, t
, fpstatus
);
6766 tcg_temp_free_ptr(fpstatus
);
6768 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
6769 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
6770 tcg_gen_movi_i32(cpu_CF
, 0);
6771 tcg_gen_movi_i32(cpu_NF
, 0);
6772 tcg_gen_movi_i32(cpu_VF
, 0);
6774 tcg_temp_free_i64(t
);
6777 /* Floating point <-> integer conversions
6778 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6779 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6780 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6781 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6783 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6785 int rd
= extract32(insn
, 0, 5);
6786 int rn
= extract32(insn
, 5, 5);
6787 int opcode
= extract32(insn
, 16, 3);
6788 int rmode
= extract32(insn
, 19, 2);
6789 int type
= extract32(insn
, 22, 2);
6790 bool sbit
= extract32(insn
, 29, 1);
6791 bool sf
= extract32(insn
, 31, 1);
6795 goto do_unallocated
;
6803 case 4: /* FCVTAS */
6804 case 5: /* FCVTAU */
6806 goto do_unallocated
;
6809 case 0: /* FCVT[NPMZ]S */
6810 case 1: /* FCVT[NPMZ]U */
6812 case 0: /* float32 */
6813 case 1: /* float64 */
6815 case 3: /* float16 */
6816 if (!dc_isar_feature(aa64_fp16
, s
)) {
6817 goto do_unallocated
;
6821 goto do_unallocated
;
6823 if (!fp_access_check(s
)) {
6826 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6830 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
6831 case 0b01100110: /* FMOV half <-> 32-bit int */
6833 case 0b11100110: /* FMOV half <-> 64-bit int */
6835 if (!dc_isar_feature(aa64_fp16
, s
)) {
6836 goto do_unallocated
;
6839 case 0b00000110: /* FMOV 32-bit */
6841 case 0b10100110: /* FMOV 64-bit */
6843 case 0b11001110: /* FMOV top half of 128-bit */
6845 if (!fp_access_check(s
)) {
6849 handle_fmov(s
, rd
, rn
, type
, itof
);
6852 case 0b00111110: /* FJCVTZS */
6853 if (!dc_isar_feature(aa64_jscvt
, s
)) {
6854 goto do_unallocated
;
6855 } else if (fp_access_check(s
)) {
6856 handle_fjcvtzs(s
, rd
, rn
);
6862 unallocated_encoding(s
);
6869 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6870 * 31 30 29 28 25 24 0
6871 * +---+---+---+---------+-----------------------------+
6872 * | | 0 | | 1 1 1 1 | |
6873 * +---+---+---+---------+-----------------------------+
6875 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6877 if (extract32(insn
, 24, 1)) {
6878 /* Floating point data-processing (3 source) */
6879 disas_fp_3src(s
, insn
);
6880 } else if (extract32(insn
, 21, 1) == 0) {
6881 /* Floating point to fixed point conversions */
6882 disas_fp_fixed_conv(s
, insn
);
6884 switch (extract32(insn
, 10, 2)) {
6886 /* Floating point conditional compare */
6887 disas_fp_ccomp(s
, insn
);
6890 /* Floating point data-processing (2 source) */
6891 disas_fp_2src(s
, insn
);
6894 /* Floating point conditional select */
6895 disas_fp_csel(s
, insn
);
6898 switch (ctz32(extract32(insn
, 12, 4))) {
6899 case 0: /* [15:12] == xxx1 */
6900 /* Floating point immediate */
6901 disas_fp_imm(s
, insn
);
6903 case 1: /* [15:12] == xx10 */
6904 /* Floating point compare */
6905 disas_fp_compare(s
, insn
);
6907 case 2: /* [15:12] == x100 */
6908 /* Floating point data-processing (1 source) */
6909 disas_fp_1src(s
, insn
);
6911 case 3: /* [15:12] == 1000 */
6912 unallocated_encoding(s
);
6914 default: /* [15:12] == 0000 */
6915 /* Floating point <-> integer conversions */
6916 disas_fp_int_conv(s
, insn
);
6924 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6927 /* Extract 64 bits from the middle of two concatenated 64 bit
6928 * vector register slices left:right. The extracted bits start
6929 * at 'pos' bits into the right (least significant) side.
6930 * We return the result in tcg_right, and guarantee not to
6933 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6934 assert(pos
> 0 && pos
< 64);
6936 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6937 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6938 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6940 tcg_temp_free_i64(tcg_tmp
);
6944 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6945 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6946 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6947 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6949 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6951 int is_q
= extract32(insn
, 30, 1);
6952 int op2
= extract32(insn
, 22, 2);
6953 int imm4
= extract32(insn
, 11, 4);
6954 int rm
= extract32(insn
, 16, 5);
6955 int rn
= extract32(insn
, 5, 5);
6956 int rd
= extract32(insn
, 0, 5);
6957 int pos
= imm4
<< 3;
6958 TCGv_i64 tcg_resl
, tcg_resh
;
6960 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6961 unallocated_encoding(s
);
6965 if (!fp_access_check(s
)) {
6969 tcg_resh
= tcg_temp_new_i64();
6970 tcg_resl
= tcg_temp_new_i64();
6972 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6973 * either extracting 128 bits from a 128:128 concatenation, or
6974 * extracting 64 bits from a 64:64 concatenation.
6977 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6979 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6980 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6982 tcg_gen_movi_i64(tcg_resh
, 0);
6989 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6990 EltPosns
*elt
= eltposns
;
6997 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6999 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7002 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7003 tcg_hh
= tcg_temp_new_i64();
7004 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7005 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7006 tcg_temp_free_i64(tcg_hh
);
7010 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7011 tcg_temp_free_i64(tcg_resl
);
7012 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7013 tcg_temp_free_i64(tcg_resh
);
7014 clear_vec_high(s
, true, rd
);
7018 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7019 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7020 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7021 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7023 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7025 int op2
= extract32(insn
, 22, 2);
7026 int is_q
= extract32(insn
, 30, 1);
7027 int rm
= extract32(insn
, 16, 5);
7028 int rn
= extract32(insn
, 5, 5);
7029 int rd
= extract32(insn
, 0, 5);
7030 int is_tblx
= extract32(insn
, 12, 1);
7031 int len
= extract32(insn
, 13, 2);
7032 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
7033 TCGv_i32 tcg_regno
, tcg_numregs
;
7036 unallocated_encoding(s
);
7040 if (!fp_access_check(s
)) {
7044 /* This does a table lookup: for every byte element in the input
7045 * we index into a table formed from up to four vector registers,
7046 * and then the output is the result of the lookups. Our helper
7047 * function does the lookup operation for a single 64 bit part of
7050 tcg_resl
= tcg_temp_new_i64();
7051 tcg_resh
= tcg_temp_new_i64();
7054 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7056 tcg_gen_movi_i64(tcg_resl
, 0);
7058 if (is_tblx
&& is_q
) {
7059 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7061 tcg_gen_movi_i64(tcg_resh
, 0);
7064 tcg_idx
= tcg_temp_new_i64();
7065 tcg_regno
= tcg_const_i32(rn
);
7066 tcg_numregs
= tcg_const_i32(len
+ 1);
7067 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
7068 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
7069 tcg_regno
, tcg_numregs
);
7071 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
7072 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
7073 tcg_regno
, tcg_numregs
);
7075 tcg_temp_free_i64(tcg_idx
);
7076 tcg_temp_free_i32(tcg_regno
);
7077 tcg_temp_free_i32(tcg_numregs
);
7079 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7080 tcg_temp_free_i64(tcg_resl
);
7081 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7082 tcg_temp_free_i64(tcg_resh
);
7083 clear_vec_high(s
, true, rd
);
7087 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7088 * +---+---+-------------+------+---+------+---+------------------+------+
7089 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7090 * +---+---+-------------+------+---+------+---+------------------+------+
7092 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7094 int rd
= extract32(insn
, 0, 5);
7095 int rn
= extract32(insn
, 5, 5);
7096 int rm
= extract32(insn
, 16, 5);
7097 int size
= extract32(insn
, 22, 2);
7098 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7099 * bit 2 indicates 1 vs 2 variant of the insn.
7101 int opcode
= extract32(insn
, 12, 2);
7102 bool part
= extract32(insn
, 14, 1);
7103 bool is_q
= extract32(insn
, 30, 1);
7104 int esize
= 8 << size
;
7106 int datasize
= is_q
? 128 : 64;
7107 int elements
= datasize
/ esize
;
7108 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7110 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7111 unallocated_encoding(s
);
7115 if (!fp_access_check(s
)) {
7119 tcg_resl
= tcg_const_i64(0);
7120 tcg_resh
= tcg_const_i64(0);
7121 tcg_res
= tcg_temp_new_i64();
7123 for (i
= 0; i
< elements
; i
++) {
7125 case 1: /* UZP1/2 */
7127 int midpoint
= elements
/ 2;
7129 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7131 read_vec_element(s
, tcg_res
, rm
,
7132 2 * (i
- midpoint
) + part
, size
);
7136 case 2: /* TRN1/2 */
7138 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7140 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7143 case 3: /* ZIP1/2 */
7145 int base
= part
* elements
/ 2;
7147 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7149 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7154 g_assert_not_reached();
7159 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7160 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7162 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7163 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7167 tcg_temp_free_i64(tcg_res
);
7169 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7170 tcg_temp_free_i64(tcg_resl
);
7171 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7172 tcg_temp_free_i64(tcg_resh
);
7173 clear_vec_high(s
, true, rd
);
7177 * do_reduction_op helper
7179 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7180 * important for correct NaN propagation that we do these
7181 * operations in exactly the order specified by the pseudocode.
7183 * This is a recursive function, TCG temps should be freed by the
7184 * calling function once it is done with the values.
7186 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7187 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7189 if (esize
== size
) {
7191 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7194 /* We should have one register left here */
7195 assert(ctpop8(vmap
) == 1);
7196 element
= ctz32(vmap
);
7197 assert(element
< 8);
7199 tcg_elem
= tcg_temp_new_i32();
7200 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7203 int bits
= size
/ 2;
7204 int shift
= ctpop8(vmap
) / 2;
7205 int vmap_lo
= (vmap
>> shift
) & vmap
;
7206 int vmap_hi
= (vmap
& ~vmap_lo
);
7207 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7209 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7210 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7211 tcg_res
= tcg_temp_new_i32();
7214 case 0x0c: /* fmaxnmv half-precision */
7215 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7217 case 0x0f: /* fmaxv half-precision */
7218 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7220 case 0x1c: /* fminnmv half-precision */
7221 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7223 case 0x1f: /* fminv half-precision */
7224 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7226 case 0x2c: /* fmaxnmv */
7227 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7229 case 0x2f: /* fmaxv */
7230 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7232 case 0x3c: /* fminnmv */
7233 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7235 case 0x3f: /* fminv */
7236 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7239 g_assert_not_reached();
7242 tcg_temp_free_i32(tcg_hi
);
7243 tcg_temp_free_i32(tcg_lo
);
7248 /* AdvSIMD across lanes
7249 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7250 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7251 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7252 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7254 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7256 int rd
= extract32(insn
, 0, 5);
7257 int rn
= extract32(insn
, 5, 5);
7258 int size
= extract32(insn
, 22, 2);
7259 int opcode
= extract32(insn
, 12, 5);
7260 bool is_q
= extract32(insn
, 30, 1);
7261 bool is_u
= extract32(insn
, 29, 1);
7263 bool is_min
= false;
7267 TCGv_i64 tcg_res
, tcg_elt
;
7270 case 0x1b: /* ADDV */
7272 unallocated_encoding(s
);
7276 case 0x3: /* SADDLV, UADDLV */
7277 case 0xa: /* SMAXV, UMAXV */
7278 case 0x1a: /* SMINV, UMINV */
7279 if (size
== 3 || (size
== 2 && !is_q
)) {
7280 unallocated_encoding(s
);
7284 case 0xc: /* FMAXNMV, FMINNMV */
7285 case 0xf: /* FMAXV, FMINV */
7286 /* Bit 1 of size field encodes min vs max and the actual size
7287 * depends on the encoding of the U bit. If not set (and FP16
7288 * enabled) then we do half-precision float instead of single
7291 is_min
= extract32(size
, 1, 1);
7293 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7295 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7296 unallocated_encoding(s
);
7303 unallocated_encoding(s
);
7307 if (!fp_access_check(s
)) {
7312 elements
= (is_q
? 128 : 64) / esize
;
7314 tcg_res
= tcg_temp_new_i64();
7315 tcg_elt
= tcg_temp_new_i64();
7317 /* These instructions operate across all lanes of a vector
7318 * to produce a single result. We can guarantee that a 64
7319 * bit intermediate is sufficient:
7320 * + for [US]ADDLV the maximum element size is 32 bits, and
7321 * the result type is 64 bits
7322 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7323 * same as the element size, which is 32 bits at most
7324 * For the integer operations we can choose to work at 64
7325 * or 32 bits and truncate at the end; for simplicity
7326 * we use 64 bits always. The floating point
7327 * ops do require 32 bit intermediates, though.
7330 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7332 for (i
= 1; i
< elements
; i
++) {
7333 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7336 case 0x03: /* SADDLV / UADDLV */
7337 case 0x1b: /* ADDV */
7338 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7340 case 0x0a: /* SMAXV / UMAXV */
7342 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7344 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7347 case 0x1a: /* SMINV / UMINV */
7349 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7351 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7355 g_assert_not_reached();
7360 /* Floating point vector reduction ops which work across 32
7361 * bit (single) or 16 bit (half-precision) intermediates.
7362 * Note that correct NaN propagation requires that we do these
7363 * operations in exactly the order specified by the pseudocode.
7365 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7366 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7367 int vmap
= (1 << elements
) - 1;
7368 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7369 (is_q
? 128 : 64), vmap
, fpst
);
7370 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7371 tcg_temp_free_i32(tcg_res32
);
7372 tcg_temp_free_ptr(fpst
);
7375 tcg_temp_free_i64(tcg_elt
);
7377 /* Now truncate the result to the width required for the final output */
7378 if (opcode
== 0x03) {
7379 /* SADDLV, UADDLV: result is 2*esize */
7385 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7388 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7391 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7396 g_assert_not_reached();
7399 write_fp_dreg(s
, rd
, tcg_res
);
7400 tcg_temp_free_i64(tcg_res
);
7403 /* DUP (Element, Vector)
7405 * 31 30 29 21 20 16 15 10 9 5 4 0
7406 * +---+---+-------------------+--------+-------------+------+------+
7407 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7408 * +---+---+-------------------+--------+-------------+------+------+
7410 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7412 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7415 int size
= ctz32(imm5
);
7418 if (size
> 3 || (size
== 3 && !is_q
)) {
7419 unallocated_encoding(s
);
7423 if (!fp_access_check(s
)) {
7427 index
= imm5
>> (size
+ 1);
7428 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7429 vec_reg_offset(s
, rn
, index
, size
),
7430 is_q
? 16 : 8, vec_full_reg_size(s
));
7433 /* DUP (element, scalar)
7434 * 31 21 20 16 15 10 9 5 4 0
7435 * +-----------------------+--------+-------------+------+------+
7436 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7437 * +-----------------------+--------+-------------+------+------+
7439 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7442 int size
= ctz32(imm5
);
7447 unallocated_encoding(s
);
7451 if (!fp_access_check(s
)) {
7455 index
= imm5
>> (size
+ 1);
7457 /* This instruction just extracts the specified element and
7458 * zero-extends it into the bottom of the destination register.
7460 tmp
= tcg_temp_new_i64();
7461 read_vec_element(s
, tmp
, rn
, index
, size
);
7462 write_fp_dreg(s
, rd
, tmp
);
7463 tcg_temp_free_i64(tmp
);
7468 * 31 30 29 21 20 16 15 10 9 5 4 0
7469 * +---+---+-------------------+--------+-------------+------+------+
7470 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7471 * +---+---+-------------------+--------+-------------+------+------+
7473 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7475 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7478 int size
= ctz32(imm5
);
7479 uint32_t dofs
, oprsz
, maxsz
;
7481 if (size
> 3 || ((size
== 3) && !is_q
)) {
7482 unallocated_encoding(s
);
7486 if (!fp_access_check(s
)) {
7490 dofs
= vec_full_reg_offset(s
, rd
);
7491 oprsz
= is_q
? 16 : 8;
7492 maxsz
= vec_full_reg_size(s
);
7494 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7499 * 31 21 20 16 15 14 11 10 9 5 4 0
7500 * +-----------------------+--------+------------+---+------+------+
7501 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7502 * +-----------------------+--------+------------+---+------+------+
7504 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7505 * index: encoded in imm5<4:size+1>
7507 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7510 int size
= ctz32(imm5
);
7511 int src_index
, dst_index
;
7515 unallocated_encoding(s
);
7519 if (!fp_access_check(s
)) {
7523 dst_index
= extract32(imm5
, 1+size
, 5);
7524 src_index
= extract32(imm4
, size
, 4);
7526 tmp
= tcg_temp_new_i64();
7528 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7529 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7531 tcg_temp_free_i64(tmp
);
7533 /* INS is considered a 128-bit write for SVE. */
7534 clear_vec_high(s
, true, rd
);
7540 * 31 21 20 16 15 10 9 5 4 0
7541 * +-----------------------+--------+-------------+------+------+
7542 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7543 * +-----------------------+--------+-------------+------+------+
7545 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7546 * index: encoded in imm5<4:size+1>
7548 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7550 int size
= ctz32(imm5
);
7554 unallocated_encoding(s
);
7558 if (!fp_access_check(s
)) {
7562 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7563 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7565 /* INS is considered a 128-bit write for SVE. */
7566 clear_vec_high(s
, true, rd
);
7573 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7574 * +---+---+-------------------+--------+-------------+------+------+
7575 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7576 * +---+---+-------------------+--------+-------------+------+------+
7578 * U: unsigned when set
7579 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7581 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7582 int rn
, int rd
, int imm5
)
7584 int size
= ctz32(imm5
);
7588 /* Check for UnallocatedEncodings */
7590 if (size
> 2 || (size
== 2 && !is_q
)) {
7591 unallocated_encoding(s
);
7596 || (size
< 3 && is_q
)
7597 || (size
== 3 && !is_q
)) {
7598 unallocated_encoding(s
);
7603 if (!fp_access_check(s
)) {
7607 element
= extract32(imm5
, 1+size
, 4);
7609 tcg_rd
= cpu_reg(s
, rd
);
7610 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7611 if (is_signed
&& !is_q
) {
7612 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7617 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7618 * +---+---+----+-----------------+------+---+------+---+------+------+
7619 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7620 * +---+---+----+-----------------+------+---+------+---+------+------+
7622 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7624 int rd
= extract32(insn
, 0, 5);
7625 int rn
= extract32(insn
, 5, 5);
7626 int imm4
= extract32(insn
, 11, 4);
7627 int op
= extract32(insn
, 29, 1);
7628 int is_q
= extract32(insn
, 30, 1);
7629 int imm5
= extract32(insn
, 16, 5);
7634 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7636 unallocated_encoding(s
);
7641 /* DUP (element - vector) */
7642 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7646 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7651 handle_simd_insg(s
, rd
, rn
, imm5
);
7653 unallocated_encoding(s
);
7658 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7659 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7662 unallocated_encoding(s
);
7668 /* AdvSIMD modified immediate
7669 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7670 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7671 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7672 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7674 * There are a number of operations that can be carried out here:
7675 * MOVI - move (shifted) imm into register
7676 * MVNI - move inverted (shifted) imm into register
7677 * ORR - bitwise OR of (shifted) imm with register
7678 * BIC - bitwise clear of (shifted) imm with register
7679 * With ARMv8.2 we also have:
7680 * FMOV half-precision
7682 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7684 int rd
= extract32(insn
, 0, 5);
7685 int cmode
= extract32(insn
, 12, 4);
7686 int cmode_3_1
= extract32(cmode
, 1, 3);
7687 int cmode_0
= extract32(cmode
, 0, 1);
7688 int o2
= extract32(insn
, 11, 1);
7689 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7690 bool is_neg
= extract32(insn
, 29, 1);
7691 bool is_q
= extract32(insn
, 30, 1);
7694 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7695 /* Check for FMOV (vector, immediate) - half-precision */
7696 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7697 unallocated_encoding(s
);
7702 if (!fp_access_check(s
)) {
7706 /* See AdvSIMDExpandImm() in ARM ARM */
7707 switch (cmode_3_1
) {
7708 case 0: /* Replicate(Zeros(24):imm8, 2) */
7709 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7710 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7711 case 3: /* Replicate(imm8:Zeros(24), 2) */
7713 int shift
= cmode_3_1
* 8;
7714 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7717 case 4: /* Replicate(Zeros(8):imm8, 4) */
7718 case 5: /* Replicate(imm8:Zeros(8), 4) */
7720 int shift
= (cmode_3_1
& 0x1) * 8;
7721 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7726 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7727 imm
= (abcdefgh
<< 16) | 0xffff;
7729 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7730 imm
= (abcdefgh
<< 8) | 0xff;
7732 imm
= bitfield_replicate(imm
, 32);
7735 if (!cmode_0
&& !is_neg
) {
7736 imm
= bitfield_replicate(abcdefgh
, 8);
7737 } else if (!cmode_0
&& is_neg
) {
7740 for (i
= 0; i
< 8; i
++) {
7741 if ((abcdefgh
) & (1 << i
)) {
7742 imm
|= 0xffULL
<< (i
* 8);
7745 } else if (cmode_0
) {
7747 imm
= (abcdefgh
& 0x3f) << 48;
7748 if (abcdefgh
& 0x80) {
7749 imm
|= 0x8000000000000000ULL
;
7751 if (abcdefgh
& 0x40) {
7752 imm
|= 0x3fc0000000000000ULL
;
7754 imm
|= 0x4000000000000000ULL
;
7758 /* FMOV (vector, immediate) - half-precision */
7759 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7760 /* now duplicate across the lanes */
7761 imm
= bitfield_replicate(imm
, 16);
7763 imm
= (abcdefgh
& 0x3f) << 19;
7764 if (abcdefgh
& 0x80) {
7767 if (abcdefgh
& 0x40) {
7778 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7779 g_assert_not_reached();
7782 if (cmode_3_1
!= 7 && is_neg
) {
7786 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7787 /* MOVI or MVNI, with MVNI negation handled above. */
7788 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7789 vec_full_reg_size(s
), imm
);
7791 /* ORR or BIC, with BIC negation to AND handled above. */
7793 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7795 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7800 /* AdvSIMD scalar copy
7801 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7802 * +-----+----+-----------------+------+---+------+---+------+------+
7803 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7804 * +-----+----+-----------------+------+---+------+---+------+------+
7806 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7808 int rd
= extract32(insn
, 0, 5);
7809 int rn
= extract32(insn
, 5, 5);
7810 int imm4
= extract32(insn
, 11, 4);
7811 int imm5
= extract32(insn
, 16, 5);
7812 int op
= extract32(insn
, 29, 1);
7814 if (op
!= 0 || imm4
!= 0) {
7815 unallocated_encoding(s
);
7819 /* DUP (element, scalar) */
7820 handle_simd_dupes(s
, rd
, rn
, imm5
);
7823 /* AdvSIMD scalar pairwise
7824 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7825 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7826 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7827 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7829 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7831 int u
= extract32(insn
, 29, 1);
7832 int size
= extract32(insn
, 22, 2);
7833 int opcode
= extract32(insn
, 12, 5);
7834 int rn
= extract32(insn
, 5, 5);
7835 int rd
= extract32(insn
, 0, 5);
7838 /* For some ops (the FP ones), size[1] is part of the encoding.
7839 * For ADDP strictly it is not but size[1] is always 1 for valid
7842 opcode
|= (extract32(size
, 1, 1) << 5);
7845 case 0x3b: /* ADDP */
7846 if (u
|| size
!= 3) {
7847 unallocated_encoding(s
);
7850 if (!fp_access_check(s
)) {
7856 case 0xc: /* FMAXNMP */
7857 case 0xd: /* FADDP */
7858 case 0xf: /* FMAXP */
7859 case 0x2c: /* FMINNMP */
7860 case 0x2f: /* FMINP */
7861 /* FP op, size[0] is 32 or 64 bit*/
7863 if (!dc_isar_feature(aa64_fp16
, s
)) {
7864 unallocated_encoding(s
);
7870 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7873 if (!fp_access_check(s
)) {
7877 fpst
= get_fpstatus_ptr(size
== MO_16
);
7880 unallocated_encoding(s
);
7884 if (size
== MO_64
) {
7885 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7886 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7887 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7889 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7890 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7893 case 0x3b: /* ADDP */
7894 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7896 case 0xc: /* FMAXNMP */
7897 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7899 case 0xd: /* FADDP */
7900 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7902 case 0xf: /* FMAXP */
7903 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7905 case 0x2c: /* FMINNMP */
7906 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7908 case 0x2f: /* FMINP */
7909 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7912 g_assert_not_reached();
7915 write_fp_dreg(s
, rd
, tcg_res
);
7917 tcg_temp_free_i64(tcg_op1
);
7918 tcg_temp_free_i64(tcg_op2
);
7919 tcg_temp_free_i64(tcg_res
);
7921 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7922 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7923 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7925 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7926 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7928 if (size
== MO_16
) {
7930 case 0xc: /* FMAXNMP */
7931 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7933 case 0xd: /* FADDP */
7934 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7936 case 0xf: /* FMAXP */
7937 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7939 case 0x2c: /* FMINNMP */
7940 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7942 case 0x2f: /* FMINP */
7943 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7946 g_assert_not_reached();
7950 case 0xc: /* FMAXNMP */
7951 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7953 case 0xd: /* FADDP */
7954 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7956 case 0xf: /* FMAXP */
7957 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7959 case 0x2c: /* FMINNMP */
7960 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7962 case 0x2f: /* FMINP */
7963 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7966 g_assert_not_reached();
7970 write_fp_sreg(s
, rd
, tcg_res
);
7972 tcg_temp_free_i32(tcg_op1
);
7973 tcg_temp_free_i32(tcg_op2
);
7974 tcg_temp_free_i32(tcg_res
);
7978 tcg_temp_free_ptr(fpst
);
7983 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7985 * This code is handles the common shifting code and is used by both
7986 * the vector and scalar code.
7988 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7989 TCGv_i64 tcg_rnd
, bool accumulate
,
7990 bool is_u
, int size
, int shift
)
7992 bool extended_result
= false;
7993 bool round
= tcg_rnd
!= NULL
;
7995 TCGv_i64 tcg_src_hi
;
7997 if (round
&& size
== 3) {
7998 extended_result
= true;
7999 ext_lshift
= 64 - shift
;
8000 tcg_src_hi
= tcg_temp_new_i64();
8001 } else if (shift
== 64) {
8002 if (!accumulate
&& is_u
) {
8003 /* result is zero */
8004 tcg_gen_movi_i64(tcg_res
, 0);
8009 /* Deal with the rounding step */
8011 if (extended_result
) {
8012 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8014 /* take care of sign extending tcg_res */
8015 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8016 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8017 tcg_src
, tcg_src_hi
,
8020 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8024 tcg_temp_free_i64(tcg_zero
);
8026 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8030 /* Now do the shift right */
8031 if (round
&& extended_result
) {
8032 /* extended case, >64 bit precision required */
8033 if (ext_lshift
== 0) {
8034 /* special case, only high bits matter */
8035 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8037 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8038 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8039 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8044 /* essentially shifting in 64 zeros */
8045 tcg_gen_movi_i64(tcg_src
, 0);
8047 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8051 /* effectively extending the sign-bit */
8052 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8054 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8060 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8062 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8065 if (extended_result
) {
8066 tcg_temp_free_i64(tcg_src_hi
);
8070 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8071 static void handle_scalar_simd_shri(DisasContext
*s
,
8072 bool is_u
, int immh
, int immb
,
8073 int opcode
, int rn
, int rd
)
8076 int immhb
= immh
<< 3 | immb
;
8077 int shift
= 2 * (8 << size
) - immhb
;
8078 bool accumulate
= false;
8080 bool insert
= false;
8085 if (!extract32(immh
, 3, 1)) {
8086 unallocated_encoding(s
);
8090 if (!fp_access_check(s
)) {
8095 case 0x02: /* SSRA / USRA (accumulate) */
8098 case 0x04: /* SRSHR / URSHR (rounding) */
8101 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8102 accumulate
= round
= true;
8104 case 0x08: /* SRI */
8110 uint64_t round_const
= 1ULL << (shift
- 1);
8111 tcg_round
= tcg_const_i64(round_const
);
8116 tcg_rn
= read_fp_dreg(s
, rn
);
8117 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8120 /* shift count same as element size is valid but does nothing;
8121 * special case to avoid potential shift by 64.
8123 int esize
= 8 << size
;
8124 if (shift
!= esize
) {
8125 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8126 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8129 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8130 accumulate
, is_u
, size
, shift
);
8133 write_fp_dreg(s
, rd
, tcg_rd
);
8135 tcg_temp_free_i64(tcg_rn
);
8136 tcg_temp_free_i64(tcg_rd
);
8138 tcg_temp_free_i64(tcg_round
);
8142 /* SHL/SLI - Scalar shift left */
8143 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8144 int immh
, int immb
, int opcode
,
8147 int size
= 32 - clz32(immh
) - 1;
8148 int immhb
= immh
<< 3 | immb
;
8149 int shift
= immhb
- (8 << size
);
8150 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8151 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8153 if (!extract32(immh
, 3, 1)) {
8154 unallocated_encoding(s
);
8158 if (!fp_access_check(s
)) {
8162 tcg_rn
= read_fp_dreg(s
, rn
);
8163 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8166 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8168 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8171 write_fp_dreg(s
, rd
, tcg_rd
);
8173 tcg_temp_free_i64(tcg_rn
);
8174 tcg_temp_free_i64(tcg_rd
);
8177 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8178 * (signed/unsigned) narrowing */
8179 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8180 bool is_u_shift
, bool is_u_narrow
,
8181 int immh
, int immb
, int opcode
,
8184 int immhb
= immh
<< 3 | immb
;
8185 int size
= 32 - clz32(immh
) - 1;
8186 int esize
= 8 << size
;
8187 int shift
= (2 * esize
) - immhb
;
8188 int elements
= is_scalar
? 1 : (64 / esize
);
8189 bool round
= extract32(opcode
, 0, 1);
8190 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8191 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8192 TCGv_i32 tcg_rd_narrowed
;
8195 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8196 { gen_helper_neon_narrow_sat_s8
,
8197 gen_helper_neon_unarrow_sat8
},
8198 { gen_helper_neon_narrow_sat_s16
,
8199 gen_helper_neon_unarrow_sat16
},
8200 { gen_helper_neon_narrow_sat_s32
,
8201 gen_helper_neon_unarrow_sat32
},
8204 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8205 gen_helper_neon_narrow_sat_u8
,
8206 gen_helper_neon_narrow_sat_u16
,
8207 gen_helper_neon_narrow_sat_u32
,
8210 NeonGenNarrowEnvFn
*narrowfn
;
8216 if (extract32(immh
, 3, 1)) {
8217 unallocated_encoding(s
);
8221 if (!fp_access_check(s
)) {
8226 narrowfn
= unsigned_narrow_fns
[size
];
8228 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8231 tcg_rn
= tcg_temp_new_i64();
8232 tcg_rd
= tcg_temp_new_i64();
8233 tcg_rd_narrowed
= tcg_temp_new_i32();
8234 tcg_final
= tcg_const_i64(0);
8237 uint64_t round_const
= 1ULL << (shift
- 1);
8238 tcg_round
= tcg_const_i64(round_const
);
8243 for (i
= 0; i
< elements
; i
++) {
8244 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8245 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8246 false, is_u_shift
, size
+1, shift
);
8247 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8248 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8249 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8253 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8255 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8259 tcg_temp_free_i64(tcg_round
);
8261 tcg_temp_free_i64(tcg_rn
);
8262 tcg_temp_free_i64(tcg_rd
);
8263 tcg_temp_free_i32(tcg_rd_narrowed
);
8264 tcg_temp_free_i64(tcg_final
);
8266 clear_vec_high(s
, is_q
, rd
);
8269 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8270 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8271 bool src_unsigned
, bool dst_unsigned
,
8272 int immh
, int immb
, int rn
, int rd
)
8274 int immhb
= immh
<< 3 | immb
;
8275 int size
= 32 - clz32(immh
) - 1;
8276 int shift
= immhb
- (8 << size
);
8280 assert(!(scalar
&& is_q
));
8283 if (!is_q
&& extract32(immh
, 3, 1)) {
8284 unallocated_encoding(s
);
8288 /* Since we use the variable-shift helpers we must
8289 * replicate the shift count into each element of
8290 * the tcg_shift value.
8294 shift
|= shift
<< 8;
8297 shift
|= shift
<< 16;
8303 g_assert_not_reached();
8307 if (!fp_access_check(s
)) {
8312 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8313 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8314 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8315 { NULL
, gen_helper_neon_qshl_u64
},
8317 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8318 int maxpass
= is_q
? 2 : 1;
8320 for (pass
= 0; pass
< maxpass
; pass
++) {
8321 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8323 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8324 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8325 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8327 tcg_temp_free_i64(tcg_op
);
8329 tcg_temp_free_i64(tcg_shift
);
8330 clear_vec_high(s
, is_q
, rd
);
8332 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8333 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8335 { gen_helper_neon_qshl_s8
,
8336 gen_helper_neon_qshl_s16
,
8337 gen_helper_neon_qshl_s32
},
8338 { gen_helper_neon_qshlu_s8
,
8339 gen_helper_neon_qshlu_s16
,
8340 gen_helper_neon_qshlu_s32
}
8342 { NULL
, NULL
, NULL
},
8343 { gen_helper_neon_qshl_u8
,
8344 gen_helper_neon_qshl_u16
,
8345 gen_helper_neon_qshl_u32
}
8348 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8349 MemOp memop
= scalar
? size
: MO_32
;
8350 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8352 for (pass
= 0; pass
< maxpass
; pass
++) {
8353 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8355 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8356 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8360 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8363 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8368 g_assert_not_reached();
8370 write_fp_sreg(s
, rd
, tcg_op
);
8372 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8375 tcg_temp_free_i32(tcg_op
);
8377 tcg_temp_free_i32(tcg_shift
);
8380 clear_vec_high(s
, is_q
, rd
);
8385 /* Common vector code for handling integer to FP conversion */
8386 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8387 int elements
, int is_signed
,
8388 int fracbits
, int size
)
8390 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8391 TCGv_i32 tcg_shift
= NULL
;
8393 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8396 if (fracbits
|| size
== MO_64
) {
8397 tcg_shift
= tcg_const_i32(fracbits
);
8400 if (size
== MO_64
) {
8401 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8402 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8404 for (pass
= 0; pass
< elements
; pass
++) {
8405 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8408 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8409 tcg_shift
, tcg_fpst
);
8411 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8412 tcg_shift
, tcg_fpst
);
8414 if (elements
== 1) {
8415 write_fp_dreg(s
, rd
, tcg_double
);
8417 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8421 tcg_temp_free_i64(tcg_int64
);
8422 tcg_temp_free_i64(tcg_double
);
8425 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8426 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8428 for (pass
= 0; pass
< elements
; pass
++) {
8429 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8435 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8436 tcg_shift
, tcg_fpst
);
8438 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8439 tcg_shift
, tcg_fpst
);
8443 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8445 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8452 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8453 tcg_shift
, tcg_fpst
);
8455 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8456 tcg_shift
, tcg_fpst
);
8460 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8462 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8467 g_assert_not_reached();
8470 if (elements
== 1) {
8471 write_fp_sreg(s
, rd
, tcg_float
);
8473 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8477 tcg_temp_free_i32(tcg_int32
);
8478 tcg_temp_free_i32(tcg_float
);
8481 tcg_temp_free_ptr(tcg_fpst
);
8483 tcg_temp_free_i32(tcg_shift
);
8486 clear_vec_high(s
, elements
<< size
== 16, rd
);
8489 /* UCVTF/SCVTF - Integer to FP conversion */
8490 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8491 bool is_q
, bool is_u
,
8492 int immh
, int immb
, int opcode
,
8495 int size
, elements
, fracbits
;
8496 int immhb
= immh
<< 3 | immb
;
8500 if (!is_scalar
&& !is_q
) {
8501 unallocated_encoding(s
);
8504 } else if (immh
& 4) {
8506 } else if (immh
& 2) {
8508 if (!dc_isar_feature(aa64_fp16
, s
)) {
8509 unallocated_encoding(s
);
8513 /* immh == 0 would be a failure of the decode logic */
8514 g_assert(immh
== 1);
8515 unallocated_encoding(s
);
8522 elements
= (8 << is_q
) >> size
;
8524 fracbits
= (16 << size
) - immhb
;
8526 if (!fp_access_check(s
)) {
8530 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8533 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8534 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8535 bool is_q
, bool is_u
,
8536 int immh
, int immb
, int rn
, int rd
)
8538 int immhb
= immh
<< 3 | immb
;
8539 int pass
, size
, fracbits
;
8540 TCGv_ptr tcg_fpstatus
;
8541 TCGv_i32 tcg_rmode
, tcg_shift
;
8545 if (!is_scalar
&& !is_q
) {
8546 unallocated_encoding(s
);
8549 } else if (immh
& 0x4) {
8551 } else if (immh
& 0x2) {
8553 if (!dc_isar_feature(aa64_fp16
, s
)) {
8554 unallocated_encoding(s
);
8558 /* Should have split out AdvSIMD modified immediate earlier. */
8560 unallocated_encoding(s
);
8564 if (!fp_access_check(s
)) {
8568 assert(!(is_scalar
&& is_q
));
8570 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8571 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8572 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8573 fracbits
= (16 << size
) - immhb
;
8574 tcg_shift
= tcg_const_i32(fracbits
);
8576 if (size
== MO_64
) {
8577 int maxpass
= is_scalar
? 1 : 2;
8579 for (pass
= 0; pass
< maxpass
; pass
++) {
8580 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8582 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8584 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8586 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8588 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8589 tcg_temp_free_i64(tcg_op
);
8591 clear_vec_high(s
, is_q
, rd
);
8593 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8594 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8599 fn
= gen_helper_vfp_touhh
;
8601 fn
= gen_helper_vfp_toshh
;
8606 fn
= gen_helper_vfp_touls
;
8608 fn
= gen_helper_vfp_tosls
;
8612 g_assert_not_reached();
8615 for (pass
= 0; pass
< maxpass
; pass
++) {
8616 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8618 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8619 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8621 write_fp_sreg(s
, rd
, tcg_op
);
8623 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8625 tcg_temp_free_i32(tcg_op
);
8628 clear_vec_high(s
, is_q
, rd
);
8632 tcg_temp_free_ptr(tcg_fpstatus
);
8633 tcg_temp_free_i32(tcg_shift
);
8634 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8635 tcg_temp_free_i32(tcg_rmode
);
8638 /* AdvSIMD scalar shift by immediate
8639 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8640 * +-----+---+-------------+------+------+--------+---+------+------+
8641 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8642 * +-----+---+-------------+------+------+--------+---+------+------+
8644 * This is the scalar version so it works on a fixed sized registers
8646 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8648 int rd
= extract32(insn
, 0, 5);
8649 int rn
= extract32(insn
, 5, 5);
8650 int opcode
= extract32(insn
, 11, 5);
8651 int immb
= extract32(insn
, 16, 3);
8652 int immh
= extract32(insn
, 19, 4);
8653 bool is_u
= extract32(insn
, 29, 1);
8656 unallocated_encoding(s
);
8661 case 0x08: /* SRI */
8663 unallocated_encoding(s
);
8667 case 0x00: /* SSHR / USHR */
8668 case 0x02: /* SSRA / USRA */
8669 case 0x04: /* SRSHR / URSHR */
8670 case 0x06: /* SRSRA / URSRA */
8671 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8673 case 0x0a: /* SHL / SLI */
8674 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8676 case 0x1c: /* SCVTF, UCVTF */
8677 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8680 case 0x10: /* SQSHRUN, SQSHRUN2 */
8681 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8683 unallocated_encoding(s
);
8686 handle_vec_simd_sqshrn(s
, true, false, false, true,
8687 immh
, immb
, opcode
, rn
, rd
);
8689 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8690 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8691 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8692 immh
, immb
, opcode
, rn
, rd
);
8694 case 0xc: /* SQSHLU */
8696 unallocated_encoding(s
);
8699 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8701 case 0xe: /* SQSHL, UQSHL */
8702 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8704 case 0x1f: /* FCVTZS, FCVTZU */
8705 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8708 unallocated_encoding(s
);
8713 /* AdvSIMD scalar three different
8714 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8715 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8716 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8717 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8719 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8721 bool is_u
= extract32(insn
, 29, 1);
8722 int size
= extract32(insn
, 22, 2);
8723 int opcode
= extract32(insn
, 12, 4);
8724 int rm
= extract32(insn
, 16, 5);
8725 int rn
= extract32(insn
, 5, 5);
8726 int rd
= extract32(insn
, 0, 5);
8729 unallocated_encoding(s
);
8734 case 0x9: /* SQDMLAL, SQDMLAL2 */
8735 case 0xb: /* SQDMLSL, SQDMLSL2 */
8736 case 0xd: /* SQDMULL, SQDMULL2 */
8737 if (size
== 0 || size
== 3) {
8738 unallocated_encoding(s
);
8743 unallocated_encoding(s
);
8747 if (!fp_access_check(s
)) {
8752 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8753 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8754 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8756 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8757 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8759 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8760 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8763 case 0xd: /* SQDMULL, SQDMULL2 */
8765 case 0xb: /* SQDMLSL, SQDMLSL2 */
8766 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8768 case 0x9: /* SQDMLAL, SQDMLAL2 */
8769 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8770 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8774 g_assert_not_reached();
8777 write_fp_dreg(s
, rd
, tcg_res
);
8779 tcg_temp_free_i64(tcg_op1
);
8780 tcg_temp_free_i64(tcg_op2
);
8781 tcg_temp_free_i64(tcg_res
);
8783 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8784 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8785 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8787 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8788 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8791 case 0xd: /* SQDMULL, SQDMULL2 */
8793 case 0xb: /* SQDMLSL, SQDMLSL2 */
8794 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8796 case 0x9: /* SQDMLAL, SQDMLAL2 */
8798 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8799 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8800 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8802 tcg_temp_free_i64(tcg_op3
);
8806 g_assert_not_reached();
8809 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8810 write_fp_dreg(s
, rd
, tcg_res
);
8812 tcg_temp_free_i32(tcg_op1
);
8813 tcg_temp_free_i32(tcg_op2
);
8814 tcg_temp_free_i64(tcg_res
);
8818 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8819 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8821 /* Handle 64x64->64 opcodes which are shared between the scalar
8822 * and vector 3-same groups. We cover every opcode where size == 3
8823 * is valid in either the three-reg-same (integer, not pairwise)
8824 * or scalar-three-reg-same groups.
8829 case 0x1: /* SQADD */
8831 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8833 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8836 case 0x5: /* SQSUB */
8838 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8840 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8843 case 0x6: /* CMGT, CMHI */
8844 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8845 * We implement this using setcond (test) and then negating.
8847 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8849 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8850 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8852 case 0x7: /* CMGE, CMHS */
8853 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8855 case 0x11: /* CMTST, CMEQ */
8860 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8862 case 0x8: /* SSHL, USHL */
8864 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8866 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8869 case 0x9: /* SQSHL, UQSHL */
8871 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8873 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8876 case 0xa: /* SRSHL, URSHL */
8878 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8880 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8883 case 0xb: /* SQRSHL, UQRSHL */
8885 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8887 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8890 case 0x10: /* ADD, SUB */
8892 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8894 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8898 g_assert_not_reached();
8902 /* Handle the 3-same-operands float operations; shared by the scalar
8903 * and vector encodings. The caller must filter out any encodings
8904 * not allocated for the encoding it is dealing with.
8906 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8907 int fpopcode
, int rd
, int rn
, int rm
)
8910 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8912 for (pass
= 0; pass
< elements
; pass
++) {
8915 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8916 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8917 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8919 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8920 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8923 case 0x39: /* FMLS */
8924 /* As usual for ARM, separate negation for fused multiply-add */
8925 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8927 case 0x19: /* FMLA */
8928 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8929 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8932 case 0x18: /* FMAXNM */
8933 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8935 case 0x1a: /* FADD */
8936 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8938 case 0x1b: /* FMULX */
8939 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8941 case 0x1c: /* FCMEQ */
8942 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8944 case 0x1e: /* FMAX */
8945 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8947 case 0x1f: /* FRECPS */
8948 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8950 case 0x38: /* FMINNM */
8951 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8953 case 0x3a: /* FSUB */
8954 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8956 case 0x3e: /* FMIN */
8957 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8959 case 0x3f: /* FRSQRTS */
8960 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8962 case 0x5b: /* FMUL */
8963 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8965 case 0x5c: /* FCMGE */
8966 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8968 case 0x5d: /* FACGE */
8969 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8971 case 0x5f: /* FDIV */
8972 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8974 case 0x7a: /* FABD */
8975 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8976 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8978 case 0x7c: /* FCMGT */
8979 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8981 case 0x7d: /* FACGT */
8982 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8985 g_assert_not_reached();
8988 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8990 tcg_temp_free_i64(tcg_res
);
8991 tcg_temp_free_i64(tcg_op1
);
8992 tcg_temp_free_i64(tcg_op2
);
8995 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8996 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8997 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8999 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9000 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9003 case 0x39: /* FMLS */
9004 /* As usual for ARM, separate negation for fused multiply-add */
9005 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9007 case 0x19: /* FMLA */
9008 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9009 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9012 case 0x1a: /* FADD */
9013 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9015 case 0x1b: /* FMULX */
9016 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9018 case 0x1c: /* FCMEQ */
9019 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9021 case 0x1e: /* FMAX */
9022 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9024 case 0x1f: /* FRECPS */
9025 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9027 case 0x18: /* FMAXNM */
9028 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9030 case 0x38: /* FMINNM */
9031 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9033 case 0x3a: /* FSUB */
9034 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9036 case 0x3e: /* FMIN */
9037 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9039 case 0x3f: /* FRSQRTS */
9040 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9042 case 0x5b: /* FMUL */
9043 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9045 case 0x5c: /* FCMGE */
9046 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9048 case 0x5d: /* FACGE */
9049 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9051 case 0x5f: /* FDIV */
9052 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9054 case 0x7a: /* FABD */
9055 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9056 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9058 case 0x7c: /* FCMGT */
9059 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9061 case 0x7d: /* FACGT */
9062 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9065 g_assert_not_reached();
9068 if (elements
== 1) {
9069 /* scalar single so clear high part */
9070 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9072 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9073 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9074 tcg_temp_free_i64(tcg_tmp
);
9076 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9079 tcg_temp_free_i32(tcg_res
);
9080 tcg_temp_free_i32(tcg_op1
);
9081 tcg_temp_free_i32(tcg_op2
);
9085 tcg_temp_free_ptr(fpst
);
9087 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9090 /* AdvSIMD scalar three same
9091 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9092 * +-----+---+-----------+------+---+------+--------+---+------+------+
9093 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9094 * +-----+---+-----------+------+---+------+--------+---+------+------+
9096 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9098 int rd
= extract32(insn
, 0, 5);
9099 int rn
= extract32(insn
, 5, 5);
9100 int opcode
= extract32(insn
, 11, 5);
9101 int rm
= extract32(insn
, 16, 5);
9102 int size
= extract32(insn
, 22, 2);
9103 bool u
= extract32(insn
, 29, 1);
9106 if (opcode
>= 0x18) {
9107 /* Floating point: U, size[1] and opcode indicate operation */
9108 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9110 case 0x1b: /* FMULX */
9111 case 0x1f: /* FRECPS */
9112 case 0x3f: /* FRSQRTS */
9113 case 0x5d: /* FACGE */
9114 case 0x7d: /* FACGT */
9115 case 0x1c: /* FCMEQ */
9116 case 0x5c: /* FCMGE */
9117 case 0x7c: /* FCMGT */
9118 case 0x7a: /* FABD */
9121 unallocated_encoding(s
);
9125 if (!fp_access_check(s
)) {
9129 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9134 case 0x1: /* SQADD, UQADD */
9135 case 0x5: /* SQSUB, UQSUB */
9136 case 0x9: /* SQSHL, UQSHL */
9137 case 0xb: /* SQRSHL, UQRSHL */
9139 case 0x8: /* SSHL, USHL */
9140 case 0xa: /* SRSHL, URSHL */
9141 case 0x6: /* CMGT, CMHI */
9142 case 0x7: /* CMGE, CMHS */
9143 case 0x11: /* CMTST, CMEQ */
9144 case 0x10: /* ADD, SUB (vector) */
9146 unallocated_encoding(s
);
9150 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9151 if (size
!= 1 && size
!= 2) {
9152 unallocated_encoding(s
);
9157 unallocated_encoding(s
);
9161 if (!fp_access_check(s
)) {
9165 tcg_rd
= tcg_temp_new_i64();
9168 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9169 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9171 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9172 tcg_temp_free_i64(tcg_rn
);
9173 tcg_temp_free_i64(tcg_rm
);
9175 /* Do a single operation on the lowest element in the vector.
9176 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9177 * no side effects for all these operations.
9178 * OPTME: special-purpose helpers would avoid doing some
9179 * unnecessary work in the helper for the 8 and 16 bit cases.
9181 NeonGenTwoOpEnvFn
*genenvfn
;
9182 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9183 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9184 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9186 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9187 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9190 case 0x1: /* SQADD, UQADD */
9192 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9193 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9194 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9195 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9197 genenvfn
= fns
[size
][u
];
9200 case 0x5: /* SQSUB, UQSUB */
9202 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9203 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9204 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9205 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9207 genenvfn
= fns
[size
][u
];
9210 case 0x9: /* SQSHL, UQSHL */
9212 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9213 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9214 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9215 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9217 genenvfn
= fns
[size
][u
];
9220 case 0xb: /* SQRSHL, UQRSHL */
9222 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9223 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9224 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9225 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9227 genenvfn
= fns
[size
][u
];
9230 case 0x16: /* SQDMULH, SQRDMULH */
9232 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9233 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9234 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9236 assert(size
== 1 || size
== 2);
9237 genenvfn
= fns
[size
- 1][u
];
9241 g_assert_not_reached();
9244 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9245 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9246 tcg_temp_free_i32(tcg_rd32
);
9247 tcg_temp_free_i32(tcg_rn
);
9248 tcg_temp_free_i32(tcg_rm
);
9251 write_fp_dreg(s
, rd
, tcg_rd
);
9253 tcg_temp_free_i64(tcg_rd
);
9256 /* AdvSIMD scalar three same FP16
9257 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9258 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9259 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9260 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9261 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9262 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9264 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9267 int rd
= extract32(insn
, 0, 5);
9268 int rn
= extract32(insn
, 5, 5);
9269 int opcode
= extract32(insn
, 11, 3);
9270 int rm
= extract32(insn
, 16, 5);
9271 bool u
= extract32(insn
, 29, 1);
9272 bool a
= extract32(insn
, 23, 1);
9273 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9280 case 0x03: /* FMULX */
9281 case 0x04: /* FCMEQ (reg) */
9282 case 0x07: /* FRECPS */
9283 case 0x0f: /* FRSQRTS */
9284 case 0x14: /* FCMGE (reg) */
9285 case 0x15: /* FACGE */
9286 case 0x1a: /* FABD */
9287 case 0x1c: /* FCMGT (reg) */
9288 case 0x1d: /* FACGT */
9291 unallocated_encoding(s
);
9295 if (!dc_isar_feature(aa64_fp16
, s
)) {
9296 unallocated_encoding(s
);
9299 if (!fp_access_check(s
)) {
9303 fpst
= get_fpstatus_ptr(true);
9305 tcg_op1
= read_fp_hreg(s
, rn
);
9306 tcg_op2
= read_fp_hreg(s
, rm
);
9307 tcg_res
= tcg_temp_new_i32();
9310 case 0x03: /* FMULX */
9311 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9313 case 0x04: /* FCMEQ (reg) */
9314 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9316 case 0x07: /* FRECPS */
9317 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9319 case 0x0f: /* FRSQRTS */
9320 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9322 case 0x14: /* FCMGE (reg) */
9323 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9325 case 0x15: /* FACGE */
9326 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9328 case 0x1a: /* FABD */
9329 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9330 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9332 case 0x1c: /* FCMGT (reg) */
9333 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9335 case 0x1d: /* FACGT */
9336 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9339 g_assert_not_reached();
9342 write_fp_sreg(s
, rd
, tcg_res
);
9345 tcg_temp_free_i32(tcg_res
);
9346 tcg_temp_free_i32(tcg_op1
);
9347 tcg_temp_free_i32(tcg_op2
);
9348 tcg_temp_free_ptr(fpst
);
9351 /* AdvSIMD scalar three same extra
9352 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9353 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9354 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9355 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9357 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9360 int rd
= extract32(insn
, 0, 5);
9361 int rn
= extract32(insn
, 5, 5);
9362 int opcode
= extract32(insn
, 11, 4);
9363 int rm
= extract32(insn
, 16, 5);
9364 int size
= extract32(insn
, 22, 2);
9365 bool u
= extract32(insn
, 29, 1);
9366 TCGv_i32 ele1
, ele2
, ele3
;
9370 switch (u
* 16 + opcode
) {
9371 case 0x10: /* SQRDMLAH (vector) */
9372 case 0x11: /* SQRDMLSH (vector) */
9373 if (size
!= 1 && size
!= 2) {
9374 unallocated_encoding(s
);
9377 feature
= dc_isar_feature(aa64_rdm
, s
);
9380 unallocated_encoding(s
);
9384 unallocated_encoding(s
);
9387 if (!fp_access_check(s
)) {
9391 /* Do a single operation on the lowest element in the vector.
9392 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9393 * with no side effects for all these operations.
9394 * OPTME: special-purpose helpers would avoid doing some
9395 * unnecessary work in the helper for the 16 bit cases.
9397 ele1
= tcg_temp_new_i32();
9398 ele2
= tcg_temp_new_i32();
9399 ele3
= tcg_temp_new_i32();
9401 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9402 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9403 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9406 case 0x0: /* SQRDMLAH */
9408 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9410 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9413 case 0x1: /* SQRDMLSH */
9415 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9417 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9421 g_assert_not_reached();
9423 tcg_temp_free_i32(ele1
);
9424 tcg_temp_free_i32(ele2
);
9426 res
= tcg_temp_new_i64();
9427 tcg_gen_extu_i32_i64(res
, ele3
);
9428 tcg_temp_free_i32(ele3
);
9430 write_fp_dreg(s
, rd
, res
);
9431 tcg_temp_free_i64(res
);
9434 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9435 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9436 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9438 /* Handle 64->64 opcodes which are shared between the scalar and
9439 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9440 * is valid in either group and also the double-precision fp ops.
9441 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9447 case 0x4: /* CLS, CLZ */
9449 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9451 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9455 /* This opcode is shared with CNT and RBIT but we have earlier
9456 * enforced that size == 3 if and only if this is the NOT insn.
9458 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9460 case 0x7: /* SQABS, SQNEG */
9462 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9464 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9467 case 0xa: /* CMLT */
9468 /* 64 bit integer comparison against zero, result is
9469 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9474 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9475 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9477 case 0x8: /* CMGT, CMGE */
9478 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9480 case 0x9: /* CMEQ, CMLE */
9481 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9483 case 0xb: /* ABS, NEG */
9485 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9487 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9490 case 0x2f: /* FABS */
9491 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9493 case 0x6f: /* FNEG */
9494 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9496 case 0x7f: /* FSQRT */
9497 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9499 case 0x1a: /* FCVTNS */
9500 case 0x1b: /* FCVTMS */
9501 case 0x1c: /* FCVTAS */
9502 case 0x3a: /* FCVTPS */
9503 case 0x3b: /* FCVTZS */
9505 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9506 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9507 tcg_temp_free_i32(tcg_shift
);
9510 case 0x5a: /* FCVTNU */
9511 case 0x5b: /* FCVTMU */
9512 case 0x5c: /* FCVTAU */
9513 case 0x7a: /* FCVTPU */
9514 case 0x7b: /* FCVTZU */
9516 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9517 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9518 tcg_temp_free_i32(tcg_shift
);
9521 case 0x18: /* FRINTN */
9522 case 0x19: /* FRINTM */
9523 case 0x38: /* FRINTP */
9524 case 0x39: /* FRINTZ */
9525 case 0x58: /* FRINTA */
9526 case 0x79: /* FRINTI */
9527 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9529 case 0x59: /* FRINTX */
9530 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9532 case 0x1e: /* FRINT32Z */
9533 case 0x5e: /* FRINT32X */
9534 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9536 case 0x1f: /* FRINT64Z */
9537 case 0x5f: /* FRINT64X */
9538 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9541 g_assert_not_reached();
9545 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9546 bool is_scalar
, bool is_u
, bool is_q
,
9547 int size
, int rn
, int rd
)
9549 bool is_double
= (size
== MO_64
);
9552 if (!fp_access_check(s
)) {
9556 fpst
= get_fpstatus_ptr(size
== MO_16
);
9559 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9560 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9561 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9562 NeonGenTwoDoubleOPFn
*genfn
;
9567 case 0x2e: /* FCMLT (zero) */
9570 case 0x2c: /* FCMGT (zero) */
9571 genfn
= gen_helper_neon_cgt_f64
;
9573 case 0x2d: /* FCMEQ (zero) */
9574 genfn
= gen_helper_neon_ceq_f64
;
9576 case 0x6d: /* FCMLE (zero) */
9579 case 0x6c: /* FCMGE (zero) */
9580 genfn
= gen_helper_neon_cge_f64
;
9583 g_assert_not_reached();
9586 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9587 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9589 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9591 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9593 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9595 tcg_temp_free_i64(tcg_res
);
9596 tcg_temp_free_i64(tcg_zero
);
9597 tcg_temp_free_i64(tcg_op
);
9599 clear_vec_high(s
, !is_scalar
, rd
);
9601 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9602 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9603 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9604 NeonGenTwoSingleOPFn
*genfn
;
9606 int pass
, maxpasses
;
9608 if (size
== MO_16
) {
9610 case 0x2e: /* FCMLT (zero) */
9613 case 0x2c: /* FCMGT (zero) */
9614 genfn
= gen_helper_advsimd_cgt_f16
;
9616 case 0x2d: /* FCMEQ (zero) */
9617 genfn
= gen_helper_advsimd_ceq_f16
;
9619 case 0x6d: /* FCMLE (zero) */
9622 case 0x6c: /* FCMGE (zero) */
9623 genfn
= gen_helper_advsimd_cge_f16
;
9626 g_assert_not_reached();
9630 case 0x2e: /* FCMLT (zero) */
9633 case 0x2c: /* FCMGT (zero) */
9634 genfn
= gen_helper_neon_cgt_f32
;
9636 case 0x2d: /* FCMEQ (zero) */
9637 genfn
= gen_helper_neon_ceq_f32
;
9639 case 0x6d: /* FCMLE (zero) */
9642 case 0x6c: /* FCMGE (zero) */
9643 genfn
= gen_helper_neon_cge_f32
;
9646 g_assert_not_reached();
9653 int vector_size
= 8 << is_q
;
9654 maxpasses
= vector_size
>> size
;
9657 for (pass
= 0; pass
< maxpasses
; pass
++) {
9658 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9660 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9662 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9665 write_fp_sreg(s
, rd
, tcg_res
);
9667 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9670 tcg_temp_free_i32(tcg_res
);
9671 tcg_temp_free_i32(tcg_zero
);
9672 tcg_temp_free_i32(tcg_op
);
9674 clear_vec_high(s
, is_q
, rd
);
9678 tcg_temp_free_ptr(fpst
);
9681 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9682 bool is_scalar
, bool is_u
, bool is_q
,
9683 int size
, int rn
, int rd
)
9685 bool is_double
= (size
== 3);
9686 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9689 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9690 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9693 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9694 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9696 case 0x3d: /* FRECPE */
9697 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9699 case 0x3f: /* FRECPX */
9700 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9702 case 0x7d: /* FRSQRTE */
9703 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9706 g_assert_not_reached();
9708 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9710 tcg_temp_free_i64(tcg_res
);
9711 tcg_temp_free_i64(tcg_op
);
9712 clear_vec_high(s
, !is_scalar
, rd
);
9714 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9715 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9716 int pass
, maxpasses
;
9721 maxpasses
= is_q
? 4 : 2;
9724 for (pass
= 0; pass
< maxpasses
; pass
++) {
9725 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9728 case 0x3c: /* URECPE */
9729 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
9731 case 0x3d: /* FRECPE */
9732 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9734 case 0x3f: /* FRECPX */
9735 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9737 case 0x7d: /* FRSQRTE */
9738 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9741 g_assert_not_reached();
9745 write_fp_sreg(s
, rd
, tcg_res
);
9747 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9750 tcg_temp_free_i32(tcg_res
);
9751 tcg_temp_free_i32(tcg_op
);
9753 clear_vec_high(s
, is_q
, rd
);
9756 tcg_temp_free_ptr(fpst
);
9759 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9760 int opcode
, bool u
, bool is_q
,
9761 int size
, int rn
, int rd
)
9763 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9764 * in the source becomes a size element in the destination).
9767 TCGv_i32 tcg_res
[2];
9768 int destelt
= is_q
? 2 : 0;
9769 int passes
= scalar
? 1 : 2;
9772 tcg_res
[1] = tcg_const_i32(0);
9775 for (pass
= 0; pass
< passes
; pass
++) {
9776 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9777 NeonGenNarrowFn
*genfn
= NULL
;
9778 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9781 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9783 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9785 tcg_res
[pass
] = tcg_temp_new_i32();
9788 case 0x12: /* XTN, SQXTUN */
9790 static NeonGenNarrowFn
* const xtnfns
[3] = {
9791 gen_helper_neon_narrow_u8
,
9792 gen_helper_neon_narrow_u16
,
9793 tcg_gen_extrl_i64_i32
,
9795 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9796 gen_helper_neon_unarrow_sat8
,
9797 gen_helper_neon_unarrow_sat16
,
9798 gen_helper_neon_unarrow_sat32
,
9801 genenvfn
= sqxtunfns
[size
];
9803 genfn
= xtnfns
[size
];
9807 case 0x14: /* SQXTN, UQXTN */
9809 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9810 { gen_helper_neon_narrow_sat_s8
,
9811 gen_helper_neon_narrow_sat_u8
},
9812 { gen_helper_neon_narrow_sat_s16
,
9813 gen_helper_neon_narrow_sat_u16
},
9814 { gen_helper_neon_narrow_sat_s32
,
9815 gen_helper_neon_narrow_sat_u32
},
9817 genenvfn
= fns
[size
][u
];
9820 case 0x16: /* FCVTN, FCVTN2 */
9821 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9823 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9825 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9826 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9827 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9828 TCGv_i32 ahp
= get_ahp_flag();
9830 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9831 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9832 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9833 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9834 tcg_temp_free_i32(tcg_lo
);
9835 tcg_temp_free_i32(tcg_hi
);
9836 tcg_temp_free_ptr(fpst
);
9837 tcg_temp_free_i32(ahp
);
9840 case 0x56: /* FCVTXN, FCVTXN2 */
9841 /* 64 bit to 32 bit float conversion
9842 * with von Neumann rounding (round to odd)
9845 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9848 g_assert_not_reached();
9852 genfn(tcg_res
[pass
], tcg_op
);
9853 } else if (genenvfn
) {
9854 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9857 tcg_temp_free_i64(tcg_op
);
9860 for (pass
= 0; pass
< 2; pass
++) {
9861 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9862 tcg_temp_free_i32(tcg_res
[pass
]);
9864 clear_vec_high(s
, is_q
, rd
);
9867 /* Remaining saturating accumulating ops */
9868 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9869 bool is_q
, int size
, int rn
, int rd
)
9871 bool is_double
= (size
== 3);
9874 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9875 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9878 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9879 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9880 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9882 if (is_u
) { /* USQADD */
9883 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9884 } else { /* SUQADD */
9885 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9887 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9889 tcg_temp_free_i64(tcg_rd
);
9890 tcg_temp_free_i64(tcg_rn
);
9891 clear_vec_high(s
, !is_scalar
, rd
);
9893 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9894 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9895 int pass
, maxpasses
;
9900 maxpasses
= is_q
? 4 : 2;
9903 for (pass
= 0; pass
< maxpasses
; pass
++) {
9905 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9906 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9908 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9909 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9912 if (is_u
) { /* USQADD */
9915 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9918 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9921 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9924 g_assert_not_reached();
9926 } else { /* SUQADD */
9929 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9932 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9935 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9938 g_assert_not_reached();
9943 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9944 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9945 tcg_temp_free_i64(tcg_zero
);
9947 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9949 tcg_temp_free_i32(tcg_rd
);
9950 tcg_temp_free_i32(tcg_rn
);
9951 clear_vec_high(s
, is_q
, rd
);
9955 /* AdvSIMD scalar two reg misc
9956 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9957 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9958 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9959 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9961 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9963 int rd
= extract32(insn
, 0, 5);
9964 int rn
= extract32(insn
, 5, 5);
9965 int opcode
= extract32(insn
, 12, 5);
9966 int size
= extract32(insn
, 22, 2);
9967 bool u
= extract32(insn
, 29, 1);
9968 bool is_fcvt
= false;
9971 TCGv_ptr tcg_fpstatus
;
9974 case 0x3: /* USQADD / SUQADD*/
9975 if (!fp_access_check(s
)) {
9978 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9980 case 0x7: /* SQABS / SQNEG */
9982 case 0xa: /* CMLT */
9984 unallocated_encoding(s
);
9988 case 0x8: /* CMGT, CMGE */
9989 case 0x9: /* CMEQ, CMLE */
9990 case 0xb: /* ABS, NEG */
9992 unallocated_encoding(s
);
9996 case 0x12: /* SQXTUN */
9998 unallocated_encoding(s
);
10002 case 0x14: /* SQXTN, UQXTN */
10004 unallocated_encoding(s
);
10007 if (!fp_access_check(s
)) {
10010 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10013 case 0x16 ... 0x1d:
10015 /* Floating point: U, size[1] and opcode indicate operation;
10016 * size[0] indicates single or double precision.
10018 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10019 size
= extract32(size
, 0, 1) ? 3 : 2;
10021 case 0x2c: /* FCMGT (zero) */
10022 case 0x2d: /* FCMEQ (zero) */
10023 case 0x2e: /* FCMLT (zero) */
10024 case 0x6c: /* FCMGE (zero) */
10025 case 0x6d: /* FCMLE (zero) */
10026 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10028 case 0x1d: /* SCVTF */
10029 case 0x5d: /* UCVTF */
10031 bool is_signed
= (opcode
== 0x1d);
10032 if (!fp_access_check(s
)) {
10035 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10038 case 0x3d: /* FRECPE */
10039 case 0x3f: /* FRECPX */
10040 case 0x7d: /* FRSQRTE */
10041 if (!fp_access_check(s
)) {
10044 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10046 case 0x1a: /* FCVTNS */
10047 case 0x1b: /* FCVTMS */
10048 case 0x3a: /* FCVTPS */
10049 case 0x3b: /* FCVTZS */
10050 case 0x5a: /* FCVTNU */
10051 case 0x5b: /* FCVTMU */
10052 case 0x7a: /* FCVTPU */
10053 case 0x7b: /* FCVTZU */
10055 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10057 case 0x1c: /* FCVTAS */
10058 case 0x5c: /* FCVTAU */
10059 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10061 rmode
= FPROUNDING_TIEAWAY
;
10063 case 0x56: /* FCVTXN, FCVTXN2 */
10065 unallocated_encoding(s
);
10068 if (!fp_access_check(s
)) {
10071 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10074 unallocated_encoding(s
);
10079 unallocated_encoding(s
);
10083 if (!fp_access_check(s
)) {
10088 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10089 tcg_fpstatus
= get_fpstatus_ptr(false);
10090 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10093 tcg_fpstatus
= NULL
;
10097 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10098 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10100 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10101 write_fp_dreg(s
, rd
, tcg_rd
);
10102 tcg_temp_free_i64(tcg_rd
);
10103 tcg_temp_free_i64(tcg_rn
);
10105 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10106 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10108 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10111 case 0x7: /* SQABS, SQNEG */
10113 NeonGenOneOpEnvFn
*genfn
;
10114 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10115 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10116 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10117 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10119 genfn
= fns
[size
][u
];
10120 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10123 case 0x1a: /* FCVTNS */
10124 case 0x1b: /* FCVTMS */
10125 case 0x1c: /* FCVTAS */
10126 case 0x3a: /* FCVTPS */
10127 case 0x3b: /* FCVTZS */
10129 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10130 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10131 tcg_temp_free_i32(tcg_shift
);
10134 case 0x5a: /* FCVTNU */
10135 case 0x5b: /* FCVTMU */
10136 case 0x5c: /* FCVTAU */
10137 case 0x7a: /* FCVTPU */
10138 case 0x7b: /* FCVTZU */
10140 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10141 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10142 tcg_temp_free_i32(tcg_shift
);
10146 g_assert_not_reached();
10149 write_fp_sreg(s
, rd
, tcg_rd
);
10150 tcg_temp_free_i32(tcg_rd
);
10151 tcg_temp_free_i32(tcg_rn
);
10155 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10156 tcg_temp_free_i32(tcg_rmode
);
10157 tcg_temp_free_ptr(tcg_fpstatus
);
10161 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10162 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10163 int immh
, int immb
, int opcode
, int rn
, int rd
)
10165 int size
= 32 - clz32(immh
) - 1;
10166 int immhb
= immh
<< 3 | immb
;
10167 int shift
= 2 * (8 << size
) - immhb
;
10168 bool accumulate
= false;
10169 int dsize
= is_q
? 128 : 64;
10170 int esize
= 8 << size
;
10171 int elements
= dsize
/esize
;
10172 MemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
10173 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10174 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10175 TCGv_i64 tcg_round
;
10176 uint64_t round_const
;
10179 if (extract32(immh
, 3, 1) && !is_q
) {
10180 unallocated_encoding(s
);
10183 tcg_debug_assert(size
<= 3);
10185 if (!fp_access_check(s
)) {
10190 case 0x02: /* SSRA / USRA (accumulate) */
10191 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
,
10192 is_u
? gen_gvec_usra
: gen_gvec_ssra
, size
);
10194 case 0x08: /* SRI */
10195 /* Shift count same as element size is valid but does nothing. */
10196 if (shift
== 8 << size
) {
10199 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
10202 case 0x00: /* SSHR / USHR */
10204 if (shift
== 8 << size
) {
10205 /* Shift count the same size as element size produces zero. */
10206 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10207 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10209 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
10212 /* Shift count the same size as element size produces all sign. */
10213 if (shift
== 8 << size
) {
10216 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
10220 case 0x04: /* SRSHR / URSHR (rounding) */
10221 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
,
10222 is_u
? gen_gvec_urshr
: gen_gvec_srshr
, size
);
10225 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10226 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
,
10227 is_u
? gen_gvec_ursra
: gen_gvec_srsra
, size
);
10231 g_assert_not_reached();
10234 round_const
= 1ULL << (shift
- 1);
10235 tcg_round
= tcg_const_i64(round_const
);
10237 for (i
= 0; i
< elements
; i
++) {
10238 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
10240 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
10243 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10244 accumulate
, is_u
, size
, shift
);
10246 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
10248 tcg_temp_free_i64(tcg_round
);
10251 clear_vec_high(s
, is_q
, rd
);
10254 /* SHL/SLI - Vector shift left */
10255 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10256 int immh
, int immb
, int opcode
, int rn
, int rd
)
10258 int size
= 32 - clz32(immh
) - 1;
10259 int immhb
= immh
<< 3 | immb
;
10260 int shift
= immhb
- (8 << size
);
10262 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10263 assert(size
>= 0 && size
<= 3);
10265 if (extract32(immh
, 3, 1) && !is_q
) {
10266 unallocated_encoding(s
);
10270 if (!fp_access_check(s
)) {
10275 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sli_op
[size
]);
10277 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10281 /* USHLL/SHLL - Vector shift left with widening */
10282 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10283 int immh
, int immb
, int opcode
, int rn
, int rd
)
10285 int size
= 32 - clz32(immh
) - 1;
10286 int immhb
= immh
<< 3 | immb
;
10287 int shift
= immhb
- (8 << size
);
10289 int esize
= 8 << size
;
10290 int elements
= dsize
/esize
;
10291 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10292 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10296 unallocated_encoding(s
);
10300 if (!fp_access_check(s
)) {
10304 /* For the LL variants the store is larger than the load,
10305 * so if rd == rn we would overwrite parts of our input.
10306 * So load everything right now and use shifts in the main loop.
10308 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10310 for (i
= 0; i
< elements
; i
++) {
10311 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10312 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10313 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10314 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10318 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10319 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10320 int immh
, int immb
, int opcode
, int rn
, int rd
)
10322 int immhb
= immh
<< 3 | immb
;
10323 int size
= 32 - clz32(immh
) - 1;
10325 int esize
= 8 << size
;
10326 int elements
= dsize
/esize
;
10327 int shift
= (2 * esize
) - immhb
;
10328 bool round
= extract32(opcode
, 0, 1);
10329 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10330 TCGv_i64 tcg_round
;
10333 if (extract32(immh
, 3, 1)) {
10334 unallocated_encoding(s
);
10338 if (!fp_access_check(s
)) {
10342 tcg_rn
= tcg_temp_new_i64();
10343 tcg_rd
= tcg_temp_new_i64();
10344 tcg_final
= tcg_temp_new_i64();
10345 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10348 uint64_t round_const
= 1ULL << (shift
- 1);
10349 tcg_round
= tcg_const_i64(round_const
);
10354 for (i
= 0; i
< elements
; i
++) {
10355 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10356 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10357 false, true, size
+1, shift
);
10359 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10363 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10365 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10368 tcg_temp_free_i64(tcg_round
);
10370 tcg_temp_free_i64(tcg_rn
);
10371 tcg_temp_free_i64(tcg_rd
);
10372 tcg_temp_free_i64(tcg_final
);
10374 clear_vec_high(s
, is_q
, rd
);
10378 /* AdvSIMD shift by immediate
10379 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10380 * +---+---+---+-------------+------+------+--------+---+------+------+
10381 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10382 * +---+---+---+-------------+------+------+--------+---+------+------+
10384 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10386 int rd
= extract32(insn
, 0, 5);
10387 int rn
= extract32(insn
, 5, 5);
10388 int opcode
= extract32(insn
, 11, 5);
10389 int immb
= extract32(insn
, 16, 3);
10390 int immh
= extract32(insn
, 19, 4);
10391 bool is_u
= extract32(insn
, 29, 1);
10392 bool is_q
= extract32(insn
, 30, 1);
10394 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10398 case 0x08: /* SRI */
10400 unallocated_encoding(s
);
10404 case 0x00: /* SSHR / USHR */
10405 case 0x02: /* SSRA / USRA (accumulate) */
10406 case 0x04: /* SRSHR / URSHR (rounding) */
10407 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10408 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10410 case 0x0a: /* SHL / SLI */
10411 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10413 case 0x10: /* SHRN */
10414 case 0x11: /* RSHRN / SQRSHRUN */
10416 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10419 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10422 case 0x12: /* SQSHRN / UQSHRN */
10423 case 0x13: /* SQRSHRN / UQRSHRN */
10424 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10427 case 0x14: /* SSHLL / USHLL */
10428 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10430 case 0x1c: /* SCVTF / UCVTF */
10431 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10434 case 0xc: /* SQSHLU */
10436 unallocated_encoding(s
);
10439 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10441 case 0xe: /* SQSHL, UQSHL */
10442 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10444 case 0x1f: /* FCVTZS/ FCVTZU */
10445 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10448 unallocated_encoding(s
);
10453 /* Generate code to do a "long" addition or subtraction, ie one done in
10454 * TCGv_i64 on vector lanes twice the width specified by size.
10456 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10457 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10459 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10460 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10461 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10462 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10464 NeonGenTwo64OpFn
*genfn
;
10467 genfn
= fns
[size
][is_sub
];
10468 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10471 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10472 int opcode
, int rd
, int rn
, int rm
)
10474 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10475 TCGv_i64 tcg_res
[2];
10478 tcg_res
[0] = tcg_temp_new_i64();
10479 tcg_res
[1] = tcg_temp_new_i64();
10481 /* Does this op do an adding accumulate, a subtracting accumulate,
10482 * or no accumulate at all?
10500 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10501 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10504 /* size == 2 means two 32x32->64 operations; this is worth special
10505 * casing because we can generally handle it inline.
10508 for (pass
= 0; pass
< 2; pass
++) {
10509 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10510 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10511 TCGv_i64 tcg_passres
;
10512 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10514 int elt
= pass
+ is_q
* 2;
10516 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10517 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10520 tcg_passres
= tcg_res
[pass
];
10522 tcg_passres
= tcg_temp_new_i64();
10526 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10527 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10529 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10530 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10532 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10533 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10535 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10536 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10538 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10539 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10540 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10542 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10543 tcg_temp_free_i64(tcg_tmp1
);
10544 tcg_temp_free_i64(tcg_tmp2
);
10547 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10548 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10549 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10550 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10552 case 9: /* SQDMLAL, SQDMLAL2 */
10553 case 11: /* SQDMLSL, SQDMLSL2 */
10554 case 13: /* SQDMULL, SQDMULL2 */
10555 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10556 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10557 tcg_passres
, tcg_passres
);
10560 g_assert_not_reached();
10563 if (opcode
== 9 || opcode
== 11) {
10564 /* saturating accumulate ops */
10566 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10568 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10569 tcg_res
[pass
], tcg_passres
);
10570 } else if (accop
> 0) {
10571 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10572 } else if (accop
< 0) {
10573 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10577 tcg_temp_free_i64(tcg_passres
);
10580 tcg_temp_free_i64(tcg_op1
);
10581 tcg_temp_free_i64(tcg_op2
);
10584 /* size 0 or 1, generally helper functions */
10585 for (pass
= 0; pass
< 2; pass
++) {
10586 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10587 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10588 TCGv_i64 tcg_passres
;
10589 int elt
= pass
+ is_q
* 2;
10591 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10592 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10595 tcg_passres
= tcg_res
[pass
];
10597 tcg_passres
= tcg_temp_new_i64();
10601 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10602 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10604 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10605 static NeonGenWidenFn
* const widenfns
[2][2] = {
10606 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10607 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10609 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10611 widenfn(tcg_op2_64
, tcg_op2
);
10612 widenfn(tcg_passres
, tcg_op1
);
10613 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10614 tcg_passres
, tcg_op2_64
);
10615 tcg_temp_free_i64(tcg_op2_64
);
10618 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10619 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10622 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10624 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10628 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10630 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10634 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10635 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10636 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10639 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10641 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10645 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10647 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10651 case 9: /* SQDMLAL, SQDMLAL2 */
10652 case 11: /* SQDMLSL, SQDMLSL2 */
10653 case 13: /* SQDMULL, SQDMULL2 */
10655 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10656 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10657 tcg_passres
, tcg_passres
);
10660 g_assert_not_reached();
10662 tcg_temp_free_i32(tcg_op1
);
10663 tcg_temp_free_i32(tcg_op2
);
10666 if (opcode
== 9 || opcode
== 11) {
10667 /* saturating accumulate ops */
10669 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10671 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10675 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10676 tcg_res
[pass
], tcg_passres
);
10678 tcg_temp_free_i64(tcg_passres
);
10683 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10684 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10685 tcg_temp_free_i64(tcg_res
[0]);
10686 tcg_temp_free_i64(tcg_res
[1]);
10689 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10690 int opcode
, int rd
, int rn
, int rm
)
10692 TCGv_i64 tcg_res
[2];
10693 int part
= is_q
? 2 : 0;
10696 for (pass
= 0; pass
< 2; pass
++) {
10697 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10698 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10699 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10700 static NeonGenWidenFn
* const widenfns
[3][2] = {
10701 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10702 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10703 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10705 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10707 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10708 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10709 widenfn(tcg_op2_wide
, tcg_op2
);
10710 tcg_temp_free_i32(tcg_op2
);
10711 tcg_res
[pass
] = tcg_temp_new_i64();
10712 gen_neon_addl(size
, (opcode
== 3),
10713 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10714 tcg_temp_free_i64(tcg_op1
);
10715 tcg_temp_free_i64(tcg_op2_wide
);
10718 for (pass
= 0; pass
< 2; pass
++) {
10719 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10720 tcg_temp_free_i64(tcg_res
[pass
]);
10724 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10726 tcg_gen_addi_i64(in
, in
, 1U << 31);
10727 tcg_gen_extrh_i64_i32(res
, in
);
10730 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10731 int opcode
, int rd
, int rn
, int rm
)
10733 TCGv_i32 tcg_res
[2];
10734 int part
= is_q
? 2 : 0;
10737 for (pass
= 0; pass
< 2; pass
++) {
10738 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10739 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10740 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10741 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10742 { gen_helper_neon_narrow_high_u8
,
10743 gen_helper_neon_narrow_round_high_u8
},
10744 { gen_helper_neon_narrow_high_u16
,
10745 gen_helper_neon_narrow_round_high_u16
},
10746 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10748 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10750 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10751 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10753 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10755 tcg_temp_free_i64(tcg_op1
);
10756 tcg_temp_free_i64(tcg_op2
);
10758 tcg_res
[pass
] = tcg_temp_new_i32();
10759 gennarrow(tcg_res
[pass
], tcg_wideres
);
10760 tcg_temp_free_i64(tcg_wideres
);
10763 for (pass
= 0; pass
< 2; pass
++) {
10764 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10765 tcg_temp_free_i32(tcg_res
[pass
]);
10767 clear_vec_high(s
, is_q
, rd
);
10770 /* AdvSIMD three different
10771 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10772 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10773 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10774 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10776 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10778 /* Instructions in this group fall into three basic classes
10779 * (in each case with the operation working on each element in
10780 * the input vectors):
10781 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10783 * (2) wide 64 x 128 -> 128
10784 * (3) narrowing 128 x 128 -> 64
10785 * Here we do initial decode, catch unallocated cases and
10786 * dispatch to separate functions for each class.
10788 int is_q
= extract32(insn
, 30, 1);
10789 int is_u
= extract32(insn
, 29, 1);
10790 int size
= extract32(insn
, 22, 2);
10791 int opcode
= extract32(insn
, 12, 4);
10792 int rm
= extract32(insn
, 16, 5);
10793 int rn
= extract32(insn
, 5, 5);
10794 int rd
= extract32(insn
, 0, 5);
10797 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10798 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10799 /* 64 x 128 -> 128 */
10801 unallocated_encoding(s
);
10804 if (!fp_access_check(s
)) {
10807 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10809 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10810 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10811 /* 128 x 128 -> 64 */
10813 unallocated_encoding(s
);
10816 if (!fp_access_check(s
)) {
10819 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10821 case 14: /* PMULL, PMULL2 */
10823 unallocated_encoding(s
);
10827 case 0: /* PMULL.P8 */
10828 if (!fp_access_check(s
)) {
10831 /* The Q field specifies lo/hi half input for this insn. */
10832 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10833 gen_helper_neon_pmull_h
);
10836 case 3: /* PMULL.P64 */
10837 if (!dc_isar_feature(aa64_pmull
, s
)) {
10838 unallocated_encoding(s
);
10841 if (!fp_access_check(s
)) {
10844 /* The Q field specifies lo/hi half input for this insn. */
10845 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10846 gen_helper_gvec_pmull_q
);
10850 unallocated_encoding(s
);
10854 case 9: /* SQDMLAL, SQDMLAL2 */
10855 case 11: /* SQDMLSL, SQDMLSL2 */
10856 case 13: /* SQDMULL, SQDMULL2 */
10857 if (is_u
|| size
== 0) {
10858 unallocated_encoding(s
);
10862 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10863 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10864 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10865 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10866 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10867 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10868 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10869 /* 64 x 64 -> 128 */
10871 unallocated_encoding(s
);
10874 if (!fp_access_check(s
)) {
10878 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10881 /* opcode 15 not allocated */
10882 unallocated_encoding(s
);
10887 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10888 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10890 int rd
= extract32(insn
, 0, 5);
10891 int rn
= extract32(insn
, 5, 5);
10892 int rm
= extract32(insn
, 16, 5);
10893 int size
= extract32(insn
, 22, 2);
10894 bool is_u
= extract32(insn
, 29, 1);
10895 bool is_q
= extract32(insn
, 30, 1);
10897 if (!fp_access_check(s
)) {
10901 switch (size
+ 4 * is_u
) {
10903 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10906 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10909 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10912 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10915 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10918 case 5: /* BSL bitwise select */
10919 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
10921 case 6: /* BIT, bitwise insert if true */
10922 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
10924 case 7: /* BIF, bitwise insert if false */
10925 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
10929 g_assert_not_reached();
10933 /* Pairwise op subgroup of C3.6.16.
10935 * This is called directly or via the handle_3same_float for float pairwise
10936 * operations where the opcode and size are calculated differently.
10938 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10939 int size
, int rn
, int rm
, int rd
)
10944 /* Floating point operations need fpst */
10945 if (opcode
>= 0x58) {
10946 fpst
= get_fpstatus_ptr(false);
10951 if (!fp_access_check(s
)) {
10955 /* These operations work on the concatenated rm:rn, with each pair of
10956 * adjacent elements being operated on to produce an element in the result.
10959 TCGv_i64 tcg_res
[2];
10961 for (pass
= 0; pass
< 2; pass
++) {
10962 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10963 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10964 int passreg
= (pass
== 0) ? rn
: rm
;
10966 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10967 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10968 tcg_res
[pass
] = tcg_temp_new_i64();
10971 case 0x17: /* ADDP */
10972 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10974 case 0x58: /* FMAXNMP */
10975 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10977 case 0x5a: /* FADDP */
10978 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10980 case 0x5e: /* FMAXP */
10981 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10983 case 0x78: /* FMINNMP */
10984 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10986 case 0x7e: /* FMINP */
10987 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10990 g_assert_not_reached();
10993 tcg_temp_free_i64(tcg_op1
);
10994 tcg_temp_free_i64(tcg_op2
);
10997 for (pass
= 0; pass
< 2; pass
++) {
10998 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10999 tcg_temp_free_i64(tcg_res
[pass
]);
11002 int maxpass
= is_q
? 4 : 2;
11003 TCGv_i32 tcg_res
[4];
11005 for (pass
= 0; pass
< maxpass
; pass
++) {
11006 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11007 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11008 NeonGenTwoOpFn
*genfn
= NULL
;
11009 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11010 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11012 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11013 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11014 tcg_res
[pass
] = tcg_temp_new_i32();
11017 case 0x17: /* ADDP */
11019 static NeonGenTwoOpFn
* const fns
[3] = {
11020 gen_helper_neon_padd_u8
,
11021 gen_helper_neon_padd_u16
,
11027 case 0x14: /* SMAXP, UMAXP */
11029 static NeonGenTwoOpFn
* const fns
[3][2] = {
11030 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11031 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11032 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11034 genfn
= fns
[size
][u
];
11037 case 0x15: /* SMINP, UMINP */
11039 static NeonGenTwoOpFn
* const fns
[3][2] = {
11040 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11041 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11042 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11044 genfn
= fns
[size
][u
];
11047 /* The FP operations are all on single floats (32 bit) */
11048 case 0x58: /* FMAXNMP */
11049 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11051 case 0x5a: /* FADDP */
11052 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11054 case 0x5e: /* FMAXP */
11055 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11057 case 0x78: /* FMINNMP */
11058 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11060 case 0x7e: /* FMINP */
11061 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11064 g_assert_not_reached();
11067 /* FP ops called directly, otherwise call now */
11069 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11072 tcg_temp_free_i32(tcg_op1
);
11073 tcg_temp_free_i32(tcg_op2
);
11076 for (pass
= 0; pass
< maxpass
; pass
++) {
11077 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11078 tcg_temp_free_i32(tcg_res
[pass
]);
11080 clear_vec_high(s
, is_q
, rd
);
11084 tcg_temp_free_ptr(fpst
);
11088 /* Floating point op subgroup of C3.6.16. */
11089 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11091 /* For floating point ops, the U, size[1] and opcode bits
11092 * together indicate the operation. size[0] indicates single
11095 int fpopcode
= extract32(insn
, 11, 5)
11096 | (extract32(insn
, 23, 1) << 5)
11097 | (extract32(insn
, 29, 1) << 6);
11098 int is_q
= extract32(insn
, 30, 1);
11099 int size
= extract32(insn
, 22, 1);
11100 int rm
= extract32(insn
, 16, 5);
11101 int rn
= extract32(insn
, 5, 5);
11102 int rd
= extract32(insn
, 0, 5);
11104 int datasize
= is_q
? 128 : 64;
11105 int esize
= 32 << size
;
11106 int elements
= datasize
/ esize
;
11108 if (size
== 1 && !is_q
) {
11109 unallocated_encoding(s
);
11113 switch (fpopcode
) {
11114 case 0x58: /* FMAXNMP */
11115 case 0x5a: /* FADDP */
11116 case 0x5e: /* FMAXP */
11117 case 0x78: /* FMINNMP */
11118 case 0x7e: /* FMINP */
11119 if (size
&& !is_q
) {
11120 unallocated_encoding(s
);
11123 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11126 case 0x1b: /* FMULX */
11127 case 0x1f: /* FRECPS */
11128 case 0x3f: /* FRSQRTS */
11129 case 0x5d: /* FACGE */
11130 case 0x7d: /* FACGT */
11131 case 0x19: /* FMLA */
11132 case 0x39: /* FMLS */
11133 case 0x18: /* FMAXNM */
11134 case 0x1a: /* FADD */
11135 case 0x1c: /* FCMEQ */
11136 case 0x1e: /* FMAX */
11137 case 0x38: /* FMINNM */
11138 case 0x3a: /* FSUB */
11139 case 0x3e: /* FMIN */
11140 case 0x5b: /* FMUL */
11141 case 0x5c: /* FCMGE */
11142 case 0x5f: /* FDIV */
11143 case 0x7a: /* FABD */
11144 case 0x7c: /* FCMGT */
11145 if (!fp_access_check(s
)) {
11148 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11151 case 0x1d: /* FMLAL */
11152 case 0x3d: /* FMLSL */
11153 case 0x59: /* FMLAL2 */
11154 case 0x79: /* FMLSL2 */
11155 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11156 unallocated_encoding(s
);
11159 if (fp_access_check(s
)) {
11160 int is_s
= extract32(insn
, 23, 1);
11161 int is_2
= extract32(insn
, 29, 1);
11162 int data
= (is_2
<< 1) | is_s
;
11163 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11164 vec_full_reg_offset(s
, rn
),
11165 vec_full_reg_offset(s
, rm
), cpu_env
,
11166 is_q
? 16 : 8, vec_full_reg_size(s
),
11167 data
, gen_helper_gvec_fmlal_a64
);
11172 unallocated_encoding(s
);
11177 /* Integer op subgroup of C3.6.16. */
11178 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11180 int is_q
= extract32(insn
, 30, 1);
11181 int u
= extract32(insn
, 29, 1);
11182 int size
= extract32(insn
, 22, 2);
11183 int opcode
= extract32(insn
, 11, 5);
11184 int rm
= extract32(insn
, 16, 5);
11185 int rn
= extract32(insn
, 5, 5);
11186 int rd
= extract32(insn
, 0, 5);
11191 case 0x13: /* MUL, PMUL */
11192 if (u
&& size
!= 0) {
11193 unallocated_encoding(s
);
11197 case 0x0: /* SHADD, UHADD */
11198 case 0x2: /* SRHADD, URHADD */
11199 case 0x4: /* SHSUB, UHSUB */
11200 case 0xc: /* SMAX, UMAX */
11201 case 0xd: /* SMIN, UMIN */
11202 case 0xe: /* SABD, UABD */
11203 case 0xf: /* SABA, UABA */
11204 case 0x12: /* MLA, MLS */
11206 unallocated_encoding(s
);
11210 case 0x16: /* SQDMULH, SQRDMULH */
11211 if (size
== 0 || size
== 3) {
11212 unallocated_encoding(s
);
11217 if (size
== 3 && !is_q
) {
11218 unallocated_encoding(s
);
11224 if (!fp_access_check(s
)) {
11229 case 0x01: /* SQADD, UQADD */
11230 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11231 offsetof(CPUARMState
, vfp
.qc
),
11232 vec_full_reg_offset(s
, rn
),
11233 vec_full_reg_offset(s
, rm
),
11234 is_q
? 16 : 8, vec_full_reg_size(s
),
11235 (u
? uqadd_op
: sqadd_op
) + size
);
11237 case 0x05: /* SQSUB, UQSUB */
11238 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11239 offsetof(CPUARMState
, vfp
.qc
),
11240 vec_full_reg_offset(s
, rn
),
11241 vec_full_reg_offset(s
, rm
),
11242 is_q
? 16 : 8, vec_full_reg_size(s
),
11243 (u
? uqsub_op
: sqsub_op
) + size
);
11245 case 0x08: /* SSHL, USHL */
11246 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
,
11247 u
? &ushl_op
[size
] : &sshl_op
[size
]);
11249 case 0x0c: /* SMAX, UMAX */
11251 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11253 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11256 case 0x0d: /* SMIN, UMIN */
11258 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11260 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11263 case 0x10: /* ADD, SUB */
11265 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11267 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11270 case 0x13: /* MUL, PMUL */
11271 if (!u
) { /* MUL */
11272 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11273 } else { /* PMUL */
11274 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11277 case 0x12: /* MLA, MLS */
11279 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
11281 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
11285 if (!u
) { /* CMTST */
11286 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
11290 cond
= TCG_COND_EQ
;
11292 case 0x06: /* CMGT, CMHI */
11293 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11295 case 0x07: /* CMGE, CMHS */
11296 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11298 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11299 vec_full_reg_offset(s
, rn
),
11300 vec_full_reg_offset(s
, rm
),
11301 is_q
? 16 : 8, vec_full_reg_size(s
));
11307 for (pass
= 0; pass
< 2; pass
++) {
11308 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11309 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11310 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11312 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11313 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11315 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11317 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11319 tcg_temp_free_i64(tcg_res
);
11320 tcg_temp_free_i64(tcg_op1
);
11321 tcg_temp_free_i64(tcg_op2
);
11324 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11325 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11326 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11327 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11328 NeonGenTwoOpFn
*genfn
= NULL
;
11329 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11331 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11332 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11335 case 0x0: /* SHADD, UHADD */
11337 static NeonGenTwoOpFn
* const fns
[3][2] = {
11338 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11339 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11340 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11342 genfn
= fns
[size
][u
];
11345 case 0x2: /* SRHADD, URHADD */
11347 static NeonGenTwoOpFn
* const fns
[3][2] = {
11348 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11349 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11350 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11352 genfn
= fns
[size
][u
];
11355 case 0x4: /* SHSUB, UHSUB */
11357 static NeonGenTwoOpFn
* const fns
[3][2] = {
11358 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11359 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11360 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11362 genfn
= fns
[size
][u
];
11365 case 0x9: /* SQSHL, UQSHL */
11367 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11368 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11369 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11370 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11372 genenvfn
= fns
[size
][u
];
11375 case 0xa: /* SRSHL, URSHL */
11377 static NeonGenTwoOpFn
* const fns
[3][2] = {
11378 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11379 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11380 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11382 genfn
= fns
[size
][u
];
11385 case 0xb: /* SQRSHL, UQRSHL */
11387 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11388 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11389 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11390 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11392 genenvfn
= fns
[size
][u
];
11395 case 0xe: /* SABD, UABD */
11396 case 0xf: /* SABA, UABA */
11398 static NeonGenTwoOpFn
* const fns
[3][2] = {
11399 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11400 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11401 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11403 genfn
= fns
[size
][u
];
11406 case 0x16: /* SQDMULH, SQRDMULH */
11408 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11409 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11410 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11412 assert(size
== 1 || size
== 2);
11413 genenvfn
= fns
[size
- 1][u
];
11417 g_assert_not_reached();
11421 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11423 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11426 if (opcode
== 0xf) {
11427 /* SABA, UABA: accumulating ops */
11428 static NeonGenTwoOpFn
* const fns
[3] = {
11429 gen_helper_neon_add_u8
,
11430 gen_helper_neon_add_u16
,
11434 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11435 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11438 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11440 tcg_temp_free_i32(tcg_res
);
11441 tcg_temp_free_i32(tcg_op1
);
11442 tcg_temp_free_i32(tcg_op2
);
11445 clear_vec_high(s
, is_q
, rd
);
11448 /* AdvSIMD three same
11449 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11450 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11451 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11452 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11454 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11456 int opcode
= extract32(insn
, 11, 5);
11459 case 0x3: /* logic ops */
11460 disas_simd_3same_logic(s
, insn
);
11462 case 0x17: /* ADDP */
11463 case 0x14: /* SMAXP, UMAXP */
11464 case 0x15: /* SMINP, UMINP */
11466 /* Pairwise operations */
11467 int is_q
= extract32(insn
, 30, 1);
11468 int u
= extract32(insn
, 29, 1);
11469 int size
= extract32(insn
, 22, 2);
11470 int rm
= extract32(insn
, 16, 5);
11471 int rn
= extract32(insn
, 5, 5);
11472 int rd
= extract32(insn
, 0, 5);
11473 if (opcode
== 0x17) {
11474 if (u
|| (size
== 3 && !is_q
)) {
11475 unallocated_encoding(s
);
11480 unallocated_encoding(s
);
11484 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11487 case 0x18 ... 0x31:
11488 /* floating point ops, sz[1] and U are part of opcode */
11489 disas_simd_3same_float(s
, insn
);
11492 disas_simd_3same_int(s
, insn
);
11498 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11500 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11501 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11502 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11503 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11505 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11506 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11509 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11511 int opcode
, fpopcode
;
11512 int is_q
, u
, a
, rm
, rn
, rd
;
11513 int datasize
, elements
;
11516 bool pairwise
= false;
11518 if (!dc_isar_feature(aa64_fp16
, s
)) {
11519 unallocated_encoding(s
);
11523 if (!fp_access_check(s
)) {
11527 /* For these floating point ops, the U, a and opcode bits
11528 * together indicate the operation.
11530 opcode
= extract32(insn
, 11, 3);
11531 u
= extract32(insn
, 29, 1);
11532 a
= extract32(insn
, 23, 1);
11533 is_q
= extract32(insn
, 30, 1);
11534 rm
= extract32(insn
, 16, 5);
11535 rn
= extract32(insn
, 5, 5);
11536 rd
= extract32(insn
, 0, 5);
11538 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11539 datasize
= is_q
? 128 : 64;
11540 elements
= datasize
/ 16;
11542 switch (fpopcode
) {
11543 case 0x10: /* FMAXNMP */
11544 case 0x12: /* FADDP */
11545 case 0x16: /* FMAXP */
11546 case 0x18: /* FMINNMP */
11547 case 0x1e: /* FMINP */
11552 fpst
= get_fpstatus_ptr(true);
11555 int maxpass
= is_q
? 8 : 4;
11556 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11557 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11558 TCGv_i32 tcg_res
[8];
11560 for (pass
= 0; pass
< maxpass
; pass
++) {
11561 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11562 int passelt
= (pass
<< 1) & (maxpass
- 1);
11564 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11565 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11566 tcg_res
[pass
] = tcg_temp_new_i32();
11568 switch (fpopcode
) {
11569 case 0x10: /* FMAXNMP */
11570 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11573 case 0x12: /* FADDP */
11574 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11576 case 0x16: /* FMAXP */
11577 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11579 case 0x18: /* FMINNMP */
11580 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11583 case 0x1e: /* FMINP */
11584 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11587 g_assert_not_reached();
11591 for (pass
= 0; pass
< maxpass
; pass
++) {
11592 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11593 tcg_temp_free_i32(tcg_res
[pass
]);
11596 tcg_temp_free_i32(tcg_op1
);
11597 tcg_temp_free_i32(tcg_op2
);
11600 for (pass
= 0; pass
< elements
; pass
++) {
11601 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11602 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11603 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11605 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11606 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11608 switch (fpopcode
) {
11609 case 0x0: /* FMAXNM */
11610 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11612 case 0x1: /* FMLA */
11613 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11614 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11617 case 0x2: /* FADD */
11618 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11620 case 0x3: /* FMULX */
11621 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11623 case 0x4: /* FCMEQ */
11624 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11626 case 0x6: /* FMAX */
11627 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11629 case 0x7: /* FRECPS */
11630 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11632 case 0x8: /* FMINNM */
11633 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11635 case 0x9: /* FMLS */
11636 /* As usual for ARM, separate negation for fused multiply-add */
11637 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11638 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11639 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11642 case 0xa: /* FSUB */
11643 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11645 case 0xe: /* FMIN */
11646 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11648 case 0xf: /* FRSQRTS */
11649 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11651 case 0x13: /* FMUL */
11652 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11654 case 0x14: /* FCMGE */
11655 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11657 case 0x15: /* FACGE */
11658 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11660 case 0x17: /* FDIV */
11661 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11663 case 0x1a: /* FABD */
11664 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11665 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11667 case 0x1c: /* FCMGT */
11668 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11670 case 0x1d: /* FACGT */
11671 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11674 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11675 __func__
, insn
, fpopcode
, s
->pc_curr
);
11676 g_assert_not_reached();
11679 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11680 tcg_temp_free_i32(tcg_res
);
11681 tcg_temp_free_i32(tcg_op1
);
11682 tcg_temp_free_i32(tcg_op2
);
11686 tcg_temp_free_ptr(fpst
);
11688 clear_vec_high(s
, is_q
, rd
);
11691 /* AdvSIMD three same extra
11692 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11693 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11694 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11695 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11697 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11699 int rd
= extract32(insn
, 0, 5);
11700 int rn
= extract32(insn
, 5, 5);
11701 int opcode
= extract32(insn
, 11, 4);
11702 int rm
= extract32(insn
, 16, 5);
11703 int size
= extract32(insn
, 22, 2);
11704 bool u
= extract32(insn
, 29, 1);
11705 bool is_q
= extract32(insn
, 30, 1);
11709 switch (u
* 16 + opcode
) {
11710 case 0x10: /* SQRDMLAH (vector) */
11711 case 0x11: /* SQRDMLSH (vector) */
11712 if (size
!= 1 && size
!= 2) {
11713 unallocated_encoding(s
);
11716 feature
= dc_isar_feature(aa64_rdm
, s
);
11718 case 0x02: /* SDOT (vector) */
11719 case 0x12: /* UDOT (vector) */
11720 if (size
!= MO_32
) {
11721 unallocated_encoding(s
);
11724 feature
= dc_isar_feature(aa64_dp
, s
);
11726 case 0x18: /* FCMLA, #0 */
11727 case 0x19: /* FCMLA, #90 */
11728 case 0x1a: /* FCMLA, #180 */
11729 case 0x1b: /* FCMLA, #270 */
11730 case 0x1c: /* FCADD, #90 */
11731 case 0x1e: /* FCADD, #270 */
11733 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11734 || (size
== 3 && !is_q
)) {
11735 unallocated_encoding(s
);
11738 feature
= dc_isar_feature(aa64_fcma
, s
);
11741 unallocated_encoding(s
);
11745 unallocated_encoding(s
);
11748 if (!fp_access_check(s
)) {
11753 case 0x0: /* SQRDMLAH (vector) */
11756 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11759 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11762 g_assert_not_reached();
11766 case 0x1: /* SQRDMLSH (vector) */
11769 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11772 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11775 g_assert_not_reached();
11779 case 0x2: /* SDOT / UDOT */
11780 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11781 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11784 case 0x8: /* FCMLA, #0 */
11785 case 0x9: /* FCMLA, #90 */
11786 case 0xa: /* FCMLA, #180 */
11787 case 0xb: /* FCMLA, #270 */
11788 rot
= extract32(opcode
, 0, 2);
11791 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11792 gen_helper_gvec_fcmlah
);
11795 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11796 gen_helper_gvec_fcmlas
);
11799 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11800 gen_helper_gvec_fcmlad
);
11803 g_assert_not_reached();
11807 case 0xc: /* FCADD, #90 */
11808 case 0xe: /* FCADD, #270 */
11809 rot
= extract32(opcode
, 1, 1);
11812 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11813 gen_helper_gvec_fcaddh
);
11816 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11817 gen_helper_gvec_fcadds
);
11820 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11821 gen_helper_gvec_fcaddd
);
11824 g_assert_not_reached();
11829 g_assert_not_reached();
11833 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11834 int size
, int rn
, int rd
)
11836 /* Handle 2-reg-misc ops which are widening (so each size element
11837 * in the source becomes a 2*size element in the destination.
11838 * The only instruction like this is FCVTL.
11843 /* 32 -> 64 bit fp conversion */
11844 TCGv_i64 tcg_res
[2];
11845 int srcelt
= is_q
? 2 : 0;
11847 for (pass
= 0; pass
< 2; pass
++) {
11848 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11849 tcg_res
[pass
] = tcg_temp_new_i64();
11851 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11852 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11853 tcg_temp_free_i32(tcg_op
);
11855 for (pass
= 0; pass
< 2; pass
++) {
11856 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11857 tcg_temp_free_i64(tcg_res
[pass
]);
11860 /* 16 -> 32 bit fp conversion */
11861 int srcelt
= is_q
? 4 : 0;
11862 TCGv_i32 tcg_res
[4];
11863 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11864 TCGv_i32 ahp
= get_ahp_flag();
11866 for (pass
= 0; pass
< 4; pass
++) {
11867 tcg_res
[pass
] = tcg_temp_new_i32();
11869 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11870 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11873 for (pass
= 0; pass
< 4; pass
++) {
11874 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11875 tcg_temp_free_i32(tcg_res
[pass
]);
11878 tcg_temp_free_ptr(fpst
);
11879 tcg_temp_free_i32(ahp
);
11883 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11884 bool is_q
, int size
, int rn
, int rd
)
11886 int op
= (opcode
<< 1) | u
;
11887 int opsz
= op
+ size
;
11888 int grp_size
= 3 - opsz
;
11889 int dsize
= is_q
? 128 : 64;
11893 unallocated_encoding(s
);
11897 if (!fp_access_check(s
)) {
11902 /* Special case bytes, use bswap op on each group of elements */
11903 int groups
= dsize
/ (8 << grp_size
);
11905 for (i
= 0; i
< groups
; i
++) {
11906 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11908 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11909 switch (grp_size
) {
11911 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11914 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11917 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11920 g_assert_not_reached();
11922 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11923 tcg_temp_free_i64(tcg_tmp
);
11925 clear_vec_high(s
, is_q
, rd
);
11927 int revmask
= (1 << grp_size
) - 1;
11928 int esize
= 8 << size
;
11929 int elements
= dsize
/ esize
;
11930 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11931 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11932 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11934 for (i
= 0; i
< elements
; i
++) {
11935 int e_rev
= (i
& 0xf) ^ revmask
;
11936 int off
= e_rev
* esize
;
11937 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11939 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11940 tcg_rn
, off
- 64, esize
);
11942 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11945 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11946 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11948 tcg_temp_free_i64(tcg_rd_hi
);
11949 tcg_temp_free_i64(tcg_rd
);
11950 tcg_temp_free_i64(tcg_rn
);
11954 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11955 bool is_q
, int size
, int rn
, int rd
)
11957 /* Implement the pairwise operations from 2-misc:
11958 * SADDLP, UADDLP, SADALP, UADALP.
11959 * These all add pairs of elements in the input to produce a
11960 * double-width result element in the output (possibly accumulating).
11962 bool accum
= (opcode
== 0x6);
11963 int maxpass
= is_q
? 2 : 1;
11965 TCGv_i64 tcg_res
[2];
11968 /* 32 + 32 -> 64 op */
11969 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11971 for (pass
= 0; pass
< maxpass
; pass
++) {
11972 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11973 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11975 tcg_res
[pass
] = tcg_temp_new_i64();
11977 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11978 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11979 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11981 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11982 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11985 tcg_temp_free_i64(tcg_op1
);
11986 tcg_temp_free_i64(tcg_op2
);
11989 for (pass
= 0; pass
< maxpass
; pass
++) {
11990 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11991 NeonGenOneOpFn
*genfn
;
11992 static NeonGenOneOpFn
* const fns
[2][2] = {
11993 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11994 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11997 genfn
= fns
[size
][u
];
11999 tcg_res
[pass
] = tcg_temp_new_i64();
12001 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12002 genfn(tcg_res
[pass
], tcg_op
);
12005 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12007 gen_helper_neon_addl_u16(tcg_res
[pass
],
12008 tcg_res
[pass
], tcg_op
);
12010 gen_helper_neon_addl_u32(tcg_res
[pass
],
12011 tcg_res
[pass
], tcg_op
);
12014 tcg_temp_free_i64(tcg_op
);
12018 tcg_res
[1] = tcg_const_i64(0);
12020 for (pass
= 0; pass
< 2; pass
++) {
12021 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12022 tcg_temp_free_i64(tcg_res
[pass
]);
12026 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12028 /* Implement SHLL and SHLL2 */
12030 int part
= is_q
? 2 : 0;
12031 TCGv_i64 tcg_res
[2];
12033 for (pass
= 0; pass
< 2; pass
++) {
12034 static NeonGenWidenFn
* const widenfns
[3] = {
12035 gen_helper_neon_widen_u8
,
12036 gen_helper_neon_widen_u16
,
12037 tcg_gen_extu_i32_i64
,
12039 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12040 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12042 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12043 tcg_res
[pass
] = tcg_temp_new_i64();
12044 widenfn(tcg_res
[pass
], tcg_op
);
12045 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12047 tcg_temp_free_i32(tcg_op
);
12050 for (pass
= 0; pass
< 2; pass
++) {
12051 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12052 tcg_temp_free_i64(tcg_res
[pass
]);
12056 /* AdvSIMD two reg misc
12057 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12058 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12059 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12060 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12062 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12064 int size
= extract32(insn
, 22, 2);
12065 int opcode
= extract32(insn
, 12, 5);
12066 bool u
= extract32(insn
, 29, 1);
12067 bool is_q
= extract32(insn
, 30, 1);
12068 int rn
= extract32(insn
, 5, 5);
12069 int rd
= extract32(insn
, 0, 5);
12070 bool need_fpstatus
= false;
12071 bool need_rmode
= false;
12073 TCGv_i32 tcg_rmode
;
12074 TCGv_ptr tcg_fpstatus
;
12077 case 0x0: /* REV64, REV32 */
12078 case 0x1: /* REV16 */
12079 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12081 case 0x5: /* CNT, NOT, RBIT */
12082 if (u
&& size
== 0) {
12085 } else if (u
&& size
== 1) {
12088 } else if (!u
&& size
== 0) {
12092 unallocated_encoding(s
);
12094 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12095 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12097 unallocated_encoding(s
);
12100 if (!fp_access_check(s
)) {
12104 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12106 case 0x4: /* CLS, CLZ */
12108 unallocated_encoding(s
);
12112 case 0x2: /* SADDLP, UADDLP */
12113 case 0x6: /* SADALP, UADALP */
12115 unallocated_encoding(s
);
12118 if (!fp_access_check(s
)) {
12121 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12123 case 0x13: /* SHLL, SHLL2 */
12124 if (u
== 0 || size
== 3) {
12125 unallocated_encoding(s
);
12128 if (!fp_access_check(s
)) {
12131 handle_shll(s
, is_q
, size
, rn
, rd
);
12133 case 0xa: /* CMLT */
12135 unallocated_encoding(s
);
12139 case 0x8: /* CMGT, CMGE */
12140 case 0x9: /* CMEQ, CMLE */
12141 case 0xb: /* ABS, NEG */
12142 if (size
== 3 && !is_q
) {
12143 unallocated_encoding(s
);
12147 case 0x3: /* SUQADD, USQADD */
12148 if (size
== 3 && !is_q
) {
12149 unallocated_encoding(s
);
12152 if (!fp_access_check(s
)) {
12155 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12157 case 0x7: /* SQABS, SQNEG */
12158 if (size
== 3 && !is_q
) {
12159 unallocated_encoding(s
);
12164 case 0x16 ... 0x1f:
12166 /* Floating point: U, size[1] and opcode indicate operation;
12167 * size[0] indicates single or double precision.
12169 int is_double
= extract32(size
, 0, 1);
12170 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12171 size
= is_double
? 3 : 2;
12173 case 0x2f: /* FABS */
12174 case 0x6f: /* FNEG */
12175 if (size
== 3 && !is_q
) {
12176 unallocated_encoding(s
);
12180 case 0x1d: /* SCVTF */
12181 case 0x5d: /* UCVTF */
12183 bool is_signed
= (opcode
== 0x1d) ? true : false;
12184 int elements
= is_double
? 2 : is_q
? 4 : 2;
12185 if (is_double
&& !is_q
) {
12186 unallocated_encoding(s
);
12189 if (!fp_access_check(s
)) {
12192 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12195 case 0x2c: /* FCMGT (zero) */
12196 case 0x2d: /* FCMEQ (zero) */
12197 case 0x2e: /* FCMLT (zero) */
12198 case 0x6c: /* FCMGE (zero) */
12199 case 0x6d: /* FCMLE (zero) */
12200 if (size
== 3 && !is_q
) {
12201 unallocated_encoding(s
);
12204 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12206 case 0x7f: /* FSQRT */
12207 if (size
== 3 && !is_q
) {
12208 unallocated_encoding(s
);
12212 case 0x1a: /* FCVTNS */
12213 case 0x1b: /* FCVTMS */
12214 case 0x3a: /* FCVTPS */
12215 case 0x3b: /* FCVTZS */
12216 case 0x5a: /* FCVTNU */
12217 case 0x5b: /* FCVTMU */
12218 case 0x7a: /* FCVTPU */
12219 case 0x7b: /* FCVTZU */
12220 need_fpstatus
= true;
12222 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12223 if (size
== 3 && !is_q
) {
12224 unallocated_encoding(s
);
12228 case 0x5c: /* FCVTAU */
12229 case 0x1c: /* FCVTAS */
12230 need_fpstatus
= true;
12232 rmode
= FPROUNDING_TIEAWAY
;
12233 if (size
== 3 && !is_q
) {
12234 unallocated_encoding(s
);
12238 case 0x3c: /* URECPE */
12240 unallocated_encoding(s
);
12244 case 0x3d: /* FRECPE */
12245 case 0x7d: /* FRSQRTE */
12246 if (size
== 3 && !is_q
) {
12247 unallocated_encoding(s
);
12250 if (!fp_access_check(s
)) {
12253 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12255 case 0x56: /* FCVTXN, FCVTXN2 */
12257 unallocated_encoding(s
);
12261 case 0x16: /* FCVTN, FCVTN2 */
12262 /* handle_2misc_narrow does a 2*size -> size operation, but these
12263 * instructions encode the source size rather than dest size.
12265 if (!fp_access_check(s
)) {
12268 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12270 case 0x17: /* FCVTL, FCVTL2 */
12271 if (!fp_access_check(s
)) {
12274 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12276 case 0x18: /* FRINTN */
12277 case 0x19: /* FRINTM */
12278 case 0x38: /* FRINTP */
12279 case 0x39: /* FRINTZ */
12281 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12283 case 0x59: /* FRINTX */
12284 case 0x79: /* FRINTI */
12285 need_fpstatus
= true;
12286 if (size
== 3 && !is_q
) {
12287 unallocated_encoding(s
);
12291 case 0x58: /* FRINTA */
12293 rmode
= FPROUNDING_TIEAWAY
;
12294 need_fpstatus
= true;
12295 if (size
== 3 && !is_q
) {
12296 unallocated_encoding(s
);
12300 case 0x7c: /* URSQRTE */
12302 unallocated_encoding(s
);
12305 need_fpstatus
= true;
12307 case 0x1e: /* FRINT32Z */
12308 case 0x1f: /* FRINT64Z */
12310 rmode
= FPROUNDING_ZERO
;
12312 case 0x5e: /* FRINT32X */
12313 case 0x5f: /* FRINT64X */
12314 need_fpstatus
= true;
12315 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12316 unallocated_encoding(s
);
12321 unallocated_encoding(s
);
12327 unallocated_encoding(s
);
12331 if (!fp_access_check(s
)) {
12335 if (need_fpstatus
|| need_rmode
) {
12336 tcg_fpstatus
= get_fpstatus_ptr(false);
12338 tcg_fpstatus
= NULL
;
12341 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12342 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12349 if (u
&& size
== 0) { /* NOT */
12350 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12354 case 0x8: /* CMGT, CMGE */
12355 gen_gvec_op2(s
, is_q
, rd
, rn
, u
? &cge0_op
[size
] : &cgt0_op
[size
]);
12357 case 0x9: /* CMEQ, CMLE */
12358 gen_gvec_op2(s
, is_q
, rd
, rn
, u
? &cle0_op
[size
] : &ceq0_op
[size
]);
12360 case 0xa: /* CMLT */
12361 gen_gvec_op2(s
, is_q
, rd
, rn
, &clt0_op
[size
]);
12364 if (u
) { /* ABS, NEG */
12365 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12367 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12373 /* All 64-bit element operations can be shared with scalar 2misc */
12376 /* Coverity claims (size == 3 && !is_q) has been eliminated
12377 * from all paths leading to here.
12379 tcg_debug_assert(is_q
);
12380 for (pass
= 0; pass
< 2; pass
++) {
12381 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12382 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12384 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12386 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12387 tcg_rmode
, tcg_fpstatus
);
12389 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12391 tcg_temp_free_i64(tcg_res
);
12392 tcg_temp_free_i64(tcg_op
);
12397 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12398 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12399 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12401 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12404 /* Special cases for 32 bit elements */
12406 case 0x4: /* CLS */
12408 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12410 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12413 case 0x7: /* SQABS, SQNEG */
12415 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12417 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12420 case 0x2f: /* FABS */
12421 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12423 case 0x6f: /* FNEG */
12424 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12426 case 0x7f: /* FSQRT */
12427 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12429 case 0x1a: /* FCVTNS */
12430 case 0x1b: /* FCVTMS */
12431 case 0x1c: /* FCVTAS */
12432 case 0x3a: /* FCVTPS */
12433 case 0x3b: /* FCVTZS */
12435 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12436 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12437 tcg_shift
, tcg_fpstatus
);
12438 tcg_temp_free_i32(tcg_shift
);
12441 case 0x5a: /* FCVTNU */
12442 case 0x5b: /* FCVTMU */
12443 case 0x5c: /* FCVTAU */
12444 case 0x7a: /* FCVTPU */
12445 case 0x7b: /* FCVTZU */
12447 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12448 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12449 tcg_shift
, tcg_fpstatus
);
12450 tcg_temp_free_i32(tcg_shift
);
12453 case 0x18: /* FRINTN */
12454 case 0x19: /* FRINTM */
12455 case 0x38: /* FRINTP */
12456 case 0x39: /* FRINTZ */
12457 case 0x58: /* FRINTA */
12458 case 0x79: /* FRINTI */
12459 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12461 case 0x59: /* FRINTX */
12462 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12464 case 0x7c: /* URSQRTE */
12465 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12467 case 0x1e: /* FRINT32Z */
12468 case 0x5e: /* FRINT32X */
12469 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12471 case 0x1f: /* FRINT64Z */
12472 case 0x5f: /* FRINT64X */
12473 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12476 g_assert_not_reached();
12479 /* Use helpers for 8 and 16 bit elements */
12481 case 0x5: /* CNT, RBIT */
12482 /* For these two insns size is part of the opcode specifier
12483 * (handled earlier); they always operate on byte elements.
12486 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12488 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12491 case 0x7: /* SQABS, SQNEG */
12493 NeonGenOneOpEnvFn
*genfn
;
12494 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12495 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12496 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12498 genfn
= fns
[size
][u
];
12499 genfn(tcg_res
, cpu_env
, tcg_op
);
12502 case 0x4: /* CLS, CLZ */
12505 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12507 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12511 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12513 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12518 g_assert_not_reached();
12522 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12524 tcg_temp_free_i32(tcg_res
);
12525 tcg_temp_free_i32(tcg_op
);
12528 clear_vec_high(s
, is_q
, rd
);
12531 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12532 tcg_temp_free_i32(tcg_rmode
);
12534 if (need_fpstatus
) {
12535 tcg_temp_free_ptr(tcg_fpstatus
);
12539 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12541 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12542 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12543 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12544 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12545 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12546 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12548 * This actually covers two groups where scalar access is governed by
12549 * bit 28. A bunch of the instructions (float to integral) only exist
12550 * in the vector form and are un-allocated for the scalar decode. Also
12551 * in the scalar decode Q is always 1.
12553 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12555 int fpop
, opcode
, a
, u
;
12559 bool only_in_vector
= false;
12562 TCGv_i32 tcg_rmode
= NULL
;
12563 TCGv_ptr tcg_fpstatus
= NULL
;
12564 bool need_rmode
= false;
12565 bool need_fpst
= true;
12568 if (!dc_isar_feature(aa64_fp16
, s
)) {
12569 unallocated_encoding(s
);
12573 rd
= extract32(insn
, 0, 5);
12574 rn
= extract32(insn
, 5, 5);
12576 a
= extract32(insn
, 23, 1);
12577 u
= extract32(insn
, 29, 1);
12578 is_scalar
= extract32(insn
, 28, 1);
12579 is_q
= extract32(insn
, 30, 1);
12581 opcode
= extract32(insn
, 12, 5);
12582 fpop
= deposit32(opcode
, 5, 1, a
);
12583 fpop
= deposit32(fpop
, 6, 1, u
);
12585 rd
= extract32(insn
, 0, 5);
12586 rn
= extract32(insn
, 5, 5);
12589 case 0x1d: /* SCVTF */
12590 case 0x5d: /* UCVTF */
12597 elements
= (is_q
? 8 : 4);
12600 if (!fp_access_check(s
)) {
12603 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12607 case 0x2c: /* FCMGT (zero) */
12608 case 0x2d: /* FCMEQ (zero) */
12609 case 0x2e: /* FCMLT (zero) */
12610 case 0x6c: /* FCMGE (zero) */
12611 case 0x6d: /* FCMLE (zero) */
12612 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12614 case 0x3d: /* FRECPE */
12615 case 0x3f: /* FRECPX */
12617 case 0x18: /* FRINTN */
12619 only_in_vector
= true;
12620 rmode
= FPROUNDING_TIEEVEN
;
12622 case 0x19: /* FRINTM */
12624 only_in_vector
= true;
12625 rmode
= FPROUNDING_NEGINF
;
12627 case 0x38: /* FRINTP */
12629 only_in_vector
= true;
12630 rmode
= FPROUNDING_POSINF
;
12632 case 0x39: /* FRINTZ */
12634 only_in_vector
= true;
12635 rmode
= FPROUNDING_ZERO
;
12637 case 0x58: /* FRINTA */
12639 only_in_vector
= true;
12640 rmode
= FPROUNDING_TIEAWAY
;
12642 case 0x59: /* FRINTX */
12643 case 0x79: /* FRINTI */
12644 only_in_vector
= true;
12645 /* current rounding mode */
12647 case 0x1a: /* FCVTNS */
12649 rmode
= FPROUNDING_TIEEVEN
;
12651 case 0x1b: /* FCVTMS */
12653 rmode
= FPROUNDING_NEGINF
;
12655 case 0x1c: /* FCVTAS */
12657 rmode
= FPROUNDING_TIEAWAY
;
12659 case 0x3a: /* FCVTPS */
12661 rmode
= FPROUNDING_POSINF
;
12663 case 0x3b: /* FCVTZS */
12665 rmode
= FPROUNDING_ZERO
;
12667 case 0x5a: /* FCVTNU */
12669 rmode
= FPROUNDING_TIEEVEN
;
12671 case 0x5b: /* FCVTMU */
12673 rmode
= FPROUNDING_NEGINF
;
12675 case 0x5c: /* FCVTAU */
12677 rmode
= FPROUNDING_TIEAWAY
;
12679 case 0x7a: /* FCVTPU */
12681 rmode
= FPROUNDING_POSINF
;
12683 case 0x7b: /* FCVTZU */
12685 rmode
= FPROUNDING_ZERO
;
12687 case 0x2f: /* FABS */
12688 case 0x6f: /* FNEG */
12691 case 0x7d: /* FRSQRTE */
12692 case 0x7f: /* FSQRT (vector) */
12695 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12696 g_assert_not_reached();
12700 /* Check additional constraints for the scalar encoding */
12703 unallocated_encoding(s
);
12706 /* FRINTxx is only in the vector form */
12707 if (only_in_vector
) {
12708 unallocated_encoding(s
);
12713 if (!fp_access_check(s
)) {
12717 if (need_rmode
|| need_fpst
) {
12718 tcg_fpstatus
= get_fpstatus_ptr(true);
12722 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12723 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12727 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12728 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12731 case 0x1a: /* FCVTNS */
12732 case 0x1b: /* FCVTMS */
12733 case 0x1c: /* FCVTAS */
12734 case 0x3a: /* FCVTPS */
12735 case 0x3b: /* FCVTZS */
12736 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12738 case 0x3d: /* FRECPE */
12739 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12741 case 0x3f: /* FRECPX */
12742 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12744 case 0x5a: /* FCVTNU */
12745 case 0x5b: /* FCVTMU */
12746 case 0x5c: /* FCVTAU */
12747 case 0x7a: /* FCVTPU */
12748 case 0x7b: /* FCVTZU */
12749 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12751 case 0x6f: /* FNEG */
12752 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12754 case 0x7d: /* FRSQRTE */
12755 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12758 g_assert_not_reached();
12761 /* limit any sign extension going on */
12762 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12763 write_fp_sreg(s
, rd
, tcg_res
);
12765 tcg_temp_free_i32(tcg_res
);
12766 tcg_temp_free_i32(tcg_op
);
12768 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12769 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12770 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12772 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12775 case 0x1a: /* FCVTNS */
12776 case 0x1b: /* FCVTMS */
12777 case 0x1c: /* FCVTAS */
12778 case 0x3a: /* FCVTPS */
12779 case 0x3b: /* FCVTZS */
12780 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12782 case 0x3d: /* FRECPE */
12783 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12785 case 0x5a: /* FCVTNU */
12786 case 0x5b: /* FCVTMU */
12787 case 0x5c: /* FCVTAU */
12788 case 0x7a: /* FCVTPU */
12789 case 0x7b: /* FCVTZU */
12790 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12792 case 0x18: /* FRINTN */
12793 case 0x19: /* FRINTM */
12794 case 0x38: /* FRINTP */
12795 case 0x39: /* FRINTZ */
12796 case 0x58: /* FRINTA */
12797 case 0x79: /* FRINTI */
12798 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12800 case 0x59: /* FRINTX */
12801 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12803 case 0x2f: /* FABS */
12804 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12806 case 0x6f: /* FNEG */
12807 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12809 case 0x7d: /* FRSQRTE */
12810 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12812 case 0x7f: /* FSQRT */
12813 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12816 g_assert_not_reached();
12819 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12821 tcg_temp_free_i32(tcg_res
);
12822 tcg_temp_free_i32(tcg_op
);
12825 clear_vec_high(s
, is_q
, rd
);
12829 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12830 tcg_temp_free_i32(tcg_rmode
);
12833 if (tcg_fpstatus
) {
12834 tcg_temp_free_ptr(tcg_fpstatus
);
12838 /* AdvSIMD scalar x indexed element
12839 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12840 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12841 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12842 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12843 * AdvSIMD vector x indexed element
12844 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12845 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12846 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12847 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12849 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12851 /* This encoding has two kinds of instruction:
12852 * normal, where we perform elt x idxelt => elt for each
12853 * element in the vector
12854 * long, where we perform elt x idxelt and generate a result of
12855 * double the width of the input element
12856 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12858 bool is_scalar
= extract32(insn
, 28, 1);
12859 bool is_q
= extract32(insn
, 30, 1);
12860 bool u
= extract32(insn
, 29, 1);
12861 int size
= extract32(insn
, 22, 2);
12862 int l
= extract32(insn
, 21, 1);
12863 int m
= extract32(insn
, 20, 1);
12864 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12865 int rm
= extract32(insn
, 16, 4);
12866 int opcode
= extract32(insn
, 12, 4);
12867 int h
= extract32(insn
, 11, 1);
12868 int rn
= extract32(insn
, 5, 5);
12869 int rd
= extract32(insn
, 0, 5);
12870 bool is_long
= false;
12872 bool is_fp16
= false;
12876 switch (16 * u
+ opcode
) {
12877 case 0x08: /* MUL */
12878 case 0x10: /* MLA */
12879 case 0x14: /* MLS */
12881 unallocated_encoding(s
);
12885 case 0x02: /* SMLAL, SMLAL2 */
12886 case 0x12: /* UMLAL, UMLAL2 */
12887 case 0x06: /* SMLSL, SMLSL2 */
12888 case 0x16: /* UMLSL, UMLSL2 */
12889 case 0x0a: /* SMULL, SMULL2 */
12890 case 0x1a: /* UMULL, UMULL2 */
12892 unallocated_encoding(s
);
12897 case 0x03: /* SQDMLAL, SQDMLAL2 */
12898 case 0x07: /* SQDMLSL, SQDMLSL2 */
12899 case 0x0b: /* SQDMULL, SQDMULL2 */
12902 case 0x0c: /* SQDMULH */
12903 case 0x0d: /* SQRDMULH */
12905 case 0x01: /* FMLA */
12906 case 0x05: /* FMLS */
12907 case 0x09: /* FMUL */
12908 case 0x19: /* FMULX */
12911 case 0x1d: /* SQRDMLAH */
12912 case 0x1f: /* SQRDMLSH */
12913 if (!dc_isar_feature(aa64_rdm
, s
)) {
12914 unallocated_encoding(s
);
12918 case 0x0e: /* SDOT */
12919 case 0x1e: /* UDOT */
12920 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12921 unallocated_encoding(s
);
12925 case 0x11: /* FCMLA #0 */
12926 case 0x13: /* FCMLA #90 */
12927 case 0x15: /* FCMLA #180 */
12928 case 0x17: /* FCMLA #270 */
12929 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12930 unallocated_encoding(s
);
12935 case 0x00: /* FMLAL */
12936 case 0x04: /* FMLSL */
12937 case 0x18: /* FMLAL2 */
12938 case 0x1c: /* FMLSL2 */
12939 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12940 unallocated_encoding(s
);
12944 /* is_fp, but we pass cpu_env not fp_status. */
12947 unallocated_encoding(s
);
12952 case 1: /* normal fp */
12953 /* convert insn encoded size to MemOp size */
12955 case 0: /* half-precision */
12959 case MO_32
: /* single precision */
12960 case MO_64
: /* double precision */
12963 unallocated_encoding(s
);
12968 case 2: /* complex fp */
12969 /* Each indexable element is a complex pair. */
12974 unallocated_encoding(s
);
12982 unallocated_encoding(s
);
12987 default: /* integer */
12991 unallocated_encoding(s
);
12996 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12997 unallocated_encoding(s
);
13001 /* Given MemOp size, adjust register and indexing. */
13004 index
= h
<< 2 | l
<< 1 | m
;
13007 index
= h
<< 1 | l
;
13012 unallocated_encoding(s
);
13019 g_assert_not_reached();
13022 if (!fp_access_check(s
)) {
13027 fpst
= get_fpstatus_ptr(is_fp16
);
13032 switch (16 * u
+ opcode
) {
13033 case 0x0e: /* SDOT */
13034 case 0x1e: /* UDOT */
13035 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
13036 u
? gen_helper_gvec_udot_idx_b
13037 : gen_helper_gvec_sdot_idx_b
);
13039 case 0x11: /* FCMLA #0 */
13040 case 0x13: /* FCMLA #90 */
13041 case 0x15: /* FCMLA #180 */
13042 case 0x17: /* FCMLA #270 */
13044 int rot
= extract32(insn
, 13, 2);
13045 int data
= (index
<< 2) | rot
;
13046 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13047 vec_full_reg_offset(s
, rn
),
13048 vec_full_reg_offset(s
, rm
), fpst
,
13049 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13051 ? gen_helper_gvec_fcmlas_idx
13052 : gen_helper_gvec_fcmlah_idx
);
13053 tcg_temp_free_ptr(fpst
);
13057 case 0x00: /* FMLAL */
13058 case 0x04: /* FMLSL */
13059 case 0x18: /* FMLAL2 */
13060 case 0x1c: /* FMLSL2 */
13062 int is_s
= extract32(opcode
, 2, 1);
13064 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13065 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13066 vec_full_reg_offset(s
, rn
),
13067 vec_full_reg_offset(s
, rm
), cpu_env
,
13068 is_q
? 16 : 8, vec_full_reg_size(s
),
13069 data
, gen_helper_gvec_fmlal_idx_a64
);
13075 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13078 assert(is_fp
&& is_q
&& !is_long
);
13080 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13082 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13083 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13084 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13086 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13088 switch (16 * u
+ opcode
) {
13089 case 0x05: /* FMLS */
13090 /* As usual for ARM, separate negation for fused multiply-add */
13091 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13093 case 0x01: /* FMLA */
13094 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13095 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13097 case 0x09: /* FMUL */
13098 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13100 case 0x19: /* FMULX */
13101 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13104 g_assert_not_reached();
13107 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13108 tcg_temp_free_i64(tcg_op
);
13109 tcg_temp_free_i64(tcg_res
);
13112 tcg_temp_free_i64(tcg_idx
);
13113 clear_vec_high(s
, !is_scalar
, rd
);
13114 } else if (!is_long
) {
13115 /* 32 bit floating point, or 16 or 32 bit integer.
13116 * For the 16 bit scalar case we use the usual Neon helpers and
13117 * rely on the fact that 0 op 0 == 0 with no side effects.
13119 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13120 int pass
, maxpasses
;
13125 maxpasses
= is_q
? 4 : 2;
13128 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13130 if (size
== 1 && !is_scalar
) {
13131 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13132 * the index into both halves of the 32 bit tcg_idx and then use
13133 * the usual Neon helpers.
13135 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13138 for (pass
= 0; pass
< maxpasses
; pass
++) {
13139 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13140 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13142 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13144 switch (16 * u
+ opcode
) {
13145 case 0x08: /* MUL */
13146 case 0x10: /* MLA */
13147 case 0x14: /* MLS */
13149 static NeonGenTwoOpFn
* const fns
[2][2] = {
13150 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13151 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13153 NeonGenTwoOpFn
*genfn
;
13154 bool is_sub
= opcode
== 0x4;
13157 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13159 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13161 if (opcode
== 0x8) {
13164 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13165 genfn
= fns
[size
- 1][is_sub
];
13166 genfn(tcg_res
, tcg_op
, tcg_res
);
13169 case 0x05: /* FMLS */
13170 case 0x01: /* FMLA */
13171 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13172 is_scalar
? size
: MO_32
);
13175 if (opcode
== 0x5) {
13176 /* As usual for ARM, separate negation for fused
13178 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13181 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13184 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13189 if (opcode
== 0x5) {
13190 /* As usual for ARM, separate negation for
13191 * fused multiply-add */
13192 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13194 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13198 g_assert_not_reached();
13201 case 0x09: /* FMUL */
13205 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13208 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13213 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13216 g_assert_not_reached();
13219 case 0x19: /* FMULX */
13223 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13226 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13231 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13234 g_assert_not_reached();
13237 case 0x0c: /* SQDMULH */
13239 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13242 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13246 case 0x0d: /* SQRDMULH */
13248 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13251 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13255 case 0x1d: /* SQRDMLAH */
13256 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13257 is_scalar
? size
: MO_32
);
13259 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13260 tcg_op
, tcg_idx
, tcg_res
);
13262 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13263 tcg_op
, tcg_idx
, tcg_res
);
13266 case 0x1f: /* SQRDMLSH */
13267 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13268 is_scalar
? size
: MO_32
);
13270 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13271 tcg_op
, tcg_idx
, tcg_res
);
13273 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13274 tcg_op
, tcg_idx
, tcg_res
);
13278 g_assert_not_reached();
13282 write_fp_sreg(s
, rd
, tcg_res
);
13284 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13287 tcg_temp_free_i32(tcg_op
);
13288 tcg_temp_free_i32(tcg_res
);
13291 tcg_temp_free_i32(tcg_idx
);
13292 clear_vec_high(s
, is_q
, rd
);
13294 /* long ops: 16x16->32 or 32x32->64 */
13295 TCGv_i64 tcg_res
[2];
13297 bool satop
= extract32(opcode
, 0, 1);
13298 MemOp memop
= MO_32
;
13305 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13307 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13309 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13310 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13311 TCGv_i64 tcg_passres
;
13317 passelt
= pass
+ (is_q
* 2);
13320 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13322 tcg_res
[pass
] = tcg_temp_new_i64();
13324 if (opcode
== 0xa || opcode
== 0xb) {
13325 /* Non-accumulating ops */
13326 tcg_passres
= tcg_res
[pass
];
13328 tcg_passres
= tcg_temp_new_i64();
13331 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13332 tcg_temp_free_i64(tcg_op
);
13335 /* saturating, doubling */
13336 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13337 tcg_passres
, tcg_passres
);
13340 if (opcode
== 0xa || opcode
== 0xb) {
13344 /* Accumulating op: handle accumulate step */
13345 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13348 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13349 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13351 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13352 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13354 case 0x7: /* SQDMLSL, SQDMLSL2 */
13355 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13357 case 0x3: /* SQDMLAL, SQDMLAL2 */
13358 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13363 g_assert_not_reached();
13365 tcg_temp_free_i64(tcg_passres
);
13367 tcg_temp_free_i64(tcg_idx
);
13369 clear_vec_high(s
, !is_scalar
, rd
);
13371 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13374 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13377 /* The simplest way to handle the 16x16 indexed ops is to
13378 * duplicate the index into both halves of the 32 bit tcg_idx
13379 * and then use the usual Neon helpers.
13381 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13384 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13385 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13386 TCGv_i64 tcg_passres
;
13389 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13391 read_vec_element_i32(s
, tcg_op
, rn
,
13392 pass
+ (is_q
* 2), MO_32
);
13395 tcg_res
[pass
] = tcg_temp_new_i64();
13397 if (opcode
== 0xa || opcode
== 0xb) {
13398 /* Non-accumulating ops */
13399 tcg_passres
= tcg_res
[pass
];
13401 tcg_passres
= tcg_temp_new_i64();
13404 if (memop
& MO_SIGN
) {
13405 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13407 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13410 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13411 tcg_passres
, tcg_passres
);
13413 tcg_temp_free_i32(tcg_op
);
13415 if (opcode
== 0xa || opcode
== 0xb) {
13419 /* Accumulating op: handle accumulate step */
13420 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13423 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13424 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13427 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13428 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13431 case 0x7: /* SQDMLSL, SQDMLSL2 */
13432 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13434 case 0x3: /* SQDMLAL, SQDMLAL2 */
13435 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13440 g_assert_not_reached();
13442 tcg_temp_free_i64(tcg_passres
);
13444 tcg_temp_free_i32(tcg_idx
);
13447 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13452 tcg_res
[1] = tcg_const_i64(0);
13455 for (pass
= 0; pass
< 2; pass
++) {
13456 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13457 tcg_temp_free_i64(tcg_res
[pass
]);
13462 tcg_temp_free_ptr(fpst
);
13467 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13468 * +-----------------+------+-----------+--------+-----+------+------+
13469 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13470 * +-----------------+------+-----------+--------+-----+------+------+
13472 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13474 int size
= extract32(insn
, 22, 2);
13475 int opcode
= extract32(insn
, 12, 5);
13476 int rn
= extract32(insn
, 5, 5);
13477 int rd
= extract32(insn
, 0, 5);
13479 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13480 TCGv_i32 tcg_decrypt
;
13481 CryptoThreeOpIntFn
*genfn
;
13483 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13484 unallocated_encoding(s
);
13489 case 0x4: /* AESE */
13491 genfn
= gen_helper_crypto_aese
;
13493 case 0x6: /* AESMC */
13495 genfn
= gen_helper_crypto_aesmc
;
13497 case 0x5: /* AESD */
13499 genfn
= gen_helper_crypto_aese
;
13501 case 0x7: /* AESIMC */
13503 genfn
= gen_helper_crypto_aesmc
;
13506 unallocated_encoding(s
);
13510 if (!fp_access_check(s
)) {
13514 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13515 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13516 tcg_decrypt
= tcg_const_i32(decrypt
);
13518 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13520 tcg_temp_free_ptr(tcg_rd_ptr
);
13521 tcg_temp_free_ptr(tcg_rn_ptr
);
13522 tcg_temp_free_i32(tcg_decrypt
);
13525 /* Crypto three-reg SHA
13526 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13527 * +-----------------+------+---+------+---+--------+-----+------+------+
13528 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13529 * +-----------------+------+---+------+---+--------+-----+------+------+
13531 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13533 int size
= extract32(insn
, 22, 2);
13534 int opcode
= extract32(insn
, 12, 3);
13535 int rm
= extract32(insn
, 16, 5);
13536 int rn
= extract32(insn
, 5, 5);
13537 int rd
= extract32(insn
, 0, 5);
13538 CryptoThreeOpFn
*genfn
;
13539 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13543 unallocated_encoding(s
);
13548 case 0: /* SHA1C */
13549 case 1: /* SHA1P */
13550 case 2: /* SHA1M */
13551 case 3: /* SHA1SU0 */
13553 feature
= dc_isar_feature(aa64_sha1
, s
);
13555 case 4: /* SHA256H */
13556 genfn
= gen_helper_crypto_sha256h
;
13557 feature
= dc_isar_feature(aa64_sha256
, s
);
13559 case 5: /* SHA256H2 */
13560 genfn
= gen_helper_crypto_sha256h2
;
13561 feature
= dc_isar_feature(aa64_sha256
, s
);
13563 case 6: /* SHA256SU1 */
13564 genfn
= gen_helper_crypto_sha256su1
;
13565 feature
= dc_isar_feature(aa64_sha256
, s
);
13568 unallocated_encoding(s
);
13573 unallocated_encoding(s
);
13577 if (!fp_access_check(s
)) {
13581 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13582 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13583 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13586 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13588 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13590 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13591 tcg_rm_ptr
, tcg_opcode
);
13592 tcg_temp_free_i32(tcg_opcode
);
13595 tcg_temp_free_ptr(tcg_rd_ptr
);
13596 tcg_temp_free_ptr(tcg_rn_ptr
);
13597 tcg_temp_free_ptr(tcg_rm_ptr
);
13600 /* Crypto two-reg SHA
13601 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13602 * +-----------------+------+-----------+--------+-----+------+------+
13603 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13604 * +-----------------+------+-----------+--------+-----+------+------+
13606 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13608 int size
= extract32(insn
, 22, 2);
13609 int opcode
= extract32(insn
, 12, 5);
13610 int rn
= extract32(insn
, 5, 5);
13611 int rd
= extract32(insn
, 0, 5);
13612 CryptoTwoOpFn
*genfn
;
13614 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13617 unallocated_encoding(s
);
13622 case 0: /* SHA1H */
13623 feature
= dc_isar_feature(aa64_sha1
, s
);
13624 genfn
= gen_helper_crypto_sha1h
;
13626 case 1: /* SHA1SU1 */
13627 feature
= dc_isar_feature(aa64_sha1
, s
);
13628 genfn
= gen_helper_crypto_sha1su1
;
13630 case 2: /* SHA256SU0 */
13631 feature
= dc_isar_feature(aa64_sha256
, s
);
13632 genfn
= gen_helper_crypto_sha256su0
;
13635 unallocated_encoding(s
);
13640 unallocated_encoding(s
);
13644 if (!fp_access_check(s
)) {
13648 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13649 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13651 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13653 tcg_temp_free_ptr(tcg_rd_ptr
);
13654 tcg_temp_free_ptr(tcg_rn_ptr
);
13657 /* Crypto three-reg SHA512
13658 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13659 * +-----------------------+------+---+---+-----+--------+------+------+
13660 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13661 * +-----------------------+------+---+---+-----+--------+------+------+
13663 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13665 int opcode
= extract32(insn
, 10, 2);
13666 int o
= extract32(insn
, 14, 1);
13667 int rm
= extract32(insn
, 16, 5);
13668 int rn
= extract32(insn
, 5, 5);
13669 int rd
= extract32(insn
, 0, 5);
13671 CryptoThreeOpFn
*genfn
;
13675 case 0: /* SHA512H */
13676 feature
= dc_isar_feature(aa64_sha512
, s
);
13677 genfn
= gen_helper_crypto_sha512h
;
13679 case 1: /* SHA512H2 */
13680 feature
= dc_isar_feature(aa64_sha512
, s
);
13681 genfn
= gen_helper_crypto_sha512h2
;
13683 case 2: /* SHA512SU1 */
13684 feature
= dc_isar_feature(aa64_sha512
, s
);
13685 genfn
= gen_helper_crypto_sha512su1
;
13688 feature
= dc_isar_feature(aa64_sha3
, s
);
13692 g_assert_not_reached();
13696 case 0: /* SM3PARTW1 */
13697 feature
= dc_isar_feature(aa64_sm3
, s
);
13698 genfn
= gen_helper_crypto_sm3partw1
;
13700 case 1: /* SM3PARTW2 */
13701 feature
= dc_isar_feature(aa64_sm3
, s
);
13702 genfn
= gen_helper_crypto_sm3partw2
;
13704 case 2: /* SM4EKEY */
13705 feature
= dc_isar_feature(aa64_sm4
, s
);
13706 genfn
= gen_helper_crypto_sm4ekey
;
13709 unallocated_encoding(s
);
13715 unallocated_encoding(s
);
13719 if (!fp_access_check(s
)) {
13724 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13726 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13727 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13728 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13730 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13732 tcg_temp_free_ptr(tcg_rd_ptr
);
13733 tcg_temp_free_ptr(tcg_rn_ptr
);
13734 tcg_temp_free_ptr(tcg_rm_ptr
);
13736 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13739 tcg_op1
= tcg_temp_new_i64();
13740 tcg_op2
= tcg_temp_new_i64();
13741 tcg_res
[0] = tcg_temp_new_i64();
13742 tcg_res
[1] = tcg_temp_new_i64();
13744 for (pass
= 0; pass
< 2; pass
++) {
13745 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13746 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13748 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13749 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13751 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13752 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13754 tcg_temp_free_i64(tcg_op1
);
13755 tcg_temp_free_i64(tcg_op2
);
13756 tcg_temp_free_i64(tcg_res
[0]);
13757 tcg_temp_free_i64(tcg_res
[1]);
13761 /* Crypto two-reg SHA512
13762 * 31 12 11 10 9 5 4 0
13763 * +-----------------------------------------+--------+------+------+
13764 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13765 * +-----------------------------------------+--------+------+------+
13767 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13769 int opcode
= extract32(insn
, 10, 2);
13770 int rn
= extract32(insn
, 5, 5);
13771 int rd
= extract32(insn
, 0, 5);
13772 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13774 CryptoTwoOpFn
*genfn
;
13777 case 0: /* SHA512SU0 */
13778 feature
= dc_isar_feature(aa64_sha512
, s
);
13779 genfn
= gen_helper_crypto_sha512su0
;
13782 feature
= dc_isar_feature(aa64_sm4
, s
);
13783 genfn
= gen_helper_crypto_sm4e
;
13786 unallocated_encoding(s
);
13791 unallocated_encoding(s
);
13795 if (!fp_access_check(s
)) {
13799 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13800 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13802 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13804 tcg_temp_free_ptr(tcg_rd_ptr
);
13805 tcg_temp_free_ptr(tcg_rn_ptr
);
13808 /* Crypto four-register
13809 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13810 * +-------------------+-----+------+---+------+------+------+
13811 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13812 * +-------------------+-----+------+---+------+------+------+
13814 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13816 int op0
= extract32(insn
, 21, 2);
13817 int rm
= extract32(insn
, 16, 5);
13818 int ra
= extract32(insn
, 10, 5);
13819 int rn
= extract32(insn
, 5, 5);
13820 int rd
= extract32(insn
, 0, 5);
13826 feature
= dc_isar_feature(aa64_sha3
, s
);
13828 case 2: /* SM3SS1 */
13829 feature
= dc_isar_feature(aa64_sm3
, s
);
13832 unallocated_encoding(s
);
13837 unallocated_encoding(s
);
13841 if (!fp_access_check(s
)) {
13846 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13849 tcg_op1
= tcg_temp_new_i64();
13850 tcg_op2
= tcg_temp_new_i64();
13851 tcg_op3
= tcg_temp_new_i64();
13852 tcg_res
[0] = tcg_temp_new_i64();
13853 tcg_res
[1] = tcg_temp_new_i64();
13855 for (pass
= 0; pass
< 2; pass
++) {
13856 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13857 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13858 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13862 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13865 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13867 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13869 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13870 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13872 tcg_temp_free_i64(tcg_op1
);
13873 tcg_temp_free_i64(tcg_op2
);
13874 tcg_temp_free_i64(tcg_op3
);
13875 tcg_temp_free_i64(tcg_res
[0]);
13876 tcg_temp_free_i64(tcg_res
[1]);
13878 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13880 tcg_op1
= tcg_temp_new_i32();
13881 tcg_op2
= tcg_temp_new_i32();
13882 tcg_op3
= tcg_temp_new_i32();
13883 tcg_res
= tcg_temp_new_i32();
13884 tcg_zero
= tcg_const_i32(0);
13886 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13887 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13888 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13890 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13891 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13892 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13893 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13895 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13896 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13897 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13898 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13900 tcg_temp_free_i32(tcg_op1
);
13901 tcg_temp_free_i32(tcg_op2
);
13902 tcg_temp_free_i32(tcg_op3
);
13903 tcg_temp_free_i32(tcg_res
);
13904 tcg_temp_free_i32(tcg_zero
);
13909 * 31 21 20 16 15 10 9 5 4 0
13910 * +-----------------------+------+--------+------+------+
13911 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13912 * +-----------------------+------+--------+------+------+
13914 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13916 int rm
= extract32(insn
, 16, 5);
13917 int imm6
= extract32(insn
, 10, 6);
13918 int rn
= extract32(insn
, 5, 5);
13919 int rd
= extract32(insn
, 0, 5);
13920 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13923 if (!dc_isar_feature(aa64_sha3
, s
)) {
13924 unallocated_encoding(s
);
13928 if (!fp_access_check(s
)) {
13932 tcg_op1
= tcg_temp_new_i64();
13933 tcg_op2
= tcg_temp_new_i64();
13934 tcg_res
[0] = tcg_temp_new_i64();
13935 tcg_res
[1] = tcg_temp_new_i64();
13937 for (pass
= 0; pass
< 2; pass
++) {
13938 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13939 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13941 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13942 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13944 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13945 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13947 tcg_temp_free_i64(tcg_op1
);
13948 tcg_temp_free_i64(tcg_op2
);
13949 tcg_temp_free_i64(tcg_res
[0]);
13950 tcg_temp_free_i64(tcg_res
[1]);
13953 /* Crypto three-reg imm2
13954 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13955 * +-----------------------+------+-----+------+--------+------+------+
13956 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13957 * +-----------------------+------+-----+------+--------+------+------+
13959 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13961 int opcode
= extract32(insn
, 10, 2);
13962 int imm2
= extract32(insn
, 12, 2);
13963 int rm
= extract32(insn
, 16, 5);
13964 int rn
= extract32(insn
, 5, 5);
13965 int rd
= extract32(insn
, 0, 5);
13966 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13967 TCGv_i32 tcg_imm2
, tcg_opcode
;
13969 if (!dc_isar_feature(aa64_sm3
, s
)) {
13970 unallocated_encoding(s
);
13974 if (!fp_access_check(s
)) {
13978 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13979 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13980 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13981 tcg_imm2
= tcg_const_i32(imm2
);
13982 tcg_opcode
= tcg_const_i32(opcode
);
13984 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13987 tcg_temp_free_ptr(tcg_rd_ptr
);
13988 tcg_temp_free_ptr(tcg_rn_ptr
);
13989 tcg_temp_free_ptr(tcg_rm_ptr
);
13990 tcg_temp_free_i32(tcg_imm2
);
13991 tcg_temp_free_i32(tcg_opcode
);
13994 /* C3.6 Data processing - SIMD, inc Crypto
13996 * As the decode gets a little complex we are using a table based
13997 * approach for this part of the decode.
13999 static const AArch64DecodeTable data_proc_simd
[] = {
14000 /* pattern , mask , fn */
14001 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
14002 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
14003 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
14004 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
14005 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
14006 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
14007 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
14008 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
14009 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
14010 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
14011 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
14012 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
14013 { 0x2e000000, 0xbf208400, disas_simd_ext
},
14014 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
14015 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
14016 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14017 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14018 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14019 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14020 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14021 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14022 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14023 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14024 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14025 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14026 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14027 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14028 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14029 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14030 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14031 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14032 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14033 { 0x00000000, 0x00000000, NULL
}
14036 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14038 /* Note that this is called with all non-FP cases from
14039 * table C3-6 so it must UNDEF for entries not specifically
14040 * allocated to instructions in that table.
14042 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14046 unallocated_encoding(s
);
14050 /* C3.6 Data processing - SIMD and floating point */
14051 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14053 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14054 disas_data_proc_fp(s
, insn
);
14056 /* SIMD, including crypto */
14057 disas_data_proc_simd(s
, insn
);
14063 * @env: The cpu environment
14064 * @s: The DisasContext
14066 * Return true if the page is guarded.
14068 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14070 #ifdef CONFIG_USER_ONLY
14071 return false; /* FIXME */
14073 uint64_t addr
= s
->base
.pc_first
;
14074 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14075 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14076 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14079 * We test this immediately after reading an insn, which means
14080 * that any normal page must be in the TLB. The only exception
14081 * would be for executing from flash or device memory, which
14082 * does not retain the TLB entry.
14084 * FIXME: Assume false for those, for now. We could use
14085 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14086 * table entry even for that case.
14088 return (tlb_hit(entry
->addr_code
, addr
) &&
14089 env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
.target_tlb_bit0
);
14094 * btype_destination_ok:
14095 * @insn: The instruction at the branch destination
14096 * @bt: SCTLR_ELx.BT
14097 * @btype: PSTATE.BTYPE, and is non-zero
14099 * On a guarded page, there are a limited number of insns
14100 * that may be present at the branch target:
14101 * - branch target identifiers,
14102 * - paciasp, pacibsp,
14105 * Anything else causes a Branch Target Exception.
14107 * Return true if the branch is compatible, false to raise BTITRAP.
14109 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14111 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14113 switch (extract32(insn
, 5, 7)) {
14114 case 0b011001: /* PACIASP */
14115 case 0b011011: /* PACIBSP */
14117 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14118 * with btype == 3. Otherwise all btype are ok.
14120 return !bt
|| btype
!= 3;
14121 case 0b100000: /* BTI */
14122 /* Not compatible with any btype. */
14124 case 0b100010: /* BTI c */
14125 /* Not compatible with btype == 3 */
14127 case 0b100100: /* BTI j */
14128 /* Not compatible with btype == 2 */
14130 case 0b100110: /* BTI jc */
14131 /* Compatible with any btype. */
14135 switch (insn
& 0xffe0001fu
) {
14136 case 0xd4200000u
: /* BRK */
14137 case 0xd4400000u
: /* HLT */
14138 /* Give priority to the breakpoint exception. */
14145 /* C3.1 A64 instruction index by encoding */
14146 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14150 s
->pc_curr
= s
->base
.pc_next
;
14151 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14153 s
->base
.pc_next
+= 4;
14155 s
->fp_access_checked
= false;
14157 if (dc_isar_feature(aa64_bti
, s
)) {
14158 if (s
->base
.num_insns
== 1) {
14160 * At the first insn of the TB, compute s->guarded_page.
14161 * We delayed computing this until successfully reading
14162 * the first insn of the TB, above. This (mostly) ensures
14163 * that the softmmu tlb entry has been populated, and the
14164 * page table GP bit is available.
14166 * Note that we need to compute this even if btype == 0,
14167 * because this value is used for BR instructions later
14168 * where ENV is not available.
14170 s
->guarded_page
= is_guarded_page(env
, s
);
14172 /* First insn can have btype set to non-zero. */
14173 tcg_debug_assert(s
->btype
>= 0);
14176 * Note that the Branch Target Exception has fairly high
14177 * priority -- below debugging exceptions but above most
14178 * everything else. This allows us to handle this now
14179 * instead of waiting until the insn is otherwise decoded.
14183 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14184 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14185 syn_btitrap(s
->btype
),
14186 default_exception_el(s
));
14190 /* Not the first insn: btype must be 0. */
14191 tcg_debug_assert(s
->btype
== 0);
14195 switch (extract32(insn
, 25, 4)) {
14196 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14197 unallocated_encoding(s
);
14200 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14201 unallocated_encoding(s
);
14204 case 0x8: case 0x9: /* Data processing - immediate */
14205 disas_data_proc_imm(s
, insn
);
14207 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14208 disas_b_exc_sys(s
, insn
);
14213 case 0xe: /* Loads and stores */
14214 disas_ldst(s
, insn
);
14217 case 0xd: /* Data processing - register */
14218 disas_data_proc_reg(s
, insn
);
14221 case 0xf: /* Data processing - SIMD and floating point */
14222 disas_data_proc_simd_fp(s
, insn
);
14225 assert(FALSE
); /* all 15 cases should be handled above */
14229 /* if we allocated any temporaries, free them here */
14233 * After execution of most insns, btype is reset to 0.
14234 * Note that we set btype == -1 when the insn sets btype.
14236 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14241 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14244 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14245 CPUARMState
*env
= cpu
->env_ptr
;
14246 ARMCPU
*arm_cpu
= env_archcpu(env
);
14247 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14248 int bound
, core_mmu_idx
;
14250 dc
->isar
= &arm_cpu
->isar
;
14254 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14255 * there is no secure EL1, so we route exceptions to EL3.
14257 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14258 !arm_el_is_aa64(env
, 3);
14261 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14262 dc
->condexec_mask
= 0;
14263 dc
->condexec_cond
= 0;
14264 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14265 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14266 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14267 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14268 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14269 #if !defined(CONFIG_USER_ONLY)
14270 dc
->user
= (dc
->current_el
== 0);
14272 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14273 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14274 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14275 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14276 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14277 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14278 dc
->unpriv
= FIELD_EX32(tb_flags
, TBFLAG_A64
, UNPRIV
);
14280 dc
->vec_stride
= 0;
14281 dc
->cp_regs
= arm_cpu
->cp_regs
;
14282 dc
->features
= env
->features
;
14284 /* Single step state. The code-generation logic here is:
14286 * generate code with no special handling for single-stepping (except
14287 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14288 * this happens anyway because those changes are all system register or
14290 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14291 * emit code for one insn
14292 * emit code to clear PSTATE.SS
14293 * emit code to generate software step exception for completed step
14294 * end TB (as usual for having generated an exception)
14295 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14296 * emit code to generate a software step exception
14299 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14300 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14301 dc
->is_ldex
= false;
14302 dc
->debug_target_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
14304 /* Bound the number of insns to execute to those left on the page. */
14305 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14307 /* If architectural single step active, limit to 1. */
14308 if (dc
->ss_active
) {
14311 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14313 init_tmp_a64_array(dc
);
14316 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14320 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14322 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14324 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14325 dc
->insn_start
= tcg_last_op();
14328 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14329 const CPUBreakpoint
*bp
)
14331 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14333 if (bp
->flags
& BP_CPU
) {
14334 gen_a64_set_pc_im(dc
->base
.pc_next
);
14335 gen_helper_check_breakpoints(cpu_env
);
14336 /* End the TB early; it likely won't be executed */
14337 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14339 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14340 /* The address covered by the breakpoint must be
14341 included in [tb->pc, tb->pc + tb->size) in order
14342 to for it to be properly cleared -- thus we
14343 increment the PC here so that the logic setting
14344 tb->size below does the right thing. */
14345 dc
->base
.pc_next
+= 4;
14346 dc
->base
.is_jmp
= DISAS_NORETURN
;
14352 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14354 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14355 CPUARMState
*env
= cpu
->env_ptr
;
14357 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14358 /* Singlestep state is Active-pending.
14359 * If we're in this state at the start of a TB then either
14360 * a) we just took an exception to an EL which is being debugged
14361 * and this is the first insn in the exception handler
14362 * b) debug exceptions were masked and we just unmasked them
14363 * without changing EL (eg by clearing PSTATE.D)
14364 * In either case we're going to take a swstep exception in the
14365 * "did not step an insn" case, and so the syndrome ISV and EX
14366 * bits should be zero.
14368 assert(dc
->base
.num_insns
== 1);
14369 gen_swstep_exception(dc
, 0, 0);
14370 dc
->base
.is_jmp
= DISAS_NORETURN
;
14372 disas_a64_insn(env
, dc
);
14375 translator_loop_temp_check(&dc
->base
);
14378 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14380 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14382 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14383 /* Note that this means single stepping WFI doesn't halt the CPU.
14384 * For conditional branch insns this is harmless unreachable code as
14385 * gen_goto_tb() has already handled emitting the debug exception
14386 * (and thus a tb-jump is not possible when singlestepping).
14388 switch (dc
->base
.is_jmp
) {
14390 gen_a64_set_pc_im(dc
->base
.pc_next
);
14394 if (dc
->base
.singlestep_enabled
) {
14395 gen_exception_internal(EXCP_DEBUG
);
14397 gen_step_complete_exception(dc
);
14400 case DISAS_NORETURN
:
14404 switch (dc
->base
.is_jmp
) {
14406 case DISAS_TOO_MANY
:
14407 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14411 gen_a64_set_pc_im(dc
->base
.pc_next
);
14414 tcg_gen_exit_tb(NULL
, 0);
14417 tcg_gen_lookup_and_goto_ptr();
14419 case DISAS_NORETURN
:
14423 gen_a64_set_pc_im(dc
->base
.pc_next
);
14424 gen_helper_wfe(cpu_env
);
14427 gen_a64_set_pc_im(dc
->base
.pc_next
);
14428 gen_helper_yield(cpu_env
);
14432 /* This is a special case because we don't want to just halt the CPU
14433 * if trying to debug across a WFI.
14435 TCGv_i32 tmp
= tcg_const_i32(4);
14437 gen_a64_set_pc_im(dc
->base
.pc_next
);
14438 gen_helper_wfi(cpu_env
, tmp
);
14439 tcg_temp_free_i32(tmp
);
14440 /* The helper doesn't necessarily throw an exception, but we
14441 * must go back to the main loop to check for interrupts anyway.
14443 tcg_gen_exit_tb(NULL
, 0);
14450 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14453 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14455 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14456 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14459 const TranslatorOps aarch64_translator_ops
= {
14460 .init_disas_context
= aarch64_tr_init_disas_context
,
14461 .tb_start
= aarch64_tr_tb_start
,
14462 .insn_start
= aarch64_tr_insn_start
,
14463 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14464 .translate_insn
= aarch64_tr_translate_insn
,
14465 .tb_stop
= aarch64_tr_tb_stop
,
14466 .disas_log
= aarch64_tr_disas_log
,