target/arm: Create gen_gvec_{u,s}{rshr,rsra}
commit6ccd48d4ea244c1c46a24dfa50bfb547f11422dd
authorRichard Henderson <richard.henderson@linaro.org>
Wed, 13 May 2020 16:32:31 +0000 (13 09:32 -0700)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 14 May 2020 14:03:08 +0000 (14 15:03 +0100)
tree85b28fdda20fdc18b125f119b48255161df4b7a8
parent631e565450c483e0622eec3d8b61d7fa41d16bca
target/arm: Create gen_gvec_{u,s}{rshr,rsra}

Create vectorized versions of handle_shri_with_rndacc
for shift+round and shift+round+accumulate.  Add out-of-line
helpers in preparation for longer vector lengths from SVE.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200513163245.17915-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/helper.h
target/arm/translate-a64.c
target/arm/translate.c
target/arm/translate.h
target/arm/vec_helper.c