hw/arm/integratorcp.c

   1 /*
   2  * ARM Integrator CP System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qapi/error.h"
  12 #include "qemu-common.h"
  13 #include "cpu.h"
  14 #include "hw/sysbus.h"
  15 #include "hw/devices.h"
  16 #include "hw/boards.h"
  17 #include "hw/arm/arm.h"
  18 #include "hw/misc/arm_integrator_debug.h"
  19 #include "net/net.h"
  20 #include "exec/address-spaces.h"
  21 #include "sysemu/sysemu.h"
  22 #include "qemu/error-report.h"
  23
  24 #define TYPE_INTEGRATOR_CM "integrator_core"
  25 #define INTEGRATOR_CM(obj) \
  26     OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
  27
  28 typedef struct IntegratorCMState {
  29     /*< private >*/
  30     SysBusDevice parent_obj;
  31     /*< public >*/
  32
  33     MemoryRegion iomem;
  34     uint32_t memsz;
  35     MemoryRegion flash;
  36     uint32_t cm_osc;
  37     uint32_t cm_ctrl;
  38     uint32_t cm_lock;
  39     uint32_t cm_auxosc;
  40     uint32_t cm_sdram;
  41     uint32_t cm_init;
  42     uint32_t cm_flags;
  43     uint32_t cm_nvflags;
  44     uint32_t cm_refcnt_offset;
  45     uint32_t int_level;
  46     uint32_t irq_enabled;
  47     uint32_t fiq_enabled;
  48 } IntegratorCMState;
  49
  50 static uint8_t integrator_spd[128] = {
  51    128, 8, 4, 11, 9, 1, 64, 0,  2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
  52    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
  53 };
  54
  55 static uint64_t integratorcm_read(void *opaque, hwaddr offset,
  56                                   unsigned size)
  57 {
  58     IntegratorCMState *s = opaque;
  59     if (offset >= 0x100 && offset < 0x200) {
  60         /* CM_SPD */
  61         if (offset >= 0x180)
  62             return 0;
  63         return integrator_spd[offset >> 2];
  64     }
  65     switch (offset >> 2) {
  66     case 0: /* CM_ID */
  67         return 0x411a3001;
  68     case 1: /* CM_PROC */
  69         return 0;
  70     case 2: /* CM_OSC */
  71         return s->cm_osc;
  72     case 3: /* CM_CTRL */
  73         return s->cm_ctrl;
  74     case 4: /* CM_STAT */
  75         return 0x00100000;
  76     case 5: /* CM_LOCK */
  77         if (s->cm_lock == 0xa05f) {
  78             return 0x1a05f;
  79         } else {
  80             return s->cm_lock;
  81         }
  82     case 6: /* CM_LMBUSCNT */
  83         /* ??? High frequency timer.  */
  84         hw_error("integratorcm_read: CM_LMBUSCNT");
  85     case 7: /* CM_AUXOSC */
  86         return s->cm_auxosc;
  87     case 8: /* CM_SDRAM */
  88         return s->cm_sdram;
  89     case 9: /* CM_INIT */
  90         return s->cm_init;
  91     case 10: /* CM_REFCNT */
  92         /* This register, CM_REFCNT, provides a 32-bit count value.
  93          * The count increments at the fixed reference clock frequency of 24MHz
  94          * and can be used as a real-time counter.
  95          */
  96         return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
  97                                   1000) - s->cm_refcnt_offset;
  98     case 12: /* CM_FLAGS */
  99         return s->cm_flags;
 100     case 14: /* CM_NVFLAGS */
 101         return s->cm_nvflags;
 102     case 16: /* CM_IRQ_STAT */
 103         return s->int_level & s->irq_enabled;
 104     case 17: /* CM_IRQ_RSTAT */
 105         return s->int_level;
 106     case 18: /* CM_IRQ_ENSET */
 107         return s->irq_enabled;
 108     case 20: /* CM_SOFT_INTSET */
 109         return s->int_level & 1;
 110     case 24: /* CM_FIQ_STAT */
 111         return s->int_level & s->fiq_enabled;
 112     case 25: /* CM_FIQ_RSTAT */
 113         return s->int_level;
 114     case 26: /* CM_FIQ_ENSET */
 115         return s->fiq_enabled;
 116     case 32: /* CM_VOLTAGE_CTL0 */
 117     case 33: /* CM_VOLTAGE_CTL1 */
 118     case 34: /* CM_VOLTAGE_CTL2 */
 119     case 35: /* CM_VOLTAGE_CTL3 */
 120         /* ??? Voltage control unimplemented.  */
 121         return 0;
 122     default:
 123         hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
 124                  (int)offset);
 125         return 0;
 126     }
 127 }
 128
 129 static void integratorcm_do_remap(IntegratorCMState *s)
 130 {
 131     /* Sync memory region state with CM_CTRL REMAP bit:
 132      * bit 0 => flash at address 0; bit 1 => RAM
 133      */
 134     memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
 135 }
 136
 137 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value)
 138 {
 139     if (value & 8) {
 140         qemu_system_reset_request();
 141     }
 142     if ((s->cm_ctrl ^ value) & 1) {
 143         /* (value & 1) != 0 means the green "MISC LED" is lit.
 144          * We don't have any nice place to display LEDs. printf is a bad
 145          * idea because Linux uses the LED as a heartbeat and the output
 146          * will swamp anything else on the terminal.
 147          */
 148     }
 149     /* Note that the RESET bit [3] always reads as zero */
 150     s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
 151     integratorcm_do_remap(s);
 152 }
 153
 154 static void integratorcm_update(IntegratorCMState *s)
 155 {
 156     /* ??? The CPU irq/fiq is raised when either the core module or base PIC
 157        are active.  */
 158     if (s->int_level & (s->irq_enabled | s->fiq_enabled))
 159         hw_error("Core module interrupt\n");
 160 }
 161
 162 static void integratorcm_write(void *opaque, hwaddr offset,
 163                                uint64_t value, unsigned size)
 164 {
 165     IntegratorCMState *s = opaque;
 166     switch (offset >> 2) {
 167     case 2: /* CM_OSC */
 168         if (s->cm_lock == 0xa05f)
 169             s->cm_osc = value;
 170         break;
 171     case 3: /* CM_CTRL */
 172         integratorcm_set_ctrl(s, value);
 173         break;
 174     case 5: /* CM_LOCK */
 175         s->cm_lock = value & 0xffff;
 176         break;
 177     case 7: /* CM_AUXOSC */
 178         if (s->cm_lock == 0xa05f)
 179             s->cm_auxosc = value;
 180         break;
 181     case 8: /* CM_SDRAM */
 182         s->cm_sdram = value;
 183         break;
 184     case 9: /* CM_INIT */
 185         /* ??? This can change the memory bus frequency.  */
 186         s->cm_init = value;
 187         break;
 188     case 12: /* CM_FLAGSS */
 189         s->cm_flags |= value;
 190         break;
 191     case 13: /* CM_FLAGSC */
 192         s->cm_flags &= ~value;
 193         break;
 194     case 14: /* CM_NVFLAGSS */
 195         s->cm_nvflags |= value;
 196         break;
 197     case 15: /* CM_NVFLAGSS */
 198         s->cm_nvflags &= ~value;
 199         break;
 200     case 18: /* CM_IRQ_ENSET */
 201         s->irq_enabled |= value;
 202         integratorcm_update(s);
 203         break;
 204     case 19: /* CM_IRQ_ENCLR */
 205         s->irq_enabled &= ~value;
 206         integratorcm_update(s);
 207         break;
 208     case 20: /* CM_SOFT_INTSET */
 209         s->int_level |= (value & 1);
 210         integratorcm_update(s);
 211         break;
 212     case 21: /* CM_SOFT_INTCLR */
 213         s->int_level &= ~(value & 1);
 214         integratorcm_update(s);
 215         break;
 216     case 26: /* CM_FIQ_ENSET */
 217         s->fiq_enabled |= value;
 218         integratorcm_update(s);
 219         break;
 220     case 27: /* CM_FIQ_ENCLR */
 221         s->fiq_enabled &= ~value;
 222         integratorcm_update(s);
 223         break;
 224     case 32: /* CM_VOLTAGE_CTL0 */
 225     case 33: /* CM_VOLTAGE_CTL1 */
 226     case 34: /* CM_VOLTAGE_CTL2 */
 227     case 35: /* CM_VOLTAGE_CTL3 */
 228         /* ??? Voltage control unimplemented.  */
 229         break;
 230     default:
 231         hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
 232                  (int)offset);
 233         break;
 234     }
 235 }
 236
 237 /* Integrator/CM control registers.  */
 238
 239 static const MemoryRegionOps integratorcm_ops = {
 240     .read = integratorcm_read,
 241     .write = integratorcm_write,
 242     .endianness = DEVICE_NATIVE_ENDIAN,
 243 };
 244
 245 static void integratorcm_init(Object *obj)
 246 {
 247     IntegratorCMState *s = INTEGRATOR_CM(obj);
 248     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 249
 250     s->cm_osc = 0x01000048;
 251     /* ??? What should the high bits of this value be?  */
 252     s->cm_auxosc = 0x0007feff;
 253     s->cm_sdram = 0x00011122;
 254     if (s->memsz >= 256) {
 255         integrator_spd[31] = 64;
 256         s->cm_sdram |= 0x10;
 257     } else if (s->memsz >= 128) {
 258         integrator_spd[31] = 32;
 259         s->cm_sdram |= 0x0c;
 260     } else if (s->memsz >= 64) {
 261         integrator_spd[31] = 16;
 262         s->cm_sdram |= 0x08;
 263     } else if (s->memsz >= 32) {
 264         integrator_spd[31] = 4;
 265         s->cm_sdram |= 0x04;
 266     } else {
 267         integrator_spd[31] = 2;
 268     }
 269     memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
 270     s->cm_init = 0x00000112;
 271     s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
 272                                    1000);
 273     memory_region_init_ram(&s->flash, obj, "integrator.flash", 0x100000,
 274                            &error_fatal);
 275     vmstate_register_ram_global(&s->flash);
 276
 277     memory_region_init_io(&s->iomem, obj, &integratorcm_ops, s,
 278                           "integratorcm", 0x00800000);
 279     sysbus_init_mmio(dev, &s->iomem);
 280
 281     integratorcm_do_remap(s);
 282     /* ??? Save/restore.  */
 283 }
 284
 285 /* Integrator/CP hardware emulation.  */
 286 /* Primary interrupt controller.  */
 287
 288 #define TYPE_INTEGRATOR_PIC "integrator_pic"
 289 #define INTEGRATOR_PIC(obj) \
 290    OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
 291
 292 typedef struct icp_pic_state {
 293     /*< private >*/
 294     SysBusDevice parent_obj;
 295     /*< public >*/
 296
 297     MemoryRegion iomem;
 298     uint32_t level;
 299     uint32_t irq_enabled;
 300     uint32_t fiq_enabled;
 301     qemu_irq parent_irq;
 302     qemu_irq parent_fiq;
 303 } icp_pic_state;
 304
 305 static void icp_pic_update(icp_pic_state *s)
 306 {
 307     uint32_t flags;
 308
 309     flags = (s->level & s->irq_enabled);
 310     qemu_set_irq(s->parent_irq, flags != 0);
 311     flags = (s->level & s->fiq_enabled);
 312     qemu_set_irq(s->parent_fiq, flags != 0);
 313 }
 314
 315 static void icp_pic_set_irq(void *opaque, int irq, int level)
 316 {
 317     icp_pic_state *s = (icp_pic_state *)opaque;
 318     if (level)
 319         s->level |= 1 << irq;
 320     else
 321         s->level &= ~(1 << irq);
 322     icp_pic_update(s);
 323 }
 324
 325 static uint64_t icp_pic_read(void *opaque, hwaddr offset,
 326                              unsigned size)
 327 {
 328     icp_pic_state *s = (icp_pic_state *)opaque;
 329
 330     switch (offset >> 2) {
 331     case 0: /* IRQ_STATUS */
 332         return s->level & s->irq_enabled;
 333     case 1: /* IRQ_RAWSTAT */
 334         return s->level;
 335     case 2: /* IRQ_ENABLESET */
 336         return s->irq_enabled;
 337     case 4: /* INT_SOFTSET */
 338         return s->level & 1;
 339     case 8: /* FRQ_STATUS */
 340         return s->level & s->fiq_enabled;
 341     case 9: /* FRQ_RAWSTAT */
 342         return s->level;
 343     case 10: /* FRQ_ENABLESET */
 344         return s->fiq_enabled;
 345     case 3: /* IRQ_ENABLECLR */
 346     case 5: /* INT_SOFTCLR */
 347     case 11: /* FRQ_ENABLECLR */
 348     default:
 349         printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
 350         return 0;
 351     }
 352 }
 353
 354 static void icp_pic_write(void *opaque, hwaddr offset,
 355                           uint64_t value, unsigned size)
 356 {
 357     icp_pic_state *s = (icp_pic_state *)opaque;
 358
 359     switch (offset >> 2) {
 360     case 2: /* IRQ_ENABLESET */
 361         s->irq_enabled |= value;
 362         break;
 363     case 3: /* IRQ_ENABLECLR */
 364         s->irq_enabled &= ~value;
 365         break;
 366     case 4: /* INT_SOFTSET */
 367         if (value & 1)
 368             icp_pic_set_irq(s, 0, 1);
 369         break;
 370     case 5: /* INT_SOFTCLR */
 371         if (value & 1)
 372             icp_pic_set_irq(s, 0, 0);
 373         break;
 374     case 10: /* FRQ_ENABLESET */
 375         s->fiq_enabled |= value;
 376         break;
 377     case 11: /* FRQ_ENABLECLR */
 378         s->fiq_enabled &= ~value;
 379         break;
 380     case 0: /* IRQ_STATUS */
 381     case 1: /* IRQ_RAWSTAT */
 382     case 8: /* FRQ_STATUS */
 383     case 9: /* FRQ_RAWSTAT */
 384     default:
 385         printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
 386         return;
 387     }
 388     icp_pic_update(s);
 389 }
 390
 391 static const MemoryRegionOps icp_pic_ops = {
 392     .read = icp_pic_read,
 393     .write = icp_pic_write,
 394     .endianness = DEVICE_NATIVE_ENDIAN,
 395 };
 396
 397 static void icp_pic_init(Object *obj)
 398 {
 399     DeviceState *dev = DEVICE(obj);
 400     icp_pic_state *s = INTEGRATOR_PIC(obj);
 401     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 402
 403     qdev_init_gpio_in(dev, icp_pic_set_irq, 32);
 404     sysbus_init_irq(sbd, &s->parent_irq);
 405     sysbus_init_irq(sbd, &s->parent_fiq);
 406     memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s,
 407                           "icp-pic", 0x00800000);
 408     sysbus_init_mmio(sbd, &s->iomem);
 409 }
 410
 411 /* CP control registers.  */
 412
 413 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
 414 #define ICP_CONTROL_REGS(obj) \
 415     OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS)
 416
 417 typedef struct ICPCtrlRegsState {
 418     /*< private >*/
 419     SysBusDevice parent_obj;
 420     /*< public >*/
 421
 422     MemoryRegion iomem;
 423
 424     qemu_irq mmc_irq;
 425     uint32_t intreg_state;
 426 } ICPCtrlRegsState;
 427
 428 #define ICP_GPIO_MMC_WPROT      "mmc-wprot"
 429 #define ICP_GPIO_MMC_CARDIN     "mmc-cardin"
 430
 431 #define ICP_INTREG_WPROT        (1 << 0)
 432 #define ICP_INTREG_CARDIN       (1 << 3)
 433
 434 static uint64_t icp_control_read(void *opaque, hwaddr offset,
 435                                  unsigned size)
 436 {
 437     ICPCtrlRegsState *s = opaque;
 438
 439     switch (offset >> 2) {
 440     case 0: /* CP_IDFIELD */
 441         return 0x41034003;
 442     case 1: /* CP_FLASHPROG */
 443         return 0;
 444     case 2: /* CP_INTREG */
 445         return s->intreg_state;
 446     case 3: /* CP_DECODE */
 447         return 0x11;
 448     default:
 449         hw_error("icp_control_read: Bad offset %x\n", (int)offset);
 450         return 0;
 451     }
 452 }
 453
 454 static void icp_control_write(void *opaque, hwaddr offset,
 455                           uint64_t value, unsigned size)
 456 {
 457     ICPCtrlRegsState *s = opaque;
 458
 459     switch (offset >> 2) {
 460     case 2: /* CP_INTREG */
 461         s->intreg_state &= ~(value & ICP_INTREG_CARDIN);
 462         qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN));
 463         break;
 464     case 1: /* CP_FLASHPROG */
 465     case 3: /* CP_DECODE */
 466         /* Nothing interesting implemented yet.  */
 467         break;
 468     default:
 469         hw_error("icp_control_write: Bad offset %x\n", (int)offset);
 470     }
 471 }
 472
 473 static const MemoryRegionOps icp_control_ops = {
 474     .read = icp_control_read,
 475     .write = icp_control_write,
 476     .endianness = DEVICE_NATIVE_ENDIAN,
 477 };
 478
 479 static void icp_control_mmc_wprot(void *opaque, int line, int level)
 480 {
 481     ICPCtrlRegsState *s = opaque;
 482
 483     s->intreg_state &= ~ICP_INTREG_WPROT;
 484     if (level) {
 485         s->intreg_state |= ICP_INTREG_WPROT;
 486     }
 487 }
 488
 489 static void icp_control_mmc_cardin(void *opaque, int line, int level)
 490 {
 491     ICPCtrlRegsState *s = opaque;
 492
 493     /* line is released by writing to CP_INTREG */
 494     if (level) {
 495         s->intreg_state |= ICP_INTREG_CARDIN;
 496         qemu_set_irq(s->mmc_irq, 1);
 497     }
 498 }
 499
 500 static void icp_control_init(Object *obj)
 501 {
 502     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 503     ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj);
 504     DeviceState *dev = DEVICE(obj);
 505
 506     memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s,
 507                           "icp_ctrl_regs", 0x00800000);
 508     sysbus_init_mmio(sbd, &s->iomem);
 509
 510     qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1);
 511     qdev_init_gpio_in_named(dev, icp_control_mmc_cardin,
 512                             ICP_GPIO_MMC_CARDIN, 1);
 513     sysbus_init_irq(sbd, &s->mmc_irq);
 514 }
 515
 516
 517 /* Board init.  */
 518
 519 static struct arm_boot_info integrator_binfo = {
 520     .loader_start = 0x0,
 521     .board_id = 0x113,
 522 };
 523
 524 static void integratorcp_init(MachineState *machine)
 525 {
 526     ram_addr_t ram_size = machine->ram_size;
 527     const char *cpu_model = machine->cpu_model;
 528     const char *kernel_filename = machine->kernel_filename;
 529     const char *kernel_cmdline = machine->kernel_cmdline;
 530     const char *initrd_filename = machine->initrd_filename;
 531     ObjectClass *cpu_oc;
 532     Object *cpuobj;
 533     ARMCPU *cpu;
 534     MemoryRegion *address_space_mem = get_system_memory();
 535     MemoryRegion *ram = g_new(MemoryRegion, 1);
 536     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
 537     qemu_irq pic[32];
 538     DeviceState *dev, *sic, *icp;
 539     int i;
 540
 541     if (!cpu_model) {
 542         cpu_model = "arm926";
 543     }
 544
 545     cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 546     if (!cpu_oc) {
 547         fprintf(stderr, "Unable to find CPU definition\n");
 548         exit(1);
 549     }
 550
 551     cpuobj = object_new(object_class_get_name(cpu_oc));
 552
 553     /* By default ARM1176 CPUs have EL3 enabled.  This board does not
 554      * currently support EL3 so the CPU EL3 property is disabled before
 555      * realization.
 556      */
 557     if (object_property_find(cpuobj, "has_el3", NULL)) {
 558         object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
 559     }
 560
 561     object_property_set_bool(cpuobj, true, "realized", &error_fatal);
 562
 563     cpu = ARM_CPU(cpuobj);
 564
 565     memory_region_allocate_system_memory(ram, NULL, "integrator.ram",
 566                                          ram_size);
 567     /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */
 568     /* ??? RAM should repeat to fill physical memory space.  */
 569     /* SDRAM at address zero*/
 570     memory_region_add_subregion(address_space_mem, 0, ram);
 571     /* And again at address 0x80000000 */
 572     memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
 573     memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
 574
 575     dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
 576     qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
 577     qdev_init_nofail(dev);
 578     sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
 579
 580     dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
 581                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
 582                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
 583                                 NULL);
 584     for (i = 0; i < 32; i++) {
 585         pic[i] = qdev_get_gpio_in(dev, i);
 586     }
 587     sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]);
 588     sysbus_create_varargs("integrator_pit", 0x13000000,
 589                           pic[5], pic[6], pic[7], NULL);
 590     sysbus_create_simple("pl031", 0x15000000, pic[8]);
 591     sysbus_create_simple("pl011", 0x16000000, pic[1]);
 592     sysbus_create_simple("pl011", 0x17000000, pic[2]);
 593     icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000,
 594                                qdev_get_gpio_in(sic, 3));
 595     sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
 596     sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
 597     sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
 598
 599     dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
 600     qdev_connect_gpio_out(dev, 0,
 601                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
 602     qdev_connect_gpio_out(dev, 1,
 603                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
 604
 605     if (nd_table[0].used)
 606         smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
 607
 608     sysbus_create_simple("pl110", 0xc0000000, pic[22]);
 609
 610     integrator_binfo.ram_size = ram_size;
 611     integrator_binfo.kernel_filename = kernel_filename;
 612     integrator_binfo.kernel_cmdline = kernel_cmdline;
 613     integrator_binfo.initrd_filename = initrd_filename;
 614     arm_load_kernel(cpu, &integrator_binfo);
 615 }
 616
 617 static void integratorcp_machine_init(MachineClass *mc)
 618 {
 619     mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
 620     mc->init = integratorcp_init;
 621 }
 622
 623 DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
 624
 625 static Property core_properties[] = {
 626     DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
 627     DEFINE_PROP_END_OF_LIST(),
 628 };
 629
 630 static void core_class_init(ObjectClass *klass, void *data)
 631 {
 632     DeviceClass *dc = DEVICE_CLASS(klass);
 633
 634     dc->props = core_properties;
 635 }
 636
 637 static const TypeInfo core_info = {
 638     .name          = TYPE_INTEGRATOR_CM,
 639     .parent        = TYPE_SYS_BUS_DEVICE,
 640     .instance_size = sizeof(IntegratorCMState),
 641     .instance_init = integratorcm_init,
 642     .class_init    = core_class_init,
 643 };
 644
 645 static const TypeInfo icp_pic_info = {
 646     .name          = TYPE_INTEGRATOR_PIC,
 647     .parent        = TYPE_SYS_BUS_DEVICE,
 648     .instance_size = sizeof(icp_pic_state),
 649     .instance_init = icp_pic_init,
 650 };
 651
 652 static const TypeInfo icp_ctrl_regs_info = {
 653     .name          = TYPE_ICP_CONTROL_REGS,
 654     .parent        = TYPE_SYS_BUS_DEVICE,
 655     .instance_size = sizeof(ICPCtrlRegsState),
 656     .instance_init = icp_control_init,
 657 };
 658
 659 static void integratorcp_register_types(void)
 660 {
 661     type_register_static(&icp_pic_info);
 662     type_register_static(&core_info);
 663     type_register_static(&icp_ctrl_regs_info);
 664 }
 665
 666 type_init(integratorcp_register_types)