2 * Helpers for loads and stores
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
31 //#define DEBUG_UNASSIGNED
33 //#define DEBUG_CACHE_CONTROL
36 #define DPRINTF_MMU(fmt, ...) \
37 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
39 #define DPRINTF_MMU(fmt, ...) do {} while (0)
43 #define DPRINTF_MXCC(fmt, ...) \
44 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
46 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
50 #define DPRINTF_ASI(fmt, ...) \
51 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
54 #ifdef DEBUG_CACHE_CONTROL
55 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
56 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
58 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
63 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
65 #define AM_CHECK(env1) (1)
69 #define QT0 (env->qt0)
70 #define QT1 (env->qt1)
72 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
73 /* Calculates TSB pointer value for fault page size
74 * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers
75 * UA2005 holds the page size configuration in mmu_ctx registers */
76 static uint64_t ultrasparc_tsb_pointer(CPUSPARCState
*env
,
77 const SparcV9MMU
*mmu
, const int idx
)
79 uint64_t tsb_register
;
81 if (cpu_has_hypervisor(env
)) {
83 int ctx
= mmu
->tag_access
& 0x1fffULL
;
84 uint64_t ctx_register
= mmu
->sun4v_ctx_config
[ctx
? 1 : 0];
86 tsb_index
|= ctx
? 2 : 0;
87 page_size
= idx
? ctx_register
>> 8 : ctx_register
;
89 tsb_register
= mmu
->sun4v_tsb_pointers
[tsb_index
];
92 tsb_register
= mmu
->tsb
;
94 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
95 int tsb_size
= tsb_register
& 0xf;
97 uint64_t tsb_base_mask
= (~0x1fffULL
) << tsb_size
;
99 /* move va bits to correct position,
100 * the context bits will be masked out later */
101 uint64_t va
= mmu
->tag_access
>> (3 * page_size
+ 9);
103 /* calculate tsb_base mask and adjust va if split is in use */
106 va
&= ~(1ULL << (13 + tsb_size
));
108 va
|= (1ULL << (13 + tsb_size
));
113 return ((tsb_register
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
116 /* Calculates tag target register value by reordering bits
117 in tag access register */
118 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
120 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
123 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
124 uint64_t tlb_tag
, uint64_t tlb_tte
,
127 target_ulong mask
, size
, va
, offset
;
129 /* flush page range if translation is valid */
130 if (TTE_IS_VALID(tlb
->tte
)) {
131 CPUState
*cs
= env_cpu(env
);
133 size
= 8192ULL << 3 * TTE_PGSIZE(tlb
->tte
);
136 va
= tlb
->tag
& mask
;
138 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
139 tlb_flush_page(cs
, va
+ offset
);
147 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
148 const char *strmmu
, CPUSPARCState
*env1
)
154 int is_demap_context
= (demap_addr
>> 6) & 1;
157 switch ((demap_addr
>> 4) & 3) {
158 case 0: /* primary */
159 context
= env1
->dmmu
.mmu_primary_context
;
161 case 1: /* secondary */
162 context
= env1
->dmmu
.mmu_secondary_context
;
164 case 2: /* nucleus */
167 case 3: /* reserved */
172 for (i
= 0; i
< 64; i
++) {
173 if (TTE_IS_VALID(tlb
[i
].tte
)) {
175 if (is_demap_context
) {
176 /* will remove non-global entries matching context value */
177 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
178 !tlb_compare_context(&tlb
[i
], context
)) {
183 will remove any entry matching VA */
184 mask
= 0xffffffffffffe000ULL
;
185 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
187 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
191 /* entry should be global or matching context value */
192 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
193 !tlb_compare_context(&tlb
[i
], context
)) {
198 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
200 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
207 static uint64_t sun4v_tte_to_sun4u(CPUSPARCState
*env
, uint64_t tag
,
211 if (!(cpu_has_hypervisor(env
) && (tag
& TLB_UST1_IS_SUN4V_BIT
))) {
212 /* is already in the sun4u format */
215 sun4u_tte
= TTE_PA(sun4v_tte
) | (sun4v_tte
& TTE_VALID_BIT
);
216 sun4u_tte
|= (sun4v_tte
& 3ULL) << 61; /* TTE_PGSIZE */
217 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_NFO_BIT_UA2005
, TTE_NFO_BIT
);
218 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_USED_BIT_UA2005
, TTE_USED_BIT
);
219 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_W_OK_BIT_UA2005
, TTE_W_OK_BIT
);
220 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_SIDEEFFECT_BIT_UA2005
,
222 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_PRIV_BIT_UA2005
, TTE_PRIV_BIT
);
223 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_LOCKED_BIT_UA2005
, TTE_LOCKED_BIT
);
227 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
228 uint64_t tlb_tag
, uint64_t tlb_tte
,
229 const char *strmmu
, CPUSPARCState
*env1
,
232 unsigned int i
, replace_used
;
234 tlb_tte
= sun4v_tte_to_sun4u(env1
, addr
, tlb_tte
);
235 if (cpu_has_hypervisor(env1
)) {
236 uint64_t new_vaddr
= tlb_tag
& ~0x1fffULL
;
237 uint64_t new_size
= 8192ULL << 3 * TTE_PGSIZE(tlb_tte
);
238 uint32_t new_ctx
= tlb_tag
& 0x1fffU
;
239 for (i
= 0; i
< 64; i
++) {
240 uint32_t ctx
= tlb
[i
].tag
& 0x1fffU
;
241 /* check if new mapping overlaps an existing one */
242 if (new_ctx
== ctx
) {
243 uint64_t vaddr
= tlb
[i
].tag
& ~0x1fffULL
;
244 uint64_t size
= 8192ULL << 3 * TTE_PGSIZE(tlb
[i
].tte
);
245 if (new_vaddr
== vaddr
246 || (new_vaddr
< vaddr
+ size
247 && vaddr
< new_vaddr
+ new_size
)) {
248 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i
, vaddr
,
250 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
257 /* Try replacing invalid entry */
258 for (i
= 0; i
< 64; i
++) {
259 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
260 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
262 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
269 /* All entries are valid, try replacing unlocked entry */
271 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
273 /* Used entries are not replaced on first pass */
275 for (i
= 0; i
< 64; i
++) {
276 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
278 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
280 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
281 strmmu
, (replace_used
? "used" : "unused"), i
);
288 /* Now reset used bit and search for unused entries again */
290 for (i
= 0; i
< 64; i
++) {
291 TTE_SET_UNUSED(tlb
[i
].tte
);
296 DPRINTF_MMU("%s lru replacement: no free entries available, "
297 "replacing the last one\n", strmmu
);
299 /* corner case: the last entry is replaced anyway */
300 replace_tlb_entry(&tlb
[63], tlb_tag
, tlb_tte
, env1
);
305 #ifdef TARGET_SPARC64
306 /* returns true if access using this ASI is to have address translated by MMU
307 otherwise access is to raw physical address */
308 /* TODO: check sparc32 bits */
309 static inline int is_translating_asi(int asi
)
311 /* Ultrasparc IIi translating asi
312 - note this list is defined by cpu implementation
329 static inline target_ulong
address_mask(CPUSPARCState
*env1
, target_ulong addr
)
331 if (AM_CHECK(env1
)) {
332 addr
&= 0xffffffffULL
;
337 static inline target_ulong
asi_address_mask(CPUSPARCState
*env
,
338 int asi
, target_ulong addr
)
340 if (is_translating_asi(asi
)) {
341 addr
= address_mask(env
, addr
);
346 #ifndef CONFIG_USER_ONLY
347 static inline void do_check_asi(CPUSPARCState
*env
, int asi
, uintptr_t ra
)
349 /* ASIs >= 0x80 are user mode.
350 * ASIs >= 0x30 are hyper mode (or super if hyper is not available).
351 * ASIs <= 0x2f are super mode.
354 && !cpu_hypervisor_mode(env
)
355 && (!cpu_supervisor_mode(env
)
356 || (asi
>= 0x30 && cpu_has_hypervisor(env
)))) {
357 cpu_raise_exception_ra(env
, TT_PRIV_ACT
, ra
);
360 #endif /* !CONFIG_USER_ONLY */
363 #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)
364 static void do_check_align(CPUSPARCState
*env
, target_ulong addr
,
365 uint32_t align
, uintptr_t ra
)
368 cpu_raise_exception_ra(env
, TT_UNALIGNED
, ra
);
373 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
375 static void dump_mxcc(CPUSPARCState
*env
)
377 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
379 env
->mxccdata
[0], env
->mxccdata
[1],
380 env
->mxccdata
[2], env
->mxccdata
[3]);
381 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
383 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
385 env
->mxccregs
[0], env
->mxccregs
[1],
386 env
->mxccregs
[2], env
->mxccregs
[3],
387 env
->mxccregs
[4], env
->mxccregs
[5],
388 env
->mxccregs
[6], env
->mxccregs
[7]);
392 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
393 && defined(DEBUG_ASI)
394 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
399 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
400 addr
, asi
, r1
& 0xff);
403 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
404 addr
, asi
, r1
& 0xffff);
407 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
408 addr
, asi
, r1
& 0xffffffff);
411 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
418 #ifndef CONFIG_USER_ONLY
419 #ifndef TARGET_SPARC64
420 static void sparc_raise_mmu_fault(CPUState
*cs
, hwaddr addr
,
421 bool is_write
, bool is_exec
, int is_asi
,
422 unsigned size
, uintptr_t retaddr
)
424 SPARCCPU
*cpu
= SPARC_CPU(cs
);
425 CPUSPARCState
*env
= &cpu
->env
;
428 #ifdef DEBUG_UNASSIGNED
430 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx
431 " asi 0x%02x from " TARGET_FMT_lx
"\n",
432 is_exec
? "exec" : is_write
? "write" : "read", size
,
433 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
435 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx
436 " from " TARGET_FMT_lx
"\n",
437 is_exec
? "exec" : is_write
? "write" : "read", size
,
438 size
== 1 ? "" : "s", addr
, env
->pc
);
441 /* Don't overwrite translation and access faults */
442 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
443 if ((fault_type
> 4) || (fault_type
== 0)) {
444 env
->mmuregs
[3] = 0; /* Fault status register */
446 env
->mmuregs
[3] |= 1 << 16;
449 env
->mmuregs
[3] |= 1 << 5;
452 env
->mmuregs
[3] |= 1 << 6;
455 env
->mmuregs
[3] |= 1 << 7;
457 env
->mmuregs
[3] |= (5 << 2) | 2;
458 /* SuperSPARC will never place instruction fault addresses in the FAR */
460 env
->mmuregs
[4] = addr
; /* Fault address register */
463 /* overflow (same type fault was not read before another fault) */
464 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
465 env
->mmuregs
[3] |= 1;
468 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
469 int tt
= is_exec
? TT_CODE_ACCESS
: TT_DATA_ACCESS
;
470 cpu_raise_exception_ra(env
, tt
, retaddr
);
474 * flush neverland mappings created during no-fault mode,
475 * so the sequential MMU faults report proper fault types
477 if (env
->mmuregs
[0] & MMU_NF
) {
482 static void sparc_raise_mmu_fault(CPUState
*cs
, hwaddr addr
,
483 bool is_write
, bool is_exec
, int is_asi
,
484 unsigned size
, uintptr_t retaddr
)
486 SPARCCPU
*cpu
= SPARC_CPU(cs
);
487 CPUSPARCState
*env
= &cpu
->env
;
489 #ifdef DEBUG_UNASSIGNED
490 printf("Unassigned mem access to " HWADDR_FMT_plx
" from " TARGET_FMT_lx
491 "\n", addr
, env
->pc
);
494 if (is_exec
) { /* XXX has_hypervisor */
495 if (env
->lsu
& (IMMU_E
)) {
496 cpu_raise_exception_ra(env
, TT_CODE_ACCESS
, retaddr
);
497 } else if (cpu_has_hypervisor(env
) && !(env
->hpstate
& HS_PRIV
)) {
498 cpu_raise_exception_ra(env
, TT_INSN_REAL_TRANSLATION_MISS
, retaddr
);
501 if (env
->lsu
& (DMMU_E
)) {
502 cpu_raise_exception_ra(env
, TT_DATA_ACCESS
, retaddr
);
503 } else if (cpu_has_hypervisor(env
) && !(env
->hpstate
& HS_PRIV
)) {
504 cpu_raise_exception_ra(env
, TT_DATA_REAL_TRANSLATION_MISS
, retaddr
);
511 #ifndef TARGET_SPARC64
512 #ifndef CONFIG_USER_ONLY
515 /* Leon3 cache control */
517 static void leon3_cache_control_st(CPUSPARCState
*env
, target_ulong addr
,
518 uint64_t val
, int size
)
520 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64
", size:%d\n",
524 DPRINTF_CACHE_CONTROL("32bits only\n");
529 case 0x00: /* Cache control */
531 /* These values must always be read as zeros */
532 val
&= ~CACHE_CTRL_FD
;
533 val
&= ~CACHE_CTRL_FI
;
534 val
&= ~CACHE_CTRL_IB
;
535 val
&= ~CACHE_CTRL_IP
;
536 val
&= ~CACHE_CTRL_DP
;
538 env
->cache_control
= val
;
540 case 0x04: /* Instruction cache configuration */
541 case 0x08: /* Data cache configuration */
545 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr
);
550 static uint64_t leon3_cache_control_ld(CPUSPARCState
*env
, target_ulong addr
,
556 DPRINTF_CACHE_CONTROL("32bits only\n");
561 case 0x00: /* Cache control */
562 ret
= env
->cache_control
;
565 /* Configuration registers are read and only always keep those
568 case 0x04: /* Instruction cache configuration */
571 case 0x08: /* Data cache configuration */
575 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr
);
578 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64
", size:%d\n",
583 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
,
584 int asi
, uint32_t memop
)
586 int size
= 1 << (memop
& MO_SIZE
);
587 int sign
= memop
& MO_SIGN
;
588 CPUState
*cs
= env_cpu(env
);
590 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
591 uint32_t last_addr
= addr
;
595 do_check_align(env
, addr
, size
- 1, GETPC());
597 case ASI_M_MXCC
: /* SuperSparc MXCC registers, or... */
598 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
600 case 0x00: /* Leon3 Cache Control */
601 case 0x08: /* Leon3 Instruction Cache config */
602 case 0x0C: /* Leon3 Date Cache config */
603 if (env
->def
.features
& CPU_FEATURE_CACHE_CTRL
) {
604 ret
= leon3_cache_control_ld(env
, addr
, size
);
607 case 0x01c00a00: /* MXCC control register */
609 ret
= env
->mxccregs
[3];
611 qemu_log_mask(LOG_UNIMP
,
612 "%08x: unimplemented access size: %d\n", addr
,
616 case 0x01c00a04: /* MXCC control register */
618 ret
= env
->mxccregs
[3];
620 qemu_log_mask(LOG_UNIMP
,
621 "%08x: unimplemented access size: %d\n", addr
,
625 case 0x01c00c00: /* Module reset register */
627 ret
= env
->mxccregs
[5];
628 /* should we do something here? */
630 qemu_log_mask(LOG_UNIMP
,
631 "%08x: unimplemented access size: %d\n", addr
,
635 case 0x01c00f00: /* MBus port address register */
637 ret
= env
->mxccregs
[7];
639 qemu_log_mask(LOG_UNIMP
,
640 "%08x: unimplemented access size: %d\n", addr
,
645 qemu_log_mask(LOG_UNIMP
,
646 "%08x: unimplemented address, size: %d\n", addr
,
650 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
651 "addr = %08x -> ret = %" PRIx64
","
652 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
657 case ASI_M_FLUSH_PROBE
: /* SuperSparc MMU probe */
658 case ASI_LEON_MMUFLUSH
: /* LEON3 MMU probe */
662 mmulev
= (addr
>> 8) & 15;
666 ret
= mmu_probe(env
, addr
, mmulev
);
668 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
672 case ASI_M_MMUREGS
: /* SuperSparc MMU regs */
673 case ASI_LEON_MMUREGS
: /* LEON3 MMU regs */
675 int reg
= (addr
>> 8) & 0x1f;
677 ret
= env
->mmuregs
[reg
];
678 if (reg
== 3) { /* Fault status cleared on read */
680 } else if (reg
== 0x13) { /* Fault status read */
681 ret
= env
->mmuregs
[3];
682 } else if (reg
== 0x14) { /* Fault address read */
683 ret
= env
->mmuregs
[4];
685 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
688 case ASI_M_TLBDIAG
: /* Turbosparc ITLB Diagnostic */
689 case ASI_M_DIAGS
: /* Turbosparc DTLB Diagnostic */
690 case ASI_M_IODIAG
: /* Turbosparc IOTLB Diagnostic */
692 case ASI_KERNELTXT
: /* Supervisor code access */
693 oi
= make_memop_idx(memop
, cpu_mmu_index(env
, true));
696 ret
= cpu_ldb_code_mmu(env
, addr
, oi
, GETPC());
699 ret
= cpu_ldw_code_mmu(env
, addr
, oi
, GETPC());
703 ret
= cpu_ldl_code_mmu(env
, addr
, oi
, GETPC());
706 ret
= cpu_ldq_code_mmu(env
, addr
, oi
, GETPC());
710 case ASI_M_TXTC_TAG
: /* SparcStation 5 I-cache tag */
711 case ASI_M_TXTC_DATA
: /* SparcStation 5 I-cache data */
712 case ASI_M_DATAC_TAG
: /* SparcStation 5 D-cache tag */
713 case ASI_M_DATAC_DATA
: /* SparcStation 5 D-cache data */
715 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
718 hwaddr access_addr
= (hwaddr
)addr
| ((hwaddr
)(asi
& 0xf) << 32);
722 ret
= address_space_ldub(cs
->as
, access_addr
,
723 MEMTXATTRS_UNSPECIFIED
, &result
);
726 ret
= address_space_lduw(cs
->as
, access_addr
,
727 MEMTXATTRS_UNSPECIFIED
, &result
);
731 ret
= address_space_ldl(cs
->as
, access_addr
,
732 MEMTXATTRS_UNSPECIFIED
, &result
);
735 ret
= address_space_ldq(cs
->as
, access_addr
,
736 MEMTXATTRS_UNSPECIFIED
, &result
);
740 if (result
!= MEMTX_OK
) {
741 sparc_raise_mmu_fault(cs
, access_addr
, false, false, false,
746 case 0x30: /* Turbosparc secondary cache diagnostic */
747 case 0x31: /* Turbosparc RAM snoop */
748 case 0x32: /* Turbosparc page table descriptor diagnostic */
749 case 0x39: /* data cache diagnostic register */
752 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
754 int reg
= (addr
>> 8) & 3;
757 case 0: /* Breakpoint Value (Addr) */
758 ret
= env
->mmubpregs
[reg
];
760 case 1: /* Breakpoint Mask */
761 ret
= env
->mmubpregs
[reg
];
763 case 2: /* Breakpoint Control */
764 ret
= env
->mmubpregs
[reg
];
766 case 3: /* Breakpoint Status */
767 ret
= env
->mmubpregs
[reg
];
768 env
->mmubpregs
[reg
] = 0ULL;
771 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
775 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
776 ret
= env
->mmubpctrv
;
778 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
779 ret
= env
->mmubpctrc
;
781 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
782 ret
= env
->mmubpctrs
;
784 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
785 ret
= env
->mmubpaction
;
787 case ASI_USERTXT
: /* User code access, XXX */
789 sparc_raise_mmu_fault(cs
, addr
, false, false, asi
, size
, GETPC());
793 case ASI_USERDATA
: /* User data access */
794 case ASI_KERNELDATA
: /* Supervisor data access */
795 case ASI_P
: /* Implicit primary context data access (v9 only?) */
796 case ASI_M_BYPASS
: /* MMU passthrough */
797 case ASI_LEON_BYPASS
: /* LEON MMU passthrough */
798 /* These are always handled inline. */
799 g_assert_not_reached();
817 dump_asi("read ", last_addr
, asi
, size
, ret
);
822 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, uint64_t val
,
823 int asi
, uint32_t memop
)
825 int size
= 1 << (memop
& MO_SIZE
);
826 CPUState
*cs
= env_cpu(env
);
828 do_check_align(env
, addr
, size
- 1, GETPC());
830 case ASI_M_MXCC
: /* SuperSparc MXCC registers, or... */
831 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
833 case 0x00: /* Leon3 Cache Control */
834 case 0x08: /* Leon3 Instruction Cache config */
835 case 0x0C: /* Leon3 Date Cache config */
836 if (env
->def
.features
& CPU_FEATURE_CACHE_CTRL
) {
837 leon3_cache_control_st(env
, addr
, val
, size
);
841 case 0x01c00000: /* MXCC stream data register 0 */
843 env
->mxccdata
[0] = val
;
845 qemu_log_mask(LOG_UNIMP
,
846 "%08x: unimplemented access size: %d\n", addr
,
850 case 0x01c00008: /* MXCC stream data register 1 */
852 env
->mxccdata
[1] = val
;
854 qemu_log_mask(LOG_UNIMP
,
855 "%08x: unimplemented access size: %d\n", addr
,
859 case 0x01c00010: /* MXCC stream data register 2 */
861 env
->mxccdata
[2] = val
;
863 qemu_log_mask(LOG_UNIMP
,
864 "%08x: unimplemented access size: %d\n", addr
,
868 case 0x01c00018: /* MXCC stream data register 3 */
870 env
->mxccdata
[3] = val
;
872 qemu_log_mask(LOG_UNIMP
,
873 "%08x: unimplemented access size: %d\n", addr
,
877 case 0x01c00100: /* MXCC stream source */
882 env
->mxccregs
[0] = val
;
884 qemu_log_mask(LOG_UNIMP
,
885 "%08x: unimplemented access size: %d\n", addr
,
889 for (i
= 0; i
< 4; i
++) {
891 hwaddr access_addr
= (env
->mxccregs
[0] & 0xffffffffULL
) + 8 * i
;
893 env
->mxccdata
[i
] = address_space_ldq(cs
->as
,
895 MEMTXATTRS_UNSPECIFIED
,
897 if (result
!= MEMTX_OK
) {
898 /* TODO: investigate whether this is the right behaviour */
899 sparc_raise_mmu_fault(cs
, access_addr
, false, false,
900 false, size
, GETPC());
905 case 0x01c00200: /* MXCC stream destination */
910 env
->mxccregs
[1] = val
;
912 qemu_log_mask(LOG_UNIMP
,
913 "%08x: unimplemented access size: %d\n", addr
,
917 for (i
= 0; i
< 4; i
++) {
919 hwaddr access_addr
= (env
->mxccregs
[1] & 0xffffffffULL
) + 8 * i
;
921 address_space_stq(cs
->as
, access_addr
, env
->mxccdata
[i
],
922 MEMTXATTRS_UNSPECIFIED
, &result
);
924 if (result
!= MEMTX_OK
) {
925 /* TODO: investigate whether this is the right behaviour */
926 sparc_raise_mmu_fault(cs
, access_addr
, true, false,
927 false, size
, GETPC());
932 case 0x01c00a00: /* MXCC control register */
934 env
->mxccregs
[3] = val
;
936 qemu_log_mask(LOG_UNIMP
,
937 "%08x: unimplemented access size: %d\n", addr
,
941 case 0x01c00a04: /* MXCC control register */
943 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
946 qemu_log_mask(LOG_UNIMP
,
947 "%08x: unimplemented access size: %d\n", addr
,
951 case 0x01c00e00: /* MXCC error register */
952 /* writing a 1 bit clears the error */
954 env
->mxccregs
[6] &= ~val
;
956 qemu_log_mask(LOG_UNIMP
,
957 "%08x: unimplemented access size: %d\n", addr
,
961 case 0x01c00f00: /* MBus port address register */
963 env
->mxccregs
[7] = val
;
965 qemu_log_mask(LOG_UNIMP
,
966 "%08x: unimplemented access size: %d\n", addr
,
971 qemu_log_mask(LOG_UNIMP
,
972 "%08x: unimplemented address, size: %d\n", addr
,
976 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
977 asi
, size
, addr
, val
);
982 case ASI_M_FLUSH_PROBE
: /* SuperSparc MMU flush */
983 case ASI_LEON_MMUFLUSH
: /* LEON3 MMU flush */
987 mmulev
= (addr
>> 8) & 15;
988 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
990 case 0: /* flush page */
991 tlb_flush_page(cs
, addr
& 0xfffff000);
993 case 1: /* flush segment (256k) */
994 case 2: /* flush region (16M) */
995 case 3: /* flush context (4G) */
996 case 4: /* flush entire */
1007 case ASI_M_MMUREGS
: /* write MMU regs */
1008 case ASI_LEON_MMUREGS
: /* LEON3 write MMU regs */
1010 int reg
= (addr
>> 8) & 0x1f;
1013 oldreg
= env
->mmuregs
[reg
];
1015 case 0: /* Control Register */
1016 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
1018 /* Mappings generated during no-fault mode
1019 are invalid in normal mode. */
1020 if ((oldreg
^ env
->mmuregs
[reg
])
1021 & (MMU_NF
| env
->def
.mmu_bm
)) {
1025 case 1: /* Context Table Pointer Register */
1026 env
->mmuregs
[reg
] = val
& env
->def
.mmu_ctpr_mask
;
1028 case 2: /* Context Register */
1029 env
->mmuregs
[reg
] = val
& env
->def
.mmu_cxr_mask
;
1030 if (oldreg
!= env
->mmuregs
[reg
]) {
1031 /* we flush when the MMU context changes because
1032 QEMU has no MMU context support */
1036 case 3: /* Synchronous Fault Status Register with Clear */
1037 case 4: /* Synchronous Fault Address Register */
1039 case 0x10: /* TLB Replacement Control Register */
1040 env
->mmuregs
[reg
] = val
& env
->def
.mmu_trcr_mask
;
1042 case 0x13: /* Synchronous Fault Status Register with Read
1044 env
->mmuregs
[3] = val
& env
->def
.mmu_sfsr_mask
;
1046 case 0x14: /* Synchronous Fault Address Register */
1047 env
->mmuregs
[4] = val
;
1050 env
->mmuregs
[reg
] = val
;
1053 if (oldreg
!= env
->mmuregs
[reg
]) {
1054 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1055 reg
, oldreg
, env
->mmuregs
[reg
]);
1062 case ASI_M_TLBDIAG
: /* Turbosparc ITLB Diagnostic */
1063 case ASI_M_DIAGS
: /* Turbosparc DTLB Diagnostic */
1064 case ASI_M_IODIAG
: /* Turbosparc IOTLB Diagnostic */
1066 case ASI_M_TXTC_TAG
: /* I-cache tag */
1067 case ASI_M_TXTC_DATA
: /* I-cache data */
1068 case ASI_M_DATAC_TAG
: /* D-cache tag */
1069 case ASI_M_DATAC_DATA
: /* D-cache data */
1070 case ASI_M_FLUSH_PAGE
: /* I/D-cache flush page */
1071 case ASI_M_FLUSH_SEG
: /* I/D-cache flush segment */
1072 case ASI_M_FLUSH_REGION
: /* I/D-cache flush region */
1073 case ASI_M_FLUSH_CTX
: /* I/D-cache flush context */
1074 case ASI_M_FLUSH_USER
: /* I/D-cache flush user */
1076 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1079 hwaddr access_addr
= (hwaddr
)addr
| ((hwaddr
)(asi
& 0xf) << 32);
1083 address_space_stb(cs
->as
, access_addr
, val
,
1084 MEMTXATTRS_UNSPECIFIED
, &result
);
1087 address_space_stw(cs
->as
, access_addr
, val
,
1088 MEMTXATTRS_UNSPECIFIED
, &result
);
1092 address_space_stl(cs
->as
, access_addr
, val
,
1093 MEMTXATTRS_UNSPECIFIED
, &result
);
1096 address_space_stq(cs
->as
, access_addr
, val
,
1097 MEMTXATTRS_UNSPECIFIED
, &result
);
1100 if (result
!= MEMTX_OK
) {
1101 sparc_raise_mmu_fault(cs
, access_addr
, true, false, false,
1106 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1107 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1108 Turbosparc snoop RAM */
1109 case 0x32: /* store buffer control or Turbosparc page table
1110 descriptor diagnostic */
1111 case 0x36: /* I-cache flash clear */
1112 case 0x37: /* D-cache flash clear */
1114 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1116 int reg
= (addr
>> 8) & 3;
1119 case 0: /* Breakpoint Value (Addr) */
1120 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1122 case 1: /* Breakpoint Mask */
1123 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1125 case 2: /* Breakpoint Control */
1126 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
1128 case 3: /* Breakpoint Status */
1129 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
1132 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
1136 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1137 env
->mmubpctrv
= val
& 0xffffffff;
1139 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1140 env
->mmubpctrc
= val
& 0x3;
1142 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1143 env
->mmubpctrs
= val
& 0x3;
1145 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1146 env
->mmubpaction
= val
& 0x1fff;
1148 case ASI_USERTXT
: /* User code access, XXX */
1149 case ASI_KERNELTXT
: /* Supervisor code access, XXX */
1151 sparc_raise_mmu_fault(cs
, addr
, true, false, asi
, size
, GETPC());
1154 case ASI_USERDATA
: /* User data access */
1155 case ASI_KERNELDATA
: /* Supervisor data access */
1157 case ASI_M_BYPASS
: /* MMU passthrough */
1158 case ASI_LEON_BYPASS
: /* LEON MMU passthrough */
1159 case ASI_M_BCOPY
: /* Block copy, sta access */
1160 case ASI_M_BFILL
: /* Block fill, stda access */
1161 /* These are always handled inline. */
1162 g_assert_not_reached();
1165 dump_asi("write", addr
, asi
, size
, val
);
1169 #endif /* CONFIG_USER_ONLY */
1170 #else /* TARGET_SPARC64 */
1172 #ifdef CONFIG_USER_ONLY
1173 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
,
1174 int asi
, uint32_t memop
)
1176 int size
= 1 << (memop
& MO_SIZE
);
1177 int sign
= memop
& MO_SIGN
;
1181 cpu_raise_exception_ra(env
, TT_PRIV_ACT
, GETPC());
1183 do_check_align(env
, addr
, size
- 1, GETPC());
1184 addr
= asi_address_mask(env
, asi
, addr
);
1187 case ASI_PNF
: /* Primary no-fault */
1188 case ASI_PNFL
: /* Primary no-fault LE */
1189 case ASI_SNF
: /* Secondary no-fault */
1190 case ASI_SNFL
: /* Secondary no-fault LE */
1191 if (!page_check_range(addr
, size
, PAGE_READ
)) {
1197 ret
= cpu_ldub_data(env
, addr
);
1200 ret
= cpu_lduw_data(env
, addr
);
1203 ret
= cpu_ldl_data(env
, addr
);
1206 ret
= cpu_ldq_data(env
, addr
);
1209 g_assert_not_reached();
1214 case ASI_P
: /* Primary */
1215 case ASI_PL
: /* Primary LE */
1216 case ASI_S
: /* Secondary */
1217 case ASI_SL
: /* Secondary LE */
1218 /* These are always handled inline. */
1219 g_assert_not_reached();
1222 cpu_raise_exception_ra(env
, TT_DATA_ACCESS
, GETPC());
1225 /* Convert from little endian */
1227 case ASI_PNFL
: /* Primary no-fault LE */
1228 case ASI_SNFL
: /* Secondary no-fault LE */
1242 /* Convert to signed number */
1249 ret
= (int16_t) ret
;
1252 ret
= (int32_t) ret
;
1257 dump_asi("read", addr
, asi
, size
, ret
);
1262 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1263 int asi
, uint32_t memop
)
1265 int size
= 1 << (memop
& MO_SIZE
);
1267 dump_asi("write", addr
, asi
, size
, val
);
1270 cpu_raise_exception_ra(env
, TT_PRIV_ACT
, GETPC());
1272 do_check_align(env
, addr
, size
- 1, GETPC());
1275 case ASI_P
: /* Primary */
1276 case ASI_PL
: /* Primary LE */
1277 case ASI_S
: /* Secondary */
1278 case ASI_SL
: /* Secondary LE */
1279 /* These are always handled inline. */
1280 g_assert_not_reached();
1282 case ASI_PNF
: /* Primary no-fault, RO */
1283 case ASI_SNF
: /* Secondary no-fault, RO */
1284 case ASI_PNFL
: /* Primary no-fault LE, RO */
1285 case ASI_SNFL
: /* Secondary no-fault LE, RO */
1287 cpu_raise_exception_ra(env
, TT_DATA_ACCESS
, GETPC());
1291 #else /* CONFIG_USER_ONLY */
1293 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
,
1294 int asi
, uint32_t memop
)
1296 int size
= 1 << (memop
& MO_SIZE
);
1297 int sign
= memop
& MO_SIGN
;
1298 CPUState
*cs
= env_cpu(env
);
1300 #if defined(DEBUG_ASI)
1301 target_ulong last_addr
= addr
;
1306 do_check_asi(env
, asi
, GETPC());
1307 do_check_align(env
, addr
, size
- 1, GETPC());
1308 addr
= asi_address_mask(env
, asi
, addr
);
1317 int idx
= (env
->pstate
& PS_PRIV
1318 ? (asi
& 1 ? MMU_KERNEL_SECONDARY_IDX
: MMU_KERNEL_IDX
)
1319 : (asi
& 1 ? MMU_USER_SECONDARY_IDX
: MMU_USER_IDX
));
1321 if (cpu_get_phys_page_nofault(env
, addr
, idx
) == -1ULL) {
1323 dump_asi("read ", last_addr
, asi
, size
, ret
);
1325 /* exception_index is set in get_physical_address_data. */
1326 cpu_raise_exception_ra(env
, cs
->exception_index
, GETPC());
1328 oi
= make_memop_idx(memop
, idx
);
1331 ret
= cpu_ldb_mmu(env
, addr
, oi
, GETPC());
1334 ret
= cpu_ldw_mmu(env
, addr
, oi
, GETPC());
1337 ret
= cpu_ldl_mmu(env
, addr
, oi
, GETPC());
1340 ret
= cpu_ldq_mmu(env
, addr
, oi
, GETPC());
1343 g_assert_not_reached();
1348 case ASI_AIUP
: /* As if user primary */
1349 case ASI_AIUS
: /* As if user secondary */
1350 case ASI_AIUPL
: /* As if user primary LE */
1351 case ASI_AIUSL
: /* As if user secondary LE */
1352 case ASI_P
: /* Primary */
1353 case ASI_S
: /* Secondary */
1354 case ASI_PL
: /* Primary LE */
1355 case ASI_SL
: /* Secondary LE */
1356 case ASI_REAL
: /* Bypass */
1357 case ASI_REAL_IO
: /* Bypass, non-cacheable */
1358 case ASI_REAL_L
: /* Bypass LE */
1359 case ASI_REAL_IO_L
: /* Bypass, non-cacheable LE */
1360 case ASI_N
: /* Nucleus */
1361 case ASI_NL
: /* Nucleus Little Endian (LE) */
1362 case ASI_NUCLEUS_QUAD_LDD
: /* Nucleus quad LDD 128 bit atomic */
1363 case ASI_NUCLEUS_QUAD_LDD_L
: /* Nucleus quad LDD 128 bit atomic LE */
1364 case ASI_TWINX_AIUP
: /* As if user primary, twinx */
1365 case ASI_TWINX_AIUS
: /* As if user secondary, twinx */
1366 case ASI_TWINX_REAL
: /* Real address, twinx */
1367 case ASI_TWINX_AIUP_L
: /* As if user primary, twinx, LE */
1368 case ASI_TWINX_AIUS_L
: /* As if user secondary, twinx, LE */
1369 case ASI_TWINX_REAL_L
: /* Real address, twinx, LE */
1370 case ASI_TWINX_N
: /* Nucleus, twinx */
1371 case ASI_TWINX_NL
: /* Nucleus, twinx, LE */
1372 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1373 case ASI_TWINX_P
: /* Primary, twinx */
1374 case ASI_TWINX_PL
: /* Primary, twinx, LE */
1375 case ASI_TWINX_S
: /* Secondary, twinx */
1376 case ASI_TWINX_SL
: /* Secondary, twinx, LE */
1377 /* These are always handled inline. */
1378 g_assert_not_reached();
1380 case ASI_UPA_CONFIG
: /* UPA config */
1383 case ASI_LSU_CONTROL
: /* LSU */
1386 case ASI_IMMU
: /* I-MMU regs */
1388 int reg
= (addr
>> 3) & 0xf;
1391 /* 0x00 I-TSB Tag Target register */
1392 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
1395 ret
= env
->immu
.sfsr
;
1397 case 5: /* TSB access */
1398 ret
= env
->immu
.tsb
;
1401 /* 0x30 I-TSB Tag Access register */
1402 ret
= env
->immu
.tag_access
;
1405 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1410 case ASI_IMMU_TSB_8KB_PTR
: /* I-MMU 8k TSB pointer */
1412 /* env->immuregs[5] holds I-MMU TSB register value
1413 env->immuregs[6] holds I-MMU Tag Access register value */
1414 ret
= ultrasparc_tsb_pointer(env
, &env
->immu
, 0);
1417 case ASI_IMMU_TSB_64KB_PTR
: /* I-MMU 64k TSB pointer */
1419 /* env->immuregs[5] holds I-MMU TSB register value
1420 env->immuregs[6] holds I-MMU Tag Access register value */
1421 ret
= ultrasparc_tsb_pointer(env
, &env
->immu
, 1);
1424 case ASI_ITLB_DATA_ACCESS
: /* I-MMU data access */
1426 int reg
= (addr
>> 3) & 0x3f;
1428 ret
= env
->itlb
[reg
].tte
;
1431 case ASI_ITLB_TAG_READ
: /* I-MMU tag read */
1433 int reg
= (addr
>> 3) & 0x3f;
1435 ret
= env
->itlb
[reg
].tag
;
1438 case ASI_DMMU
: /* D-MMU regs */
1440 int reg
= (addr
>> 3) & 0xf;
1443 /* 0x00 D-TSB Tag Target register */
1444 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
1446 case 1: /* 0x08 Primary Context */
1447 ret
= env
->dmmu
.mmu_primary_context
;
1449 case 2: /* 0x10 Secondary Context */
1450 ret
= env
->dmmu
.mmu_secondary_context
;
1453 ret
= env
->dmmu
.sfsr
;
1455 case 4: /* 0x20 SFAR */
1456 ret
= env
->dmmu
.sfar
;
1458 case 5: /* 0x28 TSB access */
1459 ret
= env
->dmmu
.tsb
;
1461 case 6: /* 0x30 D-TSB Tag Access register */
1462 ret
= env
->dmmu
.tag_access
;
1465 ret
= env
->dmmu
.virtual_watchpoint
;
1468 ret
= env
->dmmu
.physical_watchpoint
;
1471 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1476 case ASI_DMMU_TSB_8KB_PTR
: /* D-MMU 8k TSB pointer */
1478 /* env->dmmuregs[5] holds D-MMU TSB register value
1479 env->dmmuregs[6] holds D-MMU Tag Access register value */
1480 ret
= ultrasparc_tsb_pointer(env
, &env
->dmmu
, 0);
1483 case ASI_DMMU_TSB_64KB_PTR
: /* D-MMU 64k TSB pointer */
1485 /* env->dmmuregs[5] holds D-MMU TSB register value
1486 env->dmmuregs[6] holds D-MMU Tag Access register value */
1487 ret
= ultrasparc_tsb_pointer(env
, &env
->dmmu
, 1);
1490 case ASI_DTLB_DATA_ACCESS
: /* D-MMU data access */
1492 int reg
= (addr
>> 3) & 0x3f;
1494 ret
= env
->dtlb
[reg
].tte
;
1497 case ASI_DTLB_TAG_READ
: /* D-MMU tag read */
1499 int reg
= (addr
>> 3) & 0x3f;
1501 ret
= env
->dtlb
[reg
].tag
;
1504 case ASI_INTR_DISPATCH_STAT
: /* Interrupt dispatch, RO */
1506 case ASI_INTR_RECEIVE
: /* Interrupt data receive */
1507 ret
= env
->ivec_status
;
1509 case ASI_INTR_R
: /* Incoming interrupt vector, RO */
1511 int reg
= (addr
>> 4) & 0x3;
1513 ret
= env
->ivec_data
[reg
];
1517 case ASI_SCRATCHPAD
: /* UA2005 privileged scratchpad */
1518 if (unlikely((addr
>= 0x20) && (addr
< 0x30))) {
1519 /* Hyperprivileged access only */
1520 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1523 case ASI_HYP_SCRATCHPAD
: /* UA2005 hyperprivileged scratchpad */
1525 unsigned int i
= (addr
>> 3) & 0x7;
1526 ret
= env
->scratch
[i
];
1529 case ASI_MMU
: /* UA2005 Context ID registers */
1530 switch ((addr
>> 3) & 0x3) {
1532 ret
= env
->dmmu
.mmu_primary_context
;
1535 ret
= env
->dmmu
.mmu_secondary_context
;
1538 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1541 case ASI_DCACHE_DATA
: /* D-cache data */
1542 case ASI_DCACHE_TAG
: /* D-cache tag access */
1543 case ASI_ESTATE_ERROR_EN
: /* E-cache error enable */
1544 case ASI_AFSR
: /* E-cache asynchronous fault status */
1545 case ASI_AFAR
: /* E-cache asynchronous fault address */
1546 case ASI_EC_TAG_DATA
: /* E-cache tag data */
1547 case ASI_IC_INSTR
: /* I-cache instruction access */
1548 case ASI_IC_TAG
: /* I-cache tag access */
1549 case ASI_IC_PRE_DECODE
: /* I-cache predecode */
1550 case ASI_IC_NEXT_FIELD
: /* I-cache LRU etc. */
1551 case ASI_EC_W
: /* E-cache tag */
1552 case ASI_EC_R
: /* E-cache tag */
1554 case ASI_DMMU_TSB_DIRECT_PTR
: /* D-MMU data pointer */
1555 case ASI_ITLB_DATA_IN
: /* I-MMU data in, WO */
1556 case ASI_IMMU_DEMAP
: /* I-MMU demap, WO */
1557 case ASI_DTLB_DATA_IN
: /* D-MMU data in, WO */
1558 case ASI_DMMU_DEMAP
: /* D-MMU demap, WO */
1559 case ASI_INTR_W
: /* Interrupt vector, WO */
1561 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1566 /* Convert to signed number */
1573 ret
= (int16_t) ret
;
1576 ret
= (int32_t) ret
;
1583 dump_asi("read ", last_addr
, asi
, size
, ret
);
1588 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1589 int asi
, uint32_t memop
)
1591 int size
= 1 << (memop
& MO_SIZE
);
1592 CPUState
*cs
= env_cpu(env
);
1595 dump_asi("write", addr
, asi
, size
, val
);
1600 do_check_asi(env
, asi
, GETPC());
1601 do_check_align(env
, addr
, size
- 1, GETPC());
1602 addr
= asi_address_mask(env
, asi
, addr
);
1605 case ASI_AIUP
: /* As if user primary */
1606 case ASI_AIUS
: /* As if user secondary */
1607 case ASI_AIUPL
: /* As if user primary LE */
1608 case ASI_AIUSL
: /* As if user secondary LE */
1609 case ASI_P
: /* Primary */
1610 case ASI_S
: /* Secondary */
1611 case ASI_PL
: /* Primary LE */
1612 case ASI_SL
: /* Secondary LE */
1613 case ASI_REAL
: /* Bypass */
1614 case ASI_REAL_IO
: /* Bypass, non-cacheable */
1615 case ASI_REAL_L
: /* Bypass LE */
1616 case ASI_REAL_IO_L
: /* Bypass, non-cacheable LE */
1617 case ASI_N
: /* Nucleus */
1618 case ASI_NL
: /* Nucleus Little Endian (LE) */
1619 case ASI_NUCLEUS_QUAD_LDD
: /* Nucleus quad LDD 128 bit atomic */
1620 case ASI_NUCLEUS_QUAD_LDD_L
: /* Nucleus quad LDD 128 bit atomic LE */
1621 case ASI_TWINX_AIUP
: /* As if user primary, twinx */
1622 case ASI_TWINX_AIUS
: /* As if user secondary, twinx */
1623 case ASI_TWINX_REAL
: /* Real address, twinx */
1624 case ASI_TWINX_AIUP_L
: /* As if user primary, twinx, LE */
1625 case ASI_TWINX_AIUS_L
: /* As if user secondary, twinx, LE */
1626 case ASI_TWINX_REAL_L
: /* Real address, twinx, LE */
1627 case ASI_TWINX_N
: /* Nucleus, twinx */
1628 case ASI_TWINX_NL
: /* Nucleus, twinx, LE */
1629 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1630 case ASI_TWINX_P
: /* Primary, twinx */
1631 case ASI_TWINX_PL
: /* Primary, twinx, LE */
1632 case ASI_TWINX_S
: /* Secondary, twinx */
1633 case ASI_TWINX_SL
: /* Secondary, twinx, LE */
1634 /* These are always handled inline. */
1635 g_assert_not_reached();
1636 /* these ASIs have different functions on UltraSPARC-IIIi
1637 * and UA2005 CPUs. Use the explicit numbers to avoid confusion
1643 if (cpu_has_hypervisor(env
)) {
1645 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS0
1646 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS1
1647 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0
1648 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1
1650 int idx
= ((asi
& 2) >> 1) | ((asi
& 8) >> 2);
1651 env
->dmmu
.sun4v_tsb_pointers
[idx
] = val
;
1658 if (cpu_has_hypervisor(env
)) {
1660 * ASI_DMMU_CTX_ZERO_CONFIG
1661 * ASI_DMMU_CTX_NONZERO_CONFIG
1663 env
->dmmu
.sun4v_ctx_config
[(asi
& 8) >> 3] = val
;
1672 if (cpu_has_hypervisor(env
)) {
1674 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS0
1675 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS1
1676 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0
1677 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1
1679 int idx
= ((asi
& 2) >> 1) | ((asi
& 8) >> 2);
1680 env
->immu
.sun4v_tsb_pointers
[idx
] = val
;
1687 if (cpu_has_hypervisor(env
)) {
1689 * ASI_IMMU_CTX_ZERO_CONFIG
1690 * ASI_IMMU_CTX_NONZERO_CONFIG
1692 env
->immu
.sun4v_ctx_config
[(asi
& 8) >> 3] = val
;
1697 case ASI_UPA_CONFIG
: /* UPA config */
1700 case ASI_LSU_CONTROL
: /* LSU */
1701 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
1703 case ASI_IMMU
: /* I-MMU regs */
1705 int reg
= (addr
>> 3) & 0xf;
1708 oldreg
= env
->immu
.mmuregs
[reg
];
1712 case 1: /* Not in I-MMU */
1716 if ((val
& 1) == 0) {
1717 val
= 0; /* Clear SFSR */
1719 env
->immu
.sfsr
= val
;
1723 case 5: /* TSB access */
1724 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
1725 PRIx64
"\n", env
->immu
.tsb
, val
);
1726 env
->immu
.tsb
= val
;
1728 case 6: /* Tag access */
1729 env
->immu
.tag_access
= val
;
1735 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1739 if (oldreg
!= env
->immu
.mmuregs
[reg
]) {
1740 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1741 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
1748 case ASI_ITLB_DATA_IN
: /* I-MMU data in */
1749 /* ignore real translation entries */
1750 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1751 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
,
1752 val
, "immu", env
, addr
);
1755 case ASI_ITLB_DATA_ACCESS
: /* I-MMU data access */
1757 /* TODO: auto demap */
1759 unsigned int i
= (addr
>> 3) & 0x3f;
1761 /* ignore real translation entries */
1762 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1763 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
,
1764 sun4v_tte_to_sun4u(env
, addr
, val
), env
);
1767 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
1772 case ASI_IMMU_DEMAP
: /* I-MMU demap */
1773 demap_tlb(env
->itlb
, addr
, "immu", env
);
1775 case ASI_DMMU
: /* D-MMU regs */
1777 int reg
= (addr
>> 3) & 0xf;
1780 oldreg
= env
->dmmu
.mmuregs
[reg
];
1786 if ((val
& 1) == 0) {
1787 val
= 0; /* Clear SFSR, Fault address */
1790 env
->dmmu
.sfsr
= val
;
1792 case 1: /* Primary context */
1793 env
->dmmu
.mmu_primary_context
= val
;
1794 /* can be optimized to only flush MMU_USER_IDX
1795 and MMU_KERNEL_IDX entries */
1798 case 2: /* Secondary context */
1799 env
->dmmu
.mmu_secondary_context
= val
;
1800 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1801 and MMU_KERNEL_SECONDARY_IDX entries */
1804 case 5: /* TSB access */
1805 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
1806 PRIx64
"\n", env
->dmmu
.tsb
, val
);
1807 env
->dmmu
.tsb
= val
;
1809 case 6: /* Tag access */
1810 env
->dmmu
.tag_access
= val
;
1812 case 7: /* Virtual Watchpoint */
1813 env
->dmmu
.virtual_watchpoint
= val
;
1815 case 8: /* Physical Watchpoint */
1816 env
->dmmu
.physical_watchpoint
= val
;
1819 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1823 if (oldreg
!= env
->dmmu
.mmuregs
[reg
]) {
1824 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1825 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
1832 case ASI_DTLB_DATA_IN
: /* D-MMU data in */
1833 /* ignore real translation entries */
1834 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1835 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
,
1836 val
, "dmmu", env
, addr
);
1839 case ASI_DTLB_DATA_ACCESS
: /* D-MMU data access */
1841 unsigned int i
= (addr
>> 3) & 0x3f;
1843 /* ignore real translation entries */
1844 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1845 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
,
1846 sun4v_tte_to_sun4u(env
, addr
, val
), env
);
1849 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
1854 case ASI_DMMU_DEMAP
: /* D-MMU demap */
1855 demap_tlb(env
->dtlb
, addr
, "dmmu", env
);
1857 case ASI_INTR_RECEIVE
: /* Interrupt data receive */
1858 env
->ivec_status
= val
& 0x20;
1860 case ASI_SCRATCHPAD
: /* UA2005 privileged scratchpad */
1861 if (unlikely((addr
>= 0x20) && (addr
< 0x30))) {
1862 /* Hyperprivileged access only */
1863 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1866 case ASI_HYP_SCRATCHPAD
: /* UA2005 hyperprivileged scratchpad */
1868 unsigned int i
= (addr
>> 3) & 0x7;
1869 env
->scratch
[i
] = val
;
1872 case ASI_MMU
: /* UA2005 Context ID registers */
1874 switch ((addr
>> 3) & 0x3) {
1876 env
->dmmu
.mmu_primary_context
= val
;
1877 env
->immu
.mmu_primary_context
= val
;
1878 tlb_flush_by_mmuidx(cs
,
1879 (1 << MMU_USER_IDX
) | (1 << MMU_KERNEL_IDX
));
1882 env
->dmmu
.mmu_secondary_context
= val
;
1883 env
->immu
.mmu_secondary_context
= val
;
1884 tlb_flush_by_mmuidx(cs
,
1885 (1 << MMU_USER_SECONDARY_IDX
) |
1886 (1 << MMU_KERNEL_SECONDARY_IDX
));
1889 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1893 case ASI_QUEUE
: /* UA2005 CPU mondo queue */
1894 case ASI_DCACHE_DATA
: /* D-cache data */
1895 case ASI_DCACHE_TAG
: /* D-cache tag access */
1896 case ASI_ESTATE_ERROR_EN
: /* E-cache error enable */
1897 case ASI_AFSR
: /* E-cache asynchronous fault status */
1898 case ASI_AFAR
: /* E-cache asynchronous fault address */
1899 case ASI_EC_TAG_DATA
: /* E-cache tag data */
1900 case ASI_IC_INSTR
: /* I-cache instruction access */
1901 case ASI_IC_TAG
: /* I-cache tag access */
1902 case ASI_IC_PRE_DECODE
: /* I-cache predecode */
1903 case ASI_IC_NEXT_FIELD
: /* I-cache LRU etc. */
1904 case ASI_EC_W
: /* E-cache tag */
1905 case ASI_EC_R
: /* E-cache tag */
1907 case ASI_IMMU_TSB_8KB_PTR
: /* I-MMU 8k TSB pointer, RO */
1908 case ASI_IMMU_TSB_64KB_PTR
: /* I-MMU 64k TSB pointer, RO */
1909 case ASI_ITLB_TAG_READ
: /* I-MMU tag read, RO */
1910 case ASI_DMMU_TSB_8KB_PTR
: /* D-MMU 8k TSB pointer, RO */
1911 case ASI_DMMU_TSB_64KB_PTR
: /* D-MMU 64k TSB pointer, RO */
1912 case ASI_DMMU_TSB_DIRECT_PTR
: /* D-MMU data pointer, RO */
1913 case ASI_DTLB_TAG_READ
: /* D-MMU tag read, RO */
1914 case ASI_INTR_DISPATCH_STAT
: /* Interrupt dispatch, RO */
1915 case ASI_INTR_R
: /* Incoming interrupt vector, RO */
1916 case ASI_PNF
: /* Primary no-fault, RO */
1917 case ASI_SNF
: /* Secondary no-fault, RO */
1918 case ASI_PNFL
: /* Primary no-fault LE, RO */
1919 case ASI_SNFL
: /* Secondary no-fault LE, RO */
1921 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1924 cpu_raise_exception_ra(env
, TT_ILL_INSN
, GETPC());
1927 #endif /* CONFIG_USER_ONLY */
1928 #endif /* TARGET_SPARC64 */
1930 #if !defined(CONFIG_USER_ONLY)
1932 void sparc_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
1933 vaddr addr
, unsigned size
,
1934 MMUAccessType access_type
,
1935 int mmu_idx
, MemTxAttrs attrs
,
1936 MemTxResult response
, uintptr_t retaddr
)
1938 bool is_write
= access_type
== MMU_DATA_STORE
;
1939 bool is_exec
= access_type
== MMU_INST_FETCH
;
1940 bool is_asi
= false;
1942 sparc_raise_mmu_fault(cs
, physaddr
, is_write
, is_exec
,
1943 is_asi
, size
, retaddr
);