hw/arm/xlnx-zynqmp.c

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "hw/arm/xlnx-zynqmp.h"
  19 #include "hw/intc/arm_gic_common.h"
  20 #include "exec/address-spaces.h"
  21
  22 #define GIC_NUM_SPI_INTR 160
  23
  24 #define ARM_PHYS_TIMER_PPI  30
  25 #define ARM_VIRT_TIMER_PPI  27
  26
  27 #define GIC_BASE_ADDR       0xf9000000
  28 #define GIC_DIST_ADDR       0xf9010000
  29 #define GIC_CPU_ADDR        0xf9020000
  30
  31 #define SATA_INTR           133
  32 #define SATA_ADDR           0xFD0C0000
  33 #define SATA_NUM_PORTS      2
  34
  35 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  36     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  37 };
  38
  39 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  40     57, 59, 61, 63,
  41 };
  42
  43 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  44     0xFF000000, 0xFF010000,
  45 };
  46
  47 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  48     21, 22,
  49 };
  50
  51 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
  52     0xFF160000, 0xFF170000,
  53 };
  54
  55 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
  56     48, 49,
  57 };
  58
  59 typedef struct XlnxZynqMPGICRegion {
  60     int region_index;
  61     uint32_t address;
  62 } XlnxZynqMPGICRegion;
  63
  64 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
  65     { .region_index = 0, .address = GIC_DIST_ADDR, },
  66     { .region_index = 1, .address = GIC_CPU_ADDR,  },
  67 };
  68
  69 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
  70 {
  71     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
  72 }
  73
  74 static void xlnx_zynqmp_init(Object *obj)
  75 {
  76     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
  77     int i;
  78
  79     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
  80         object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
  81                           "cortex-a53-" TYPE_ARM_CPU);
  82         object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
  83                                   &error_abort);
  84     }
  85
  86     for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
  87         object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
  88                           "cortex-r5-" TYPE_ARM_CPU);
  89         object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]),
  90                                   &error_abort);
  91     }
  92
  93     object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
  94     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
  95
  96     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
  97         object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
  98         qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
  99     }
 100
 101     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 102         object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
 103         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
 104     }
 105
 106     object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
 107     qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
 108
 109     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 110         object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
 111                           TYPE_SYSBUS_SDHCI);
 112         qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
 113                             sysbus_get_default());
 114     }
 115 }
 116
 117 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 118 {
 119     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
 120     MemoryRegion *system_memory = get_system_memory();
 121     uint8_t i;
 122     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
 123     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
 124     Error *err = NULL;
 125
 126     /* Create the four OCM banks */
 127     for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
 128         char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
 129
 130         memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
 131                                XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
 132         vmstate_register_ram_global(&s->ocm_ram[i]);
 133         memory_region_add_subregion(get_system_memory(),
 134                                     XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
 135                                         i * XLNX_ZYNQMP_OCM_RAM_SIZE,
 136                                     &s->ocm_ram[i]);
 137
 138         g_free(ocm_name);
 139     }
 140
 141     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
 142     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
 143     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
 144     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
 145     if (err) {
 146         error_propagate(errp, err);
 147         return;
 148     }
 149     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
 150     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
 151         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
 152         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
 153         MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
 154         uint32_t addr = r->address;
 155         int j;
 156
 157         sysbus_mmio_map(gic, r->region_index, addr);
 158
 159         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
 160             MemoryRegion *alias = &s->gic_mr[i][j];
 161
 162             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
 163             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
 164                                      0, XLNX_ZYNQMP_GIC_REGION_SIZE);
 165             memory_region_add_subregion(system_memory, addr, alias);
 166         }
 167     }
 168
 169     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
 170         qemu_irq irq;
 171         char *name;
 172
 173         object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
 174                                 "psci-conduit", &error_abort);
 175
 176         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
 177         if (strcmp(name, boot_cpu)) {
 178             /* Secondary CPUs start in PSCI powered-down state */
 179             object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
 180                                      "start-powered-off", &error_abort);
 181         } else {
 182             s->boot_cpu_ptr = &s->apu_cpu[i];
 183         }
 184         g_free(name);
 185
 186         object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
 187                                 "reset-cbar", &error_abort);
 188         object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
 189                                  &err);
 190         if (err) {
 191             error_propagate(errp, err);
 192             return;
 193         }
 194
 195         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
 196                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 197                                             ARM_CPU_IRQ));
 198         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 199                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
 200         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
 201         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 202                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
 203         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
 204     }
 205
 206     for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
 207         char *name;
 208
 209         name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
 210         if (strcmp(name, boot_cpu)) {
 211             /* Secondary CPUs start in PSCI powered-down state */
 212             object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
 213                                      "start-powered-off", &error_abort);
 214         } else {
 215             s->boot_cpu_ptr = &s->rpu_cpu[i];
 216         }
 217         g_free(name);
 218
 219         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
 220                                  &error_abort);
 221         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
 222                                  &err);
 223         if (err) {
 224             error_propagate(errp, err);
 225             return;
 226         }
 227     }
 228
 229     if (!s->boot_cpu_ptr) {
 230         error_setg(errp, "ZynqMP Boot cpu %s not found\n", boot_cpu);
 231         return;
 232     }
 233
 234     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
 235         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 236     }
 237
 238     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 239         NICInfo *nd = &nd_table[i];
 240
 241         if (nd->used) {
 242             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 243             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
 244         }
 245         object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
 246         if (err) {
 247             error_propagate(errp, err);
 248             return;
 249         }
 250         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
 251         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
 252                            gic_spi[gem_intr[i]]);
 253     }
 254
 255     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 256         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 257         if (err) {
 258             error_propagate(errp, err);
 259             return;
 260         }
 261         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
 262         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 263                            gic_spi[uart_intr[i]]);
 264     }
 265
 266     object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
 267                             &error_abort);
 268     object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
 269     if (err) {
 270         error_propagate(errp, err);
 271         return;
 272     }
 273
 274     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
 275     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
 276
 277     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 278         object_property_set_bool(OBJECT(&s->sdhci[i]), true,
 279                                  "realized", &err);
 280         if (err) {
 281             error_propagate(errp, err);
 282             return;
 283         }
 284         sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
 285                         sdhci_addr[i]);
 286         sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
 287                            gic_spi[sdhci_intr[i]]);
 288     }
 289 }
 290
 291 static Property xlnx_zynqmp_props[] = {
 292     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
 293     DEFINE_PROP_END_OF_LIST()
 294 };
 295
 296 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 297 {
 298     DeviceClass *dc = DEVICE_CLASS(oc);
 299
 300     dc->props = xlnx_zynqmp_props;
 301     dc->realize = xlnx_zynqmp_realize;
 302
 303     /*
 304      * Reason: creates an ARM CPU, thus use after free(), see
 305      * arm_cpu_class_init()
 306      */
 307     dc->cannot_destroy_with_object_finalize_yet = true;
 308 }
 309
 310 static const TypeInfo xlnx_zynqmp_type_info = {
 311     .name = TYPE_XLNX_ZYNQMP,
 312     .parent = TYPE_DEVICE,
 313     .instance_size = sizeof(XlnxZynqMPState),
 314     .instance_init = xlnx_zynqmp_init,
 315     .class_init = xlnx_zynqmp_class_init,
 316 };
 317
 318 static void xlnx_zynqmp_register_types(void)
 319 {
 320     type_register_static(&xlnx_zynqmp_type_info);
 321 }
 322
 323 type_init(xlnx_zynqmp_register_types)