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ppc/pnv: add a 'dt_isa_nodename' to the chip
[qemu/ar7.git] / hw / ppc / pnv.c
blob6625562d276d0360378562ecebf91297b516b58d
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qapi/error.h"
23 #include "sysemu/sysemu.h"
24 #include "sysemu/numa.h"
25 #include "sysemu/cpus.h"
26 #include "hw/hw.h"
27 #include "target/ppc/cpu.h"
28 #include "qemu/log.h"
29 #include "hw/ppc/fdt.h"
30 #include "hw/ppc/ppc.h"
31 #include "hw/ppc/pnv.h"
32 #include "hw/ppc/pnv_core.h"
33 #include "hw/loader.h"
34 #include "exec/address-spaces.h"
35 #include "qapi/visitor.h"
36 #include "monitor/monitor.h"
37 #include "hw/intc/intc.h"
38 #include "hw/ipmi/ipmi.h"
39 #include "target/ppc/mmu-hash64.h"
40
41 #include "hw/ppc/xics.h"
42 #include "hw/ppc/pnv_xscom.h"
43
44 #include "hw/isa/isa.h"
45 #include "hw/char/serial.h"
46 #include "hw/timer/mc146818rtc.h"
47
48 #include <libfdt.h>
49
50 #define FDT_MAX_SIZE (1 * MiB)
51
52 #define FW_FILE_NAME "skiboot.lid"
53 #define FW_LOAD_ADDR 0x0
54 #define FW_MAX_SIZE (4 * MiB)
55
56 #define KERNEL_LOAD_ADDR 0x20000000
57 #define KERNEL_MAX_SIZE (256 * MiB)
58 #define INITRD_LOAD_ADDR 0x60000000
59 #define INITRD_MAX_SIZE (256 * MiB)
60
61 static const char *pnv_chip_core_typename(const PnvChip *o)
62 {
63 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
64 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
65 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
66 const char *core_type = object_class_get_name(object_class_by_name(s));
67 g_free(s);
68 return core_type;
69 }
70
71 /*
72 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
73 * 4 * 4 sockets * 12 cores * 8 threads = 1536
74 * Let's make it 2^11
75 */
76 #define MAX_CPUS 2048
77
78 /*
79 * Memory nodes are created by hostboot, one for each range of memory
80 * that has a different "affinity". In practice, it means one range
81 * per chip.
82 */
83 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
84 {
85 char *mem_name;
86 uint64_t mem_reg_property[2];
87 int off;
88
89 mem_reg_property[0] = cpu_to_be64(start);
90 mem_reg_property[1] = cpu_to_be64(size);
91
92 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
93 off = fdt_add_subnode(fdt, 0, mem_name);
94 g_free(mem_name);
95
96 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
97 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
98 sizeof(mem_reg_property))));
99 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
100 }
101
102 static int get_cpus_node(void *fdt)
103 {
104 int cpus_offset = fdt_path_offset(fdt, "/cpus");
105
106 if (cpus_offset < 0) {
107 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
108 if (cpus_offset) {
109 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
110 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
111 }
112 }
113 _FDT(cpus_offset);
114 return cpus_offset;
115 }
116
117 /*
118 * The PowerNV cores (and threads) need to use real HW ids and not an
119 * incremental index like it has been done on other platforms. This HW
120 * id is stored in the CPU PIR, it is used to create cpu nodes in the
121 * device tree, used in XSCOM to address cores and in interrupt
122 * servers.
123 */
124 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
125 {
126 PowerPCCPU *cpu = pc->threads[0];
127 CPUState *cs = CPU(cpu);
128 DeviceClass *dc = DEVICE_GET_CLASS(cs);
129 int smt_threads = CPU_CORE(pc)->nr_threads;
130 CPUPPCState *env = &cpu->env;
131 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
132 uint32_t servers_prop[smt_threads];
133 int i;
134 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
135 0xffffffff, 0xffffffff};
136 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
137 uint32_t cpufreq = 1000000000;
138 uint32_t page_sizes_prop[64];
139 size_t page_sizes_prop_size;
140 const uint8_t pa_features[] = { 24, 0,
141 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
142 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
143 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
144 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
145 int offset;
146 char *nodename;
147 int cpus_offset = get_cpus_node(fdt);
148
149 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
150 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
151 _FDT(offset);
152 g_free(nodename);
153
154 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
155
156 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
157 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
158 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
159
160 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
161 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
162 env->dcache_line_size)));
163 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
164 env->dcache_line_size)));
165 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
166 env->icache_line_size)));
167 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
168 env->icache_line_size)));
169
170 if (pcc->l1_dcache_size) {
171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
172 pcc->l1_dcache_size)));
173 } else {
174 warn_report("Unknown L1 dcache size for cpu");
175 }
176 if (pcc->l1_icache_size) {
177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
178 pcc->l1_icache_size)));
179 } else {
180 warn_report("Unknown L1 icache size for cpu");
181 }
182
183 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
184 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
185 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
186 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
187 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
188
189 if (env->spr_cb[SPR_PURR].oea_read) {
190 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
191 }
192
193 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
194 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
195 segs, sizeof(segs))));
196 }
197
198 /* Advertise VMX/VSX (vector extensions) if available
199 * 0 / no property == no vector extensions
200 * 1 == VMX / Altivec available
201 * 2 == VSX available */
202 if (env->insns_flags & PPC_ALTIVEC) {
203 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
204
205 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
206 }
207
208 /* Advertise DFP (Decimal Floating Point) if available
209 * 0 / no property == no DFP
210 * 1 == DFP available */
211 if (env->insns_flags2 & PPC2_DFP) {
212 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
213 }
214
215 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
216 sizeof(page_sizes_prop));
217 if (page_sizes_prop_size) {
218 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
219 page_sizes_prop, page_sizes_prop_size)));
220 }
221
222 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
223 pa_features, sizeof(pa_features))));
224
225 /* Build interrupt servers properties */
226 for (i = 0; i < smt_threads; i++) {
227 servers_prop[i] = cpu_to_be32(pc->pir + i);
228 }
229 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
230 servers_prop, sizeof(servers_prop))));
231 }
232
233 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
234 uint32_t nr_threads)
235 {
236 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
237 char *name;
238 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
239 uint32_t irange[2], i, rsize;
240 uint64_t *reg;
241 int offset;
242
243 irange[0] = cpu_to_be32(pir);
244 irange[1] = cpu_to_be32(nr_threads);
245
246 rsize = sizeof(uint64_t) * 2 * nr_threads;
247 reg = g_malloc(rsize);
248 for (i = 0; i < nr_threads; i++) {
249 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
250 reg[i * 2 + 1] = cpu_to_be64(0x1000);
251 }
252
253 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
254 offset = fdt_add_subnode(fdt, 0, name);
255 _FDT(offset);
256 g_free(name);
257
258 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
259 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
260 _FDT((fdt_setprop_string(fdt, offset, "device_type",
261 "PowerPC-External-Interrupt-Presentation")));
262 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
263 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
264 irange, sizeof(irange))));
265 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
266 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
267 g_free(reg);
268 }
269
270 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
271 {
272 const char *typename = pnv_chip_core_typename(chip);
273 size_t typesize = object_type_get_instance_size(typename);
274 int i;
275
276 pnv_dt_xscom(chip, fdt, 0);
277
278 for (i = 0; i < chip->nr_cores; i++) {
279 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
280
281 pnv_dt_core(chip, pnv_core, fdt);
282
283 /* Interrupt Control Presenters (ICP). One per core. */
284 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
285 }
286
287 if (chip->ram_size) {
288 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
289 }
290 }
291
292 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
293 {
294 const char *typename = pnv_chip_core_typename(chip);
295 size_t typesize = object_type_get_instance_size(typename);
296 int i;
297
298 pnv_dt_xscom(chip, fdt, 0);
299
300 for (i = 0; i < chip->nr_cores; i++) {
301 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
302
303 pnv_dt_core(chip, pnv_core, fdt);
304 }
305
306 if (chip->ram_size) {
307 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
308 }
309 }
310
311 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
312 {
313 uint32_t io_base = d->ioport_id;
314 uint32_t io_regs[] = {
315 cpu_to_be32(1),
316 cpu_to_be32(io_base),
317 cpu_to_be32(2)
318 };
319 char *name;
320 int node;
321
322 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
323 node = fdt_add_subnode(fdt, lpc_off, name);
324 _FDT(node);
325 g_free(name);
326
327 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
328 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
329 }
330
331 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
332 {
333 const char compatible[] = "ns16550\0pnpPNP,501";
334 uint32_t io_base = d->ioport_id;
335 uint32_t io_regs[] = {
336 cpu_to_be32(1),
337 cpu_to_be32(io_base),
338 cpu_to_be32(8)
339 };
340 char *name;
341 int node;
342
343 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
344 node = fdt_add_subnode(fdt, lpc_off, name);
345 _FDT(node);
346 g_free(name);
347
348 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
349 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
350 sizeof(compatible))));
351
352 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
353 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
354 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
355 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
356 fdt_get_phandle(fdt, lpc_off))));
357
358 /* This is needed by Linux */
359 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
360 }
361
362 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
363 {
364 const char compatible[] = "bt\0ipmi-bt";
365 uint32_t io_base;
366 uint32_t io_regs[] = {
367 cpu_to_be32(1),
368 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
369 cpu_to_be32(3)
370 };
371 uint32_t irq;
372 char *name;
373 int node;
374
375 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
376 io_regs[1] = cpu_to_be32(io_base);
377
378 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
379
380 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
381 node = fdt_add_subnode(fdt, lpc_off, name);
382 _FDT(node);
383 g_free(name);
384
385 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
386 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
387 sizeof(compatible))));
388
389 /* Mark it as reserved to avoid Linux trying to claim it */
390 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
391 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
392 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
393 fdt_get_phandle(fdt, lpc_off))));
394 }
395
396 typedef struct ForeachPopulateArgs {
397 void *fdt;
398 int offset;
399 } ForeachPopulateArgs;
400
401 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
402 {
403 ForeachPopulateArgs *args = opaque;
404 ISADevice *d = ISA_DEVICE(dev);
405
406 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
407 pnv_dt_rtc(d, args->fdt, args->offset);
408 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
409 pnv_dt_serial(d, args->fdt, args->offset);
410 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
411 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
412 } else {
413 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
414 d->ioport_id);
415 }
416
417 return 0;
418 }
419
420 /* The default LPC bus of a multichip system is on chip 0. It's
421 * recognized by the firmware (skiboot) using a "primary" property.
422 */
423 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
424 {
425 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
426 ForeachPopulateArgs args = {
427 .fdt = fdt,
428 .offset = isa_offset,
429 };
430
431 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
432
433 /* ISA devices are not necessarily parented to the ISA bus so we
434 * can not use object_child_foreach() */
435 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
436 &args);
437 }
438
439 static void *pnv_dt_create(MachineState *machine)
440 {
441 const char plat_compat[] = "qemu,powernv\0ibm,powernv";
442 PnvMachineState *pnv = PNV_MACHINE(machine);
443 void *fdt;
444 char *buf;
445 int off;
446 int i;
447
448 fdt = g_malloc0(FDT_MAX_SIZE);
449 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
450
451 /* Root node */
452 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
453 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
454 _FDT((fdt_setprop_string(fdt, 0, "model",
455 "IBM PowerNV (emulated by qemu)")));
456 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat,
457 sizeof(plat_compat))));
458
459 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
460 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
461 if (qemu_uuid_set) {
462 _FDT((fdt_property_string(fdt, "system-id", buf)));
463 }
464 g_free(buf);
465
466 off = fdt_add_subnode(fdt, 0, "chosen");
467 if (machine->kernel_cmdline) {
468 _FDT((fdt_setprop_string(fdt, off, "bootargs",
469 machine->kernel_cmdline)));
470 }
471
472 if (pnv->initrd_size) {
473 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
474 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
475
476 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
477 &start_prop, sizeof(start_prop))));
478 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
479 &end_prop, sizeof(end_prop))));
480 }
481
482 /* Populate device tree for each chip */
483 for (i = 0; i < pnv->num_chips; i++) {
484 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
485 }
486
487 /* Populate ISA devices on chip 0 */
488 pnv_dt_isa(pnv, fdt);
489
490 if (pnv->bmc) {
491 pnv_dt_bmc_sensors(pnv->bmc, fdt);
492 }
493
494 return fdt;
495 }
496
497 static void pnv_powerdown_notify(Notifier *n, void *opaque)
498 {
499 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
500
501 if (pnv->bmc) {
502 pnv_bmc_powerdown(pnv->bmc);
503 }
504 }
505
506 static void pnv_reset(void)
507 {
508 MachineState *machine = MACHINE(qdev_get_machine());
509 PnvMachineState *pnv = PNV_MACHINE(machine);
510 void *fdt;
511 Object *obj;
512
513 qemu_devices_reset();
514
515 /* OpenPOWER systems have a BMC, which can be defined on the
516 * command line with:
517 *
518 * -device ipmi-bmc-sim,id=bmc0
519 *
520 * This is the internal simulator but it could also be an external
521 * BMC.
522 */
523 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL);
524 if (obj) {
525 pnv->bmc = IPMI_BMC(obj);
526 }
527
528 fdt = pnv_dt_create(machine);
529
530 /* Pack resulting tree */
531 _FDT((fdt_pack(fdt)));
532
533 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
534 }
535
536 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
537 {
538 Pnv8Chip *chip8 = PNV8_CHIP(chip);
539 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
540 }
541
542 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
543 {
544 Pnv8Chip *chip8 = PNV8_CHIP(chip);
545 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
546 }
547
548 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
549 {
550 return NULL;
551 }
552
553 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
554 {
555 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
556 }
557
558 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
559 {
560 Pnv8Chip *chip8 = PNV8_CHIP(chip);
561
562 ics_pic_print_info(&chip8->psi.ics, mon);
563 }
564
565 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
566 {
567 Pnv9Chip *chip9 = PNV9_CHIP(chip);
568
569 pnv_xive_pic_print_info(&chip9->xive, mon);
570 pnv_psi_pic_print_info(&chip9->psi, mon);
571 }
572
573 static void pnv_init(MachineState *machine)
574 {
575 PnvMachineState *pnv = PNV_MACHINE(machine);
576 MemoryRegion *ram;
577 char *fw_filename;
578 long fw_size;
579 int i;
580 char *chip_typename;
581
582 /* allocate RAM */
583 if (machine->ram_size < (1 * GiB)) {
584 warn_report("skiboot may not work with < 1GB of RAM");
585 }
586
587 ram = g_new(MemoryRegion, 1);
588 memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
589 machine->ram_size);
590 memory_region_add_subregion(get_system_memory(), 0, ram);
591
592 /* load skiboot firmware */
593 if (bios_name == NULL) {
594 bios_name = FW_FILE_NAME;
595 }
596
597 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
598 if (!fw_filename) {
599 error_report("Could not find OPAL firmware '%s'", bios_name);
600 exit(1);
601 }
602
603 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
604 if (fw_size < 0) {
605 error_report("Could not load OPAL firmware '%s'", fw_filename);
606 exit(1);
607 }
608 g_free(fw_filename);
609
610 /* load kernel */
611 if (machine->kernel_filename) {
612 long kernel_size;
613
614 kernel_size = load_image_targphys(machine->kernel_filename,
615 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
616 if (kernel_size < 0) {
617 error_report("Could not load kernel '%s'",
618 machine->kernel_filename);
619 exit(1);
620 }
621 }
622
623 /* load initrd */
624 if (machine->initrd_filename) {
625 pnv->initrd_base = INITRD_LOAD_ADDR;
626 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
627 pnv->initrd_base, INITRD_MAX_SIZE);
628 if (pnv->initrd_size < 0) {
629 error_report("Could not load initial ram disk '%s'",
630 machine->initrd_filename);
631 exit(1);
632 }
633 }
634
635 /* Create the processor chips */
636 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
637 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
638 i, machine->cpu_type);
639 if (!object_class_by_name(chip_typename)) {
640 error_report("invalid CPU model '%.*s' for %s machine",
641 i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name);
642 exit(1);
643 }
644
645 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
646 for (i = 0; i < pnv->num_chips; i++) {
647 char chip_name[32];
648 Object *chip = object_new(chip_typename);
649
650 pnv->chips[i] = PNV_CHIP(chip);
651
652 /* TODO: put all the memory in one node on chip 0 until we find a
653 * way to specify different ranges for each chip
654 */
655 if (i == 0) {
656 object_property_set_int(chip, machine->ram_size, "ram-size",
657 &error_fatal);
658 }
659
660 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
661 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
662 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
663 &error_fatal);
664 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
665 object_property_set_bool(chip, true, "realized", &error_fatal);
666 }
667 g_free(chip_typename);
668
669 /* Instantiate ISA bus on chip 0 */
670 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
671
672 /* Create serial port */
673 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
674
675 /* Create an RTC ISA device too */
676 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
677
678 /* OpenPOWER systems use a IPMI SEL Event message to notify the
679 * host to powerdown */
680 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
681 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
682 }
683
684 /*
685 * 0:21 Reserved - Read as zeros
686 * 22:24 Chip ID
687 * 25:28 Core number
688 * 29:31 Thread ID
689 */
690 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
691 {
692 return (chip->chip_id << 7) | (core_id << 3);
693 }
694
695 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
696 Error **errp)
697 {
698 Error *local_err = NULL;
699 Object *obj;
700 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
701
702 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
703 &local_err);
704 if (local_err) {
705 error_propagate(errp, local_err);
706 return;
707 }
708
709 pnv_cpu->intc = obj;
710 }
711
712 /*
713 * 0:48 Reserved - Read as zeroes
714 * 49:52 Node ID
715 * 53:55 Chip ID
716 * 56 Reserved - Read as zero
717 * 57:61 Core number
718 * 62:63 Thread ID
719 *
720 * We only care about the lower bits. uint32_t is fine for the moment.
721 */
722 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
723 {
724 return (chip->chip_id << 8) | (core_id << 2);
725 }
726
727 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
728 Error **errp)
729 {
730 Pnv9Chip *chip9 = PNV9_CHIP(chip);
731 Error *local_err = NULL;
732 Object *obj;
733 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
734
735 /*
736 * The core creates its interrupt presenter but the XIVE interrupt
737 * controller object is initialized afterwards. Hopefully, it's
738 * only used at runtime.
739 */
740 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), errp);
741 if (local_err) {
742 error_propagate(errp, local_err);
743 return;
744 }
745
746 pnv_cpu->intc = obj;
747 }
748
749 /* Allowed core identifiers on a POWER8 Processor Chip :
750 *
751 * <EX0 reserved>
752 * EX1 - Venice only
753 * EX2 - Venice only
754 * EX3 - Venice only
755 * EX4
756 * EX5
757 * EX6
758 * <EX7,8 reserved> <reserved>
759 * EX9 - Venice only
760 * EX10 - Venice only
761 * EX11 - Venice only
762 * EX12
763 * EX13
764 * EX14
765 * <EX15 reserved>
766 */
767 #define POWER8E_CORE_MASK (0x7070ull)
768 #define POWER8_CORE_MASK (0x7e7eull)
769
770 /*
771 * POWER9 has 24 cores, ids starting at 0x0
772 */
773 #define POWER9_CORE_MASK (0xffffffffffffffull)
774
775 static void pnv_chip_power8_instance_init(Object *obj)
776 {
777 Pnv8Chip *chip8 = PNV8_CHIP(obj);
778
779 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
780 TYPE_PNV8_PSI, &error_abort, NULL);
781 object_property_add_const_link(OBJECT(&chip8->psi), "xics",
782 OBJECT(qdev_get_machine()), &error_abort);
783
784 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
785 TYPE_PNV8_LPC, &error_abort, NULL);
786 object_property_add_const_link(OBJECT(&chip8->lpc), "psi",
787 OBJECT(&chip8->psi), &error_abort);
788
789 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
790 TYPE_PNV_OCC, &error_abort, NULL);
791 object_property_add_const_link(OBJECT(&chip8->occ), "psi",
792 OBJECT(&chip8->psi), &error_abort);
793 }
794
795 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
796 {
797 PnvChip *chip = PNV_CHIP(chip8);
798 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
799 const char *typename = pnv_chip_core_typename(chip);
800 size_t typesize = object_type_get_instance_size(typename);
801 int i, j;
802 char *name;
803 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
804
805 name = g_strdup_printf("icp-%x", chip->chip_id);
806 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
807 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
808 g_free(name);
809
810 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
811
812 /* Map the ICP registers for each thread */
813 for (i = 0; i < chip->nr_cores; i++) {
814 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
815 int core_hwid = CPU_CORE(pnv_core)->core_id;
816
817 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
818 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
819 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
820
821 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
822 &icp->mmio);
823 }
824 }
825 }
826
827 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
828 {
829 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
830 PnvChip *chip = PNV_CHIP(dev);
831 Pnv8Chip *chip8 = PNV8_CHIP(dev);
832 Pnv8Psi *psi8 = &chip8->psi;
833 Error *local_err = NULL;
834
835 pcc->parent_realize(dev, &local_err);
836 if (local_err) {
837 error_propagate(errp, local_err);
838 return;
839 }
840
841 /* Processor Service Interface (PSI) Host Bridge */
842 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
843 "bar", &error_fatal);
844 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
845 if (local_err) {
846 error_propagate(errp, local_err);
847 return;
848 }
849 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
850 &PNV_PSI(psi8)->xscom_regs);
851
852 /* Create LPC controller */
853 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
854 &error_fatal);
855 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
856
857 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
858 (uint64_t) PNV_XSCOM_BASE(chip),
859 PNV_XSCOM_LPC_BASE);
860
861 /* Interrupt Management Area. This is the memory region holding
862 * all the Interrupt Control Presenter (ICP) registers */
863 pnv_chip_icp_realize(chip8, &local_err);
864 if (local_err) {
865 error_propagate(errp, local_err);
866 return;
867 }
868
869 /* Create the simplified OCC model */
870 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
871 if (local_err) {
872 error_propagate(errp, local_err);
873 return;
874 }
875 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
876 }
877
878 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
879 {
880 DeviceClass *dc = DEVICE_CLASS(klass);
881 PnvChipClass *k = PNV_CHIP_CLASS(klass);
882
883 k->chip_type = PNV_CHIP_POWER8E;
884 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
885 k->cores_mask = POWER8E_CORE_MASK;
886 k->core_pir = pnv_chip_core_pir_p8;
887 k->intc_create = pnv_chip_power8_intc_create;
888 k->isa_create = pnv_chip_power8_isa_create;
889 k->dt_populate = pnv_chip_power8_dt_populate;
890 k->pic_print_info = pnv_chip_power8_pic_print_info;
891 k->xscom_base = 0x003fc0000000000ull;
892 dc->desc = "PowerNV Chip POWER8E";
893
894 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
895 &k->parent_realize);
896 }
897
898 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
899 {
900 DeviceClass *dc = DEVICE_CLASS(klass);
901 PnvChipClass *k = PNV_CHIP_CLASS(klass);
902
903 k->chip_type = PNV_CHIP_POWER8;
904 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
905 k->cores_mask = POWER8_CORE_MASK;
906 k->core_pir = pnv_chip_core_pir_p8;
907 k->intc_create = pnv_chip_power8_intc_create;
908 k->isa_create = pnv_chip_power8_isa_create;
909 k->dt_populate = pnv_chip_power8_dt_populate;
910 k->pic_print_info = pnv_chip_power8_pic_print_info;
911 k->xscom_base = 0x003fc0000000000ull;
912 dc->desc = "PowerNV Chip POWER8";
913
914 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
915 &k->parent_realize);
916 }
917
918 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
919 {
920 DeviceClass *dc = DEVICE_CLASS(klass);
921 PnvChipClass *k = PNV_CHIP_CLASS(klass);
922
923 k->chip_type = PNV_CHIP_POWER8NVL;
924 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
925 k->cores_mask = POWER8_CORE_MASK;
926 k->core_pir = pnv_chip_core_pir_p8;
927 k->intc_create = pnv_chip_power8_intc_create;
928 k->isa_create = pnv_chip_power8nvl_isa_create;
929 k->dt_populate = pnv_chip_power8_dt_populate;
930 k->pic_print_info = pnv_chip_power8_pic_print_info;
931 k->xscom_base = 0x003fc0000000000ull;
932 dc->desc = "PowerNV Chip POWER8NVL";
933
934 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
935 &k->parent_realize);
936 }
937
938 static void pnv_chip_power9_instance_init(Object *obj)
939 {
940 Pnv9Chip *chip9 = PNV9_CHIP(obj);
941
942 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive),
943 TYPE_PNV_XIVE, &error_abort, NULL);
944 object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj,
945 &error_abort);
946
947 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
948 TYPE_PNV9_PSI, &error_abort, NULL);
949 object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj,
950 &error_abort);
951 }
952
953 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
954 {
955 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
956 Pnv9Chip *chip9 = PNV9_CHIP(dev);
957 PnvChip *chip = PNV_CHIP(dev);
958 Pnv9Psi *psi9 = &chip9->psi;
959 Error *local_err = NULL;
960
961 pcc->parent_realize(dev, &local_err);
962 if (local_err) {
963 error_propagate(errp, local_err);
964 return;
965 }
966
967 /* XIVE interrupt controller (POWER9) */
968 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip),
969 "ic-bar", &error_fatal);
970 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip),
971 "vc-bar", &error_fatal);
972 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip),
973 "pc-bar", &error_fatal);
974 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip),
975 "tm-bar", &error_fatal);
976 object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
977 &local_err);
978 if (local_err) {
979 error_propagate(errp, local_err);
980 return;
981 }
982 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
983 &chip9->xive.xscom_regs);
984
985 /* Processor Service Interface (PSI) Host Bridge */
986 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
987 "bar", &error_fatal);
988 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
989 if (local_err) {
990 error_propagate(errp, local_err);
991 return;
992 }
993 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
994 &PNV_PSI(psi9)->xscom_regs);
995 }
996
997 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
998 {
999 DeviceClass *dc = DEVICE_CLASS(klass);
1000 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1001
1002 k->chip_type = PNV_CHIP_POWER9;
1003 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1004 k->cores_mask = POWER9_CORE_MASK;
1005 k->core_pir = pnv_chip_core_pir_p9;
1006 k->intc_create = pnv_chip_power9_intc_create;
1007 k->isa_create = pnv_chip_power9_isa_create;
1008 k->dt_populate = pnv_chip_power9_dt_populate;
1009 k->pic_print_info = pnv_chip_power9_pic_print_info;
1010 k->xscom_base = 0x00603fc00000000ull;
1011 dc->desc = "PowerNV Chip POWER9";
1012
1013 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1014 &k->parent_realize);
1015 }
1016
1017 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1018 {
1019 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1020 int cores_max;
1021
1022 /*
1023 * No custom mask for this chip, let's use the default one from *
1024 * the chip class
1025 */
1026 if (!chip->cores_mask) {
1027 chip->cores_mask = pcc->cores_mask;
1028 }
1029
1030 /* filter alien core ids ! some are reserved */
1031 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1032 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1033 chip->cores_mask);
1034 return;
1035 }
1036 chip->cores_mask &= pcc->cores_mask;
1037
1038 /* now that we have a sane layout, let check the number of cores */
1039 cores_max = ctpop64(chip->cores_mask);
1040 if (chip->nr_cores > cores_max) {
1041 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1042 cores_max);
1043 return;
1044 }
1045 }
1046
1047 static void pnv_chip_instance_init(Object *obj)
1048 {
1049 PNV_CHIP(obj)->xscom_base = PNV_CHIP_GET_CLASS(obj)->xscom_base;
1050 }
1051
1052 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1053 {
1054 Error *error = NULL;
1055 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1056 const char *typename = pnv_chip_core_typename(chip);
1057 size_t typesize = object_type_get_instance_size(typename);
1058 int i, core_hwid;
1059
1060 if (!object_class_by_name(typename)) {
1061 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1062 return;
1063 }
1064
1065 /* Cores */
1066 pnv_chip_core_sanitize(chip, &error);
1067 if (error) {
1068 error_propagate(errp, error);
1069 return;
1070 }
1071
1072 chip->cores = g_malloc0(typesize * chip->nr_cores);
1073
1074 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1075 && (i < chip->nr_cores); core_hwid++) {
1076 char core_name[32];
1077 void *pnv_core = chip->cores + i * typesize;
1078 uint64_t xscom_core_base;
1079
1080 if (!(chip->cores_mask & (1ull << core_hwid))) {
1081 continue;
1082 }
1083
1084 object_initialize(pnv_core, typesize, typename);
1085 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1086 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
1087 &error_fatal);
1088 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
1089 &error_fatal);
1090 object_property_set_int(OBJECT(pnv_core), core_hwid,
1091 CPU_CORE_PROP_CORE_ID, &error_fatal);
1092 object_property_set_int(OBJECT(pnv_core),
1093 pcc->core_pir(chip, core_hwid),
1094 "pir", &error_fatal);
1095 object_property_add_const_link(OBJECT(pnv_core), "chip",
1096 OBJECT(chip), &error_fatal);
1097 object_property_set_bool(OBJECT(pnv_core), true, "realized",
1098 &error_fatal);
1099 object_unref(OBJECT(pnv_core));
1100
1101 /* Each core has an XSCOM MMIO region */
1102 if (!pnv_chip_is_power9(chip)) {
1103 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
1104 } else {
1105 xscom_core_base = PNV_XSCOM_P9_EC_BASE(core_hwid);
1106 }
1107
1108 pnv_xscom_add_subregion(chip, xscom_core_base,
1109 &PNV_CORE(pnv_core)->xscom_regs);
1110 i++;
1111 }
1112 }
1113
1114 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1115 {
1116 PnvChip *chip = PNV_CHIP(dev);
1117 Error *error = NULL;
1118
1119 /* XSCOM bridge */
1120 pnv_xscom_realize(chip, &error);
1121 if (error) {
1122 error_propagate(errp, error);
1123 return;
1124 }
1125 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1126
1127 /* Cores */
1128 pnv_chip_core_realize(chip, &error);
1129 if (error) {
1130 error_propagate(errp, error);
1131 return;
1132 }
1133 }
1134
1135 static Property pnv_chip_properties[] = {
1136 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1137 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1138 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1139 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1140 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1141 DEFINE_PROP_END_OF_LIST(),
1142 };
1143
1144 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1145 {
1146 DeviceClass *dc = DEVICE_CLASS(klass);
1147
1148 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1149 dc->realize = pnv_chip_realize;
1150 dc->props = pnv_chip_properties;
1151 dc->desc = "PowerNV Chip";
1152 }
1153
1154 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1155 {
1156 PnvMachineState *pnv = PNV_MACHINE(xi);
1157 int i;
1158
1159 for (i = 0; i < pnv->num_chips; i++) {
1160 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1161
1162 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1163 return &chip8->psi.ics;
1164 }
1165 }
1166 return NULL;
1167 }
1168
1169 static void pnv_ics_resend(XICSFabric *xi)
1170 {
1171 PnvMachineState *pnv = PNV_MACHINE(xi);
1172 int i;
1173
1174 for (i = 0; i < pnv->num_chips; i++) {
1175 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1176 ics_resend(&chip8->psi.ics);
1177 }
1178 }
1179
1180 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1181 {
1182 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1183
1184 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
1185 }
1186
1187 static void pnv_pic_print_info(InterruptStatsProvider *obj,
1188 Monitor *mon)
1189 {
1190 PnvMachineState *pnv = PNV_MACHINE(obj);
1191 int i;
1192 CPUState *cs;
1193
1194 CPU_FOREACH(cs) {
1195 PowerPCCPU *cpu = POWERPC_CPU(cs);
1196
1197 if (pnv_chip_is_power9(pnv->chips[0])) {
1198 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1199 } else {
1200 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
1201 }
1202 }
1203
1204 for (i = 0; i < pnv->num_chips; i++) {
1205 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
1206 }
1207 }
1208
1209 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
1210 void *opaque, Error **errp)
1211 {
1212 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp);
1213 }
1214
1215 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
1216 void *opaque, Error **errp)
1217 {
1218 PnvMachineState *pnv = PNV_MACHINE(obj);
1219 uint32_t num_chips;
1220 Error *local_err = NULL;
1221
1222 visit_type_uint32(v, name, &num_chips, &local_err);
1223 if (local_err) {
1224 error_propagate(errp, local_err);
1225 return;
1226 }
1227
1228 /*
1229 * TODO: should we decide on how many chips we can create based
1230 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1231 */
1232 if (!is_power_of_2(num_chips) || num_chips > 4) {
1233 error_setg(errp, "invalid number of chips: '%d'", num_chips);
1234 return;
1235 }
1236
1237 pnv->num_chips = num_chips;
1238 }
1239
1240 static void pnv_machine_instance_init(Object *obj)
1241 {
1242 PnvMachineState *pnv = PNV_MACHINE(obj);
1243 pnv->num_chips = 1;
1244 }
1245
1246 static void pnv_machine_class_props_init(ObjectClass *oc)
1247 {
1248 object_class_property_add(oc, "num-chips", "uint32",
1249 pnv_get_num_chips, pnv_set_num_chips,
1250 NULL, NULL, NULL);
1251 object_class_property_set_description(oc, "num-chips",
1252 "Specifies the number of processor chips",
1253 NULL);
1254 }
1255
1256 static void pnv_machine_class_init(ObjectClass *oc, void *data)
1257 {
1258 MachineClass *mc = MACHINE_CLASS(oc);
1259 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1260 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
1261
1262 mc->desc = "IBM PowerNV (Non-Virtualized)";
1263 mc->init = pnv_init;
1264 mc->reset = pnv_reset;
1265 mc->max_cpus = MAX_CPUS;
1266 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1267 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
1268 * storage */
1269 mc->no_parallel = 1;
1270 mc->default_boot_order = NULL;
1271 mc->default_ram_size = 1 * GiB;
1272 xic->icp_get = pnv_icp_get;
1273 xic->ics_get = pnv_ics_get;
1274 xic->ics_resend = pnv_ics_resend;
1275 ispc->print_info = pnv_pic_print_info;
1276
1277 pnv_machine_class_props_init(oc);
1278 }
1279
1280 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1281 { \
1282 .name = type, \
1283 .class_init = class_initfn, \
1284 .parent = TYPE_PNV8_CHIP, \
1285 }
1286
1287 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1288 { \
1289 .name = type, \
1290 .class_init = class_initfn, \
1291 .parent = TYPE_PNV9_CHIP, \
1292 }
1293
1294 static const TypeInfo types[] = {
1295 {
1296 .name = TYPE_PNV_MACHINE,
1297 .parent = TYPE_MACHINE,
1298 .instance_size = sizeof(PnvMachineState),
1299 .instance_init = pnv_machine_instance_init,
1300 .class_init = pnv_machine_class_init,
1301 .interfaces = (InterfaceInfo[]) {
1302 { TYPE_XICS_FABRIC },
1303 { TYPE_INTERRUPT_STATS_PROVIDER },
1304 { },
1305 },
1306 },
1307 {
1308 .name = TYPE_PNV_CHIP,
1309 .parent = TYPE_SYS_BUS_DEVICE,
1310 .class_init = pnv_chip_class_init,
1311 .instance_init = pnv_chip_instance_init,
1312 .instance_size = sizeof(PnvChip),
1313 .class_size = sizeof(PnvChipClass),
1314 .abstract = true,
1315 },
1316
1317 /*
1318 * P9 chip and variants
1319 */
1320 {
1321 .name = TYPE_PNV9_CHIP,
1322 .parent = TYPE_PNV_CHIP,
1323 .instance_init = pnv_chip_power9_instance_init,
1324 .instance_size = sizeof(Pnv9Chip),
1325 },
1326 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
1327
1328 /*
1329 * P8 chip and variants
1330 */
1331 {
1332 .name = TYPE_PNV8_CHIP,
1333 .parent = TYPE_PNV_CHIP,
1334 .instance_init = pnv_chip_power8_instance_init,
1335 .instance_size = sizeof(Pnv8Chip),
1336 },
1337 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
1338 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
1339 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
1340 pnv_chip_power8nvl_class_init),
1341 };
1342
1343 DEFINE_TYPES(types)
AR7 emulation for QEMU