hw/arm/xlnx-zynqmp.c

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "hw/arm/xlnx-zynqmp.h"
  19 #include "hw/intc/arm_gic_common.h"
  20 #include "exec/address-spaces.h"
  21
  22 #define GIC_NUM_SPI_INTR 160
  23
  24 #define ARM_PHYS_TIMER_PPI  30
  25 #define ARM_VIRT_TIMER_PPI  27
  26
  27 #define GIC_BASE_ADDR       0xf9000000
  28 #define GIC_DIST_ADDR       0xf9010000
  29 #define GIC_CPU_ADDR        0xf9020000
  30
  31 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  32     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  33 };
  34
  35 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  36     57, 59, 61, 63,
  37 };
  38
  39 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  40     0xFF000000, 0xFF010000,
  41 };
  42
  43 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  44     21, 22,
  45 };
  46
  47 typedef struct XlnxZynqMPGICRegion {
  48     int region_index;
  49     uint32_t address;
  50 } XlnxZynqMPGICRegion;
  51
  52 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
  53     { .region_index = 0, .address = GIC_DIST_ADDR, },
  54     { .region_index = 1, .address = GIC_CPU_ADDR,  },
  55 };
  56
  57 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
  58 {
  59     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
  60 }
  61
  62 static void xlnx_zynqmp_init(Object *obj)
  63 {
  64     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
  65     int i;
  66
  67     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
  68         object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
  69                           "cortex-a53-" TYPE_ARM_CPU);
  70         object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
  71                                   &error_abort);
  72     }
  73
  74     object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
  75     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
  76
  77     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
  78         object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
  79         qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
  80     }
  81
  82     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
  83         object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
  84         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
  85     }
  86 }
  87
  88 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
  89 {
  90     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
  91     MemoryRegion *system_memory = get_system_memory();
  92     uint8_t i;
  93     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
  94     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
  95     Error *err = NULL;
  96
  97     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
  98     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
  99     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
 100     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
 101     if (err) {
 102         error_propagate((errp), (err));
 103         return;
 104     }
 105     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
 106     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
 107         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
 108         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
 109         MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
 110         uint32_t addr = r->address;
 111         int j;
 112
 113         sysbus_mmio_map(gic, r->region_index, addr);
 114
 115         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
 116             MemoryRegion *alias = &s->gic_mr[i][j];
 117
 118             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
 119             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
 120                                      0, XLNX_ZYNQMP_GIC_REGION_SIZE);
 121             memory_region_add_subregion(system_memory, addr, alias);
 122         }
 123     }
 124
 125     for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
 126         qemu_irq irq;
 127         char *name;
 128
 129         object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
 130                                 "psci-conduit", &error_abort);
 131
 132         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
 133         if (strcmp(name, boot_cpu)) {
 134             /* Secondary CPUs start in PSCI powered-down state */
 135             object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
 136                                      "start-powered-off", &error_abort);
 137         } else {
 138             s->boot_cpu_ptr = &s->apu_cpu[i];
 139         }
 140
 141         object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
 142                                 "reset-cbar", &err);
 143         if (err) {
 144             error_propagate((errp), (err));
 145             return;
 146         }
 147
 148         object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
 149                                  &err);
 150         if (err) {
 151             error_propagate((errp), (err));
 152             return;
 153         }
 154
 155         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
 156                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 157                                             ARM_CPU_IRQ));
 158         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 159                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
 160         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
 161         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 162                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
 163         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
 164     }
 165
 166     if (!s->boot_cpu_ptr) {
 167         error_setg(errp, "ZynqMP Boot cpu %s not found\n", boot_cpu);
 168         return;
 169     }
 170
 171     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
 172         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 173     }
 174
 175     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 176         NICInfo *nd = &nd_table[i];
 177
 178         if (nd->used) {
 179             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 180             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
 181         }
 182         object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
 183         if (err) {
 184             error_propagate((errp), (err));
 185             return;
 186         }
 187         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
 188         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
 189                            gic_spi[gem_intr[i]]);
 190     }
 191
 192     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 193         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 194         if (err) {
 195             error_propagate((errp), (err));
 196             return;
 197         }
 198         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
 199         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 200                            gic_spi[uart_intr[i]]);
 201     }
 202 }
 203
 204 static Property xlnx_zynqmp_props[] = {
 205     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
 206     DEFINE_PROP_END_OF_LIST()
 207 };
 208
 209 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 210 {
 211     DeviceClass *dc = DEVICE_CLASS(oc);
 212
 213     dc->props = xlnx_zynqmp_props;
 214     dc->realize = xlnx_zynqmp_realize;
 215 }
 216
 217 static const TypeInfo xlnx_zynqmp_type_info = {
 218     .name = TYPE_XLNX_ZYNQMP,
 219     .parent = TYPE_DEVICE,
 220     .instance_size = sizeof(XlnxZynqMPState),
 221     .instance_init = xlnx_zynqmp_init,
 222     .class_init = xlnx_zynqmp_class_init,
 223 };
 224
 225 static void xlnx_zynqmp_register_types(void)
 226 {
 227     type_register_static(&xlnx_zynqmp_type_info);
 228 }
 229
 230 type_init(xlnx_zynqmp_register_types)