2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu-common.h"
33 #include "qemu/datadir.h"
34 #include "qemu/units.h"
35 #include "qemu/option.h"
36 #include "monitor/qdev.h"
37 #include "qapi/error.h"
38 #include "hw/sysbus.h"
39 #include "hw/boards.h"
40 #include "hw/arm/boot.h"
41 #include "hw/arm/primecell.h"
42 #include "hw/arm/virt.h"
43 #include "hw/block/flash.h"
44 #include "hw/vfio/vfio-calxeda-xgmac.h"
45 #include "hw/vfio/vfio-amd-xgbe.h"
46 #include "hw/display/ramfb.h"
48 #include "sysemu/device_tree.h"
49 #include "sysemu/numa.h"
50 #include "sysemu/runstate.h"
51 #include "sysemu/sysemu.h"
52 #include "sysemu/tpm.h"
53 #include "sysemu/kvm.h"
54 #include "hw/loader.h"
55 #include "exec/address-spaces.h"
56 #include "qemu/bitops.h"
57 #include "qemu/error-report.h"
58 #include "qemu/module.h"
59 #include "hw/pci-host/gpex.h"
60 #include "hw/virtio/virtio-pci.h"
61 #include "hw/arm/sysbus-fdt.h"
62 #include "hw/platform-bus.h"
63 #include "hw/qdev-properties.h"
64 #include "hw/arm/fdt.h"
65 #include "hw/intc/arm_gic.h"
66 #include "hw/intc/arm_gicv3_common.h"
69 #include "hw/firmware/smbios.h"
70 #include "qapi/visitor.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "standard-headers/linux/input.h"
73 #include "hw/arm/smmuv3.h"
74 #include "hw/acpi/acpi.h"
75 #include "target/arm/internals.h"
76 #include "hw/mem/pc-dimm.h"
77 #include "hw/mem/nvdimm.h"
78 #include "hw/acpi/generic_event_device.h"
79 #include "hw/virtio/virtio-iommu.h"
80 #include "hw/char/pl011.h"
81 #include "qemu/guest-random.h"
83 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
84 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
87 MachineClass *mc = MACHINE_CLASS(oc); \
88 virt_machine_##major##_##minor##_options(mc); \
89 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
94 static const TypeInfo machvirt_##major##_##minor##_info = { \
95 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
96 .parent = TYPE_VIRT_MACHINE, \
97 .class_init = virt_##major##_##minor##_class_init, \
99 static void machvirt_machine_##major##_##minor##_init(void) \
101 type_register_static(&machvirt_##major##_##minor##_info); \
103 type_init(machvirt_machine_##major##_##minor##_init);
105 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
106 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
107 #define DEFINE_VIRT_MACHINE(major, minor) \
108 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
111 /* Number of external interrupt lines to configure the GIC with */
114 #define PLATFORM_BUS_NUM_IRQS 64
116 /* Legacy RAM limit in GB (< version 4.0) */
117 #define LEGACY_RAMLIMIT_GB 255
118 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
120 /* Addresses and sizes of our components.
121 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
122 * 128MB..256MB is used for miscellaneous device I/O.
123 * 256MB..1GB is reserved for possible future PCI support (ie where the
124 * PCI memory window will go if we add a PCI host controller).
125 * 1GB and up is RAM (which may happily spill over into the
126 * high memory region beyond 4GB).
127 * This represents a compromise between how much RAM can be given to
128 * a 32 bit VM and leaving space for expansion and in particular for PCI.
129 * Note that devices should generally be placed at multiples of 0x10000,
130 * to accommodate guests using 64K pages.
132 static const MemMapEntry base_memmap
[] = {
133 /* Space up to 0x8000000 is reserved for a boot ROM */
134 [VIRT_FLASH
] = { 0, 0x08000000 },
135 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
136 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
137 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
138 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
139 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
140 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
141 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
142 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
143 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
144 /* This redistributor space allows up to 2*64kB*123 CPUs */
145 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
146 [VIRT_UART
] = { 0x09000000, 0x00001000 },
147 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
148 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
149 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
150 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
151 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
152 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
153 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
154 [VIRT_NVDIMM_ACPI
] = { 0x09090000, NVDIMM_ACPI_IO_LEN
},
155 [VIRT_PVTIME
] = { 0x090a0000, 0x00010000 },
156 [VIRT_SECURE_GPIO
] = { 0x090b0000, 0x00001000 },
157 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
158 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
159 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
160 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
161 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
162 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
163 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
164 /* Actual RAM size depends on initial RAM and device memory settings */
165 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
169 * Highmem IO Regions: This memory map is floating, located after the RAM.
170 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
171 * top of the RAM, so that its base get the same alignment as the size,
172 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
173 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
174 * Note the extended_memmap is sized so that it eventually also includes the
175 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
176 * index of base_memmap).
178 static MemMapEntry extended_memmap
[] = {
179 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
180 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
181 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
182 /* Second PCIe window */
183 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
186 static const int a15irqmap
[] = {
189 [VIRT_PCIE
] = 3, /* ... to 6 */
191 [VIRT_SECURE_UART
] = 8,
193 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
194 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
195 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
196 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
199 static const char *valid_cpus
[] = {
200 ARM_CPU_TYPE_NAME("cortex-a7"),
201 ARM_CPU_TYPE_NAME("cortex-a15"),
202 ARM_CPU_TYPE_NAME("cortex-a53"),
203 ARM_CPU_TYPE_NAME("cortex-a57"),
204 ARM_CPU_TYPE_NAME("cortex-a72"),
205 ARM_CPU_TYPE_NAME("host"),
206 ARM_CPU_TYPE_NAME("max"),
209 static bool cpu_type_valid(const char *cpu
)
213 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
214 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
221 static void create_kaslr_seed(VirtMachineState
*vms
, const char *node
)
225 if (qemu_guest_getrandom(&seed
, sizeof(seed
), NULL
)) {
228 qemu_fdt_setprop_u64(vms
->fdt
, node
, "kaslr-seed", seed
);
231 static void create_fdt(VirtMachineState
*vms
)
233 MachineState
*ms
= MACHINE(vms
);
234 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
235 void *fdt
= create_device_tree(&vms
->fdt_size
);
238 error_report("create_device_tree() failed");
245 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
246 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
247 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
249 /* /chosen must exist for load_dtb to fill in necessary properties later */
250 qemu_fdt_add_subnode(fdt
, "/chosen");
251 create_kaslr_seed(vms
, "/chosen");
254 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
255 create_kaslr_seed(vms
, "/secure-chosen");
258 /* Clock node, for the benefit of the UART. The kernel device tree
259 * binding documentation claims the PL011 node clock properties are
260 * optional but in practice if you omit them the kernel refuses to
261 * probe for the device.
263 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
264 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
265 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
266 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
267 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
268 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
270 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
272 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
273 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
274 uint32_t *matrix
= g_malloc0(size
);
277 for (i
= 0; i
< nb_numa_nodes
; i
++) {
278 for (j
= 0; j
< nb_numa_nodes
; j
++) {
279 idx
= (i
* nb_numa_nodes
+ j
) * 3;
280 matrix
[idx
+ 0] = cpu_to_be32(i
);
281 matrix
[idx
+ 1] = cpu_to_be32(j
);
283 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
287 qemu_fdt_add_subnode(fdt
, "/distance-map");
288 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
289 "numa-distance-map-v1");
290 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
296 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
298 /* On real hardware these interrupts are level-triggered.
299 * On KVM they were edge-triggered before host kernel version 4.4,
300 * and level-triggered afterwards.
301 * On emulated QEMU they are level-triggered.
303 * Getting the DTB info about them wrong is awkward for some
305 * pre-4.8 ignore the DT and leave the interrupt configured
306 * with whatever the GIC reset value (or the bootloader) left it at
307 * 4.8 before rc6 honour the incorrect data by programming it back
308 * into the GIC, causing problems
309 * 4.8rc6 and later ignore the DT and always write "level triggered"
312 * For backwards-compatibility, virt-2.8 and earlier will continue
313 * to say these are edge-triggered, but later machines will report
314 * the correct information.
317 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
318 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
320 if (vmc
->claim_edge_triggered_timers
) {
321 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
324 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
325 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
326 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
327 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
330 qemu_fdt_add_subnode(vms
->fdt
, "/timer");
332 armcpu
= ARM_CPU(qemu_get_cpu(0));
333 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
334 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
335 qemu_fdt_setprop(vms
->fdt
, "/timer", "compatible",
336 compat
, sizeof(compat
));
338 qemu_fdt_setprop_string(vms
->fdt
, "/timer", "compatible",
341 qemu_fdt_setprop(vms
->fdt
, "/timer", "always-on", NULL
, 0);
342 qemu_fdt_setprop_cells(vms
->fdt
, "/timer", "interrupts",
343 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
344 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
345 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
346 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
349 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
353 const MachineState
*ms
= MACHINE(vms
);
354 int smp_cpus
= ms
->smp
.cpus
;
357 * From Documentation/devicetree/bindings/arm/cpus.txt
358 * On ARM v8 64-bit systems value should be set to 2,
359 * that corresponds to the MPIDR_EL1 register size.
360 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
361 * in the system, #address-cells can be set to 1, since
362 * MPIDR_EL1[63:32] bits are not used for CPUs
365 * Here we actually don't know whether our system is 32- or 64-bit one.
366 * The simplest way to go is to examine affinity IDs of all our CPUs. If
367 * at least one of them has Aff3 populated, we set #address-cells to 2.
369 for (cpu
= 0; cpu
< smp_cpus
; cpu
++) {
370 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
372 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
378 qemu_fdt_add_subnode(vms
->fdt
, "/cpus");
379 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#address-cells", addr_cells
);
380 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#size-cells", 0x0);
382 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
383 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
384 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
385 CPUState
*cs
= CPU(armcpu
);
387 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
388 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "cpu");
389 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
390 armcpu
->dtb_compatible
);
392 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
&& smp_cpus
> 1) {
393 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
394 "enable-method", "psci");
397 if (addr_cells
== 2) {
398 qemu_fdt_setprop_u64(vms
->fdt
, nodename
, "reg",
399 armcpu
->mp_affinity
);
401 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "reg",
402 armcpu
->mp_affinity
);
405 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
406 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "numa-node-id",
407 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
414 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
418 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
419 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
420 vms
->memmap
[VIRT_GIC_ITS
].base
);
421 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
422 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
424 qemu_fdt_setprop(vms
->fdt
, nodename
, "msi-controller", NULL
, 0);
425 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
426 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
427 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
428 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
432 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
436 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
437 vms
->memmap
[VIRT_GIC_V2M
].base
);
438 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
439 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
440 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
441 "arm,gic-v2m-frame");
442 qemu_fdt_setprop(vms
->fdt
, nodename
, "msi-controller", NULL
, 0);
443 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
444 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
445 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
446 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
450 static void fdt_add_gic_node(VirtMachineState
*vms
)
454 vms
->gic_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
455 qemu_fdt_setprop_cell(vms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
457 nodename
= g_strdup_printf("/intc@%" PRIx64
,
458 vms
->memmap
[VIRT_GIC_DIST
].base
);
459 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
460 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 3);
461 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
462 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 0x2);
463 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 0x2);
464 qemu_fdt_setprop(vms
->fdt
, nodename
, "ranges", NULL
, 0);
465 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
466 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
468 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
471 qemu_fdt_setprop_cell(vms
->fdt
, nodename
,
472 "#redistributor-regions", nb_redist_regions
);
474 if (nb_redist_regions
== 1) {
475 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
476 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
477 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
478 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
479 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
481 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
482 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
483 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
484 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
485 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
486 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
487 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
491 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
492 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
493 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
496 /* 'cortex-a15-gic' means 'GIC v2' */
497 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
498 "arm,cortex-a15-gic");
500 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
501 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
502 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
503 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
504 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
506 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
507 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
508 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
509 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
510 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
511 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
512 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
513 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
514 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
515 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
516 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
517 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
521 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
525 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
527 ARMCPU
*armcpu
= ARM_CPU(first_cpu
);
528 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
530 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
531 assert(!object_property_get_bool(OBJECT(armcpu
), "pmu", NULL
));
535 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
536 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
537 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
538 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
541 qemu_fdt_add_subnode(vms
->fdt
, "/pmu");
542 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
543 const char compat
[] = "arm,armv8-pmuv3";
544 qemu_fdt_setprop(vms
->fdt
, "/pmu", "compatible",
545 compat
, sizeof(compat
));
546 qemu_fdt_setprop_cells(vms
->fdt
, "/pmu", "interrupts",
547 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
551 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
554 MachineState
*ms
= MACHINE(vms
);
555 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
556 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
559 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
562 if (ms
->nvdimms_state
->is_enabled
) {
563 event
|= ACPI_GED_NVDIMM_HOTPLUG_EVT
;
566 dev
= qdev_new(TYPE_ACPI_GED
);
567 qdev_prop_set_uint32(dev
, "ged-event", event
);
569 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
570 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
571 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
573 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
578 static void create_its(VirtMachineState
*vms
)
580 const char *itsclass
= its_class_name();
584 /* Do nothing if not supported */
588 dev
= qdev_new(itsclass
);
590 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(vms
->gic
),
592 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
593 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
595 fdt_add_its_gic_node(vms
);
596 vms
->msi_controller
= VIRT_MSI_CTRL_ITS
;
599 static void create_v2m(VirtMachineState
*vms
)
602 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
605 dev
= qdev_new("arm-gicv2m");
606 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
607 qdev_prop_set_uint32(dev
, "base-spi", irq
);
608 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
609 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
611 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
612 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
613 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
616 fdt_add_v2m_gic_node(vms
);
617 vms
->msi_controller
= VIRT_MSI_CTRL_GICV2M
;
620 static void create_gic(VirtMachineState
*vms
)
622 MachineState
*ms
= MACHINE(vms
);
623 /* We create a standalone GIC */
624 SysBusDevice
*gicbusdev
;
626 int type
= vms
->gic_version
, i
;
627 unsigned int smp_cpus
= ms
->smp
.cpus
;
628 uint32_t nb_redist_regions
= 0;
630 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
632 vms
->gic
= qdev_new(gictype
);
633 qdev_prop_set_uint32(vms
->gic
, "revision", type
);
634 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
635 /* Note that the num-irq property counts both internal and external
636 * interrupts; there are always 32 of the former (mandated by GIC spec).
638 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
639 if (!kvm_irqchip_in_kernel()) {
640 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
644 uint32_t redist0_capacity
=
645 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
646 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
648 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
650 qdev_prop_set_uint32(vms
->gic
, "len-redist-region-count",
652 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[0]", redist0_count
);
654 if (nb_redist_regions
== 2) {
655 uint32_t redist1_capacity
=
656 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
658 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[1]",
659 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
662 if (!kvm_irqchip_in_kernel()) {
663 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
667 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
668 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
669 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
671 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
672 if (nb_redist_regions
== 2) {
673 sysbus_mmio_map(gicbusdev
, 2,
674 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
677 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
679 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
680 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
684 /* Wire the outputs from each CPU's generic timer and the GICv3
685 * maintenance interrupt signal to the appropriate GIC PPI inputs,
686 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
688 for (i
= 0; i
< smp_cpus
; i
++) {
689 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
690 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
692 /* Mapping from the output timer irq lines from the CPU to the
693 * GIC PPI inputs we use for the virt board.
695 const int timer_irq
[] = {
696 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
697 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
698 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
699 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
702 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
703 qdev_connect_gpio_out(cpudev
, irq
,
704 qdev_get_gpio_in(vms
->gic
,
705 ppibase
+ timer_irq
[irq
]));
709 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
710 ppibase
+ ARCH_GIC_MAINT_IRQ
);
711 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
713 } else if (vms
->virt
) {
714 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
715 ppibase
+ ARCH_GIC_MAINT_IRQ
);
716 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
719 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
720 qdev_get_gpio_in(vms
->gic
, ppibase
723 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
724 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
725 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
726 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
727 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
728 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
729 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
732 fdt_add_gic_node(vms
);
734 if (type
== 3 && vms
->its
) {
736 } else if (type
== 2) {
741 static void create_uart(const VirtMachineState
*vms
, int uart
,
742 MemoryRegion
*mem
, Chardev
*chr
)
745 hwaddr base
= vms
->memmap
[uart
].base
;
746 hwaddr size
= vms
->memmap
[uart
].size
;
747 int irq
= vms
->irqmap
[uart
];
748 const char compat
[] = "arm,pl011\0arm,primecell";
749 const char clocknames
[] = "uartclk\0apb_pclk";
750 DeviceState
*dev
= qdev_new(TYPE_PL011
);
751 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
753 qdev_prop_set_chr(dev
, "chardev", chr
);
754 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
755 memory_region_add_subregion(mem
, base
,
756 sysbus_mmio_get_region(s
, 0));
757 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
759 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
760 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
761 /* Note that we can't use setprop_string because of the embedded NUL */
762 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible",
763 compat
, sizeof(compat
));
764 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
766 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
767 GIC_FDT_IRQ_TYPE_SPI
, irq
,
768 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
769 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "clocks",
770 vms
->clock_phandle
, vms
->clock_phandle
);
771 qemu_fdt_setprop(vms
->fdt
, nodename
, "clock-names",
772 clocknames
, sizeof(clocknames
));
774 if (uart
== VIRT_UART
) {
775 qemu_fdt_setprop_string(vms
->fdt
, "/chosen", "stdout-path", nodename
);
777 /* Mark as not usable by the normal world */
778 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
779 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
781 qemu_fdt_setprop_string(vms
->fdt
, "/secure-chosen", "stdout-path",
788 static void create_rtc(const VirtMachineState
*vms
)
791 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
792 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
793 int irq
= vms
->irqmap
[VIRT_RTC
];
794 const char compat
[] = "arm,pl031\0arm,primecell";
796 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
798 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
799 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
800 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
801 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
803 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
804 GIC_FDT_IRQ_TYPE_SPI
, irq
,
805 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
806 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
807 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
811 static DeviceState
*gpio_key_dev
;
812 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
814 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
817 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
819 /* use gpio Pin 3 for power button event */
820 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
824 static void create_gpio_keys(const VirtMachineState
*vms
,
825 DeviceState
*pl061_dev
,
828 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
829 qdev_get_gpio_in(pl061_dev
, 3));
831 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys");
832 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
833 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#size-cells", 0);
834 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#address-cells", 1);
836 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys/poweroff");
837 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys/poweroff",
838 "label", "GPIO Key Poweroff");
839 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys/poweroff", "linux,code",
841 qemu_fdt_setprop_cells(vms
->fdt
, "/gpio-keys/poweroff",
842 "gpios", phandle
, 3, 0);
845 #define SECURE_GPIO_POWEROFF 0
846 #define SECURE_GPIO_RESET 1
848 static void create_secure_gpio_pwr(const VirtMachineState
*vms
,
849 DeviceState
*pl061_dev
,
852 DeviceState
*gpio_pwr_dev
;
855 gpio_pwr_dev
= sysbus_create_simple("gpio-pwr", -1, NULL
);
857 /* connect secure pl061 to gpio-pwr */
858 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_RESET
,
859 qdev_get_gpio_in_named(gpio_pwr_dev
, "reset", 0));
860 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_POWEROFF
,
861 qdev_get_gpio_in_named(gpio_pwr_dev
, "shutdown", 0));
863 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-poweroff");
864 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-poweroff", "compatible",
866 qemu_fdt_setprop_cells(vms
->fdt
, "/gpio-poweroff",
867 "gpios", phandle
, SECURE_GPIO_POWEROFF
, 0);
868 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-poweroff", "status", "disabled");
869 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-poweroff", "secure-status",
872 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-restart");
873 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-restart", "compatible",
875 qemu_fdt_setprop_cells(vms
->fdt
, "/gpio-restart",
876 "gpios", phandle
, SECURE_GPIO_RESET
, 0);
877 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-restart", "status", "disabled");
878 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-restart", "secure-status",
882 static void create_gpio_devices(const VirtMachineState
*vms
, int gpio
,
886 DeviceState
*pl061_dev
;
887 hwaddr base
= vms
->memmap
[gpio
].base
;
888 hwaddr size
= vms
->memmap
[gpio
].size
;
889 int irq
= vms
->irqmap
[gpio
];
890 const char compat
[] = "arm,pl061\0arm,primecell";
893 pl061_dev
= qdev_new("pl061");
894 s
= SYS_BUS_DEVICE(pl061_dev
);
895 sysbus_realize_and_unref(s
, &error_fatal
);
896 memory_region_add_subregion(mem
, base
, sysbus_mmio_get_region(s
, 0));
897 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
899 uint32_t phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
900 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
901 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
902 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
904 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
905 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#gpio-cells", 2);
906 qemu_fdt_setprop(vms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
907 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
908 GIC_FDT_IRQ_TYPE_SPI
, irq
,
909 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
910 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
911 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
912 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", phandle
);
914 if (gpio
!= VIRT_GPIO
) {
915 /* Mark as not usable by the normal world */
916 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
917 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
921 /* Child gpio devices */
922 if (gpio
== VIRT_GPIO
) {
923 create_gpio_keys(vms
, pl061_dev
, phandle
);
925 create_secure_gpio_pwr(vms
, pl061_dev
, phandle
);
929 static void create_virtio_devices(const VirtMachineState
*vms
)
932 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
934 /* We create the transports in forwards order. Since qbus_realize()
935 * prepends (not appends) new child buses, the incrementing loop below will
936 * create a list of virtio-mmio buses with decreasing base addresses.
938 * When a -device option is processed from the command line,
939 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
940 * order. The upshot is that -device options in increasing command line
941 * order are mapped to virtio-mmio buses with decreasing base addresses.
943 * When this code was originally written, that arrangement ensured that the
944 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
945 * the first -device on the command line. (The end-to-end order is a
946 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
947 * guest kernel's name-to-address assignment strategy.)
949 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
950 * the message, if not necessarily the code, of commit 70161ff336.
951 * Therefore the loop now establishes the inverse of the original intent.
953 * Unfortunately, we can't counteract the kernel change by reversing the
954 * loop; it would break existing command lines.
956 * In any case, the kernel makes no guarantee about the stability of
957 * enumeration order of virtio devices (as demonstrated by it changing
958 * between kernel versions). For reliable and stable identification
959 * of disks users must use UUIDs or similar mechanisms.
961 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
962 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
963 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
965 sysbus_create_simple("virtio-mmio", base
,
966 qdev_get_gpio_in(vms
->gic
, irq
));
969 /* We add dtb nodes in reverse order so that they appear in the finished
970 * device tree lowest address first.
972 * Note that this mapping is independent of the loop above. The previous
973 * loop influences virtio device to virtio transport assignment, whereas
974 * this loop controls how virtio transports are laid out in the dtb.
976 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
978 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
979 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
981 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
982 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
983 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
984 "compatible", "virtio,mmio");
985 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
987 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
988 GIC_FDT_IRQ_TYPE_SPI
, irq
,
989 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
990 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
995 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
997 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
999 const char *alias_prop_name
)
1002 * Create a single flash device. We use the same parameters as
1003 * the flash devices on the Versatile Express board.
1005 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
1007 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
1008 qdev_prop_set_uint8(dev
, "width", 4);
1009 qdev_prop_set_uint8(dev
, "device-width", 2);
1010 qdev_prop_set_bit(dev
, "big-endian", false);
1011 qdev_prop_set_uint16(dev
, "id0", 0x89);
1012 qdev_prop_set_uint16(dev
, "id1", 0x18);
1013 qdev_prop_set_uint16(dev
, "id2", 0x00);
1014 qdev_prop_set_uint16(dev
, "id3", 0x00);
1015 qdev_prop_set_string(dev
, "name", name
);
1016 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
));
1017 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
1018 OBJECT(dev
), "drive");
1019 return PFLASH_CFI01(dev
);
1022 static void virt_flash_create(VirtMachineState
*vms
)
1024 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
1025 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
1028 static void virt_flash_map1(PFlashCFI01
*flash
,
1029 hwaddr base
, hwaddr size
,
1030 MemoryRegion
*sysmem
)
1032 DeviceState
*dev
= DEVICE(flash
);
1034 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
1035 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
1036 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
1037 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1039 memory_region_add_subregion(sysmem
, base
,
1040 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
1044 static void virt_flash_map(VirtMachineState
*vms
,
1045 MemoryRegion
*sysmem
,
1046 MemoryRegion
*secure_sysmem
)
1049 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1050 * sysmem is the system memory space. secure_sysmem is the secure view
1051 * of the system, and the first flash device should be made visible only
1052 * there. The second flash device is visible to both secure and nonsecure.
1053 * If sysmem == secure_sysmem this means there is no separate Secure
1054 * address space and both flash devices are generally visible.
1056 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1057 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1059 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
1061 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
1065 static void virt_flash_fdt(VirtMachineState
*vms
,
1066 MemoryRegion
*sysmem
,
1067 MemoryRegion
*secure_sysmem
)
1069 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1070 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1073 if (sysmem
== secure_sysmem
) {
1074 /* Report both flash devices as a single node in the DT */
1075 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1076 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1077 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
1078 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1079 2, flashbase
, 2, flashsize
,
1080 2, flashbase
+ flashsize
, 2, flashsize
);
1081 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
1085 * Report the devices as separate nodes so we can mark one as
1086 * only visible to the secure world.
1088 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1089 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1090 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
1091 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1092 2, flashbase
, 2, flashsize
);
1093 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
1094 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
1095 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
1098 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1099 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1100 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
1101 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1102 2, flashbase
+ flashsize
, 2, flashsize
);
1103 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
1108 static bool virt_firmware_init(VirtMachineState
*vms
,
1109 MemoryRegion
*sysmem
,
1110 MemoryRegion
*secure_sysmem
)
1113 const char *bios_name
;
1114 BlockBackend
*pflash_blk0
;
1116 /* Map legacy -drive if=pflash to machine properties */
1117 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1118 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1119 drive_get(IF_PFLASH
, 0, i
));
1122 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1124 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1126 bios_name
= MACHINE(vms
)->firmware
;
1133 error_report("The contents of the first flash device may be "
1134 "specified with -bios or with -drive if=pflash... "
1135 "but you cannot use both options at once");
1139 /* Fall back to -bios */
1141 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1143 error_report("Could not find ROM image '%s'", bios_name
);
1146 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1147 image_size
= load_image_mr(fname
, mr
);
1149 if (image_size
< 0) {
1150 error_report("Could not load ROM image '%s'", bios_name
);
1155 return pflash_blk0
|| bios_name
;
1158 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1160 MachineState
*ms
= MACHINE(vms
);
1161 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1162 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1166 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1167 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1169 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1170 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1171 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
1172 "compatible", "qemu,fw-cfg-mmio");
1173 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1175 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1180 static void create_pcie_irq_map(const VirtMachineState
*vms
,
1181 uint32_t gic_phandle
,
1182 int first_irq
, const char *nodename
)
1185 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1186 uint32_t *irq_map
= full_irq_map
;
1188 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1189 for (pin
= 0; pin
< 4; pin
++) {
1190 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1191 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1192 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1196 devfn
<< 8, 0, 0, /* devfn */
1197 pin
+ 1, /* PCI pin */
1198 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1200 /* Convert map to big endian */
1201 for (i
= 0; i
< 10; i
++) {
1202 irq_map
[i
] = cpu_to_be32(map
[i
]);
1208 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-map",
1209 full_irq_map
, sizeof(full_irq_map
));
1211 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupt-map-mask",
1212 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1217 static void create_smmu(const VirtMachineState
*vms
,
1221 const char compat
[] = "arm,smmu-v3";
1222 int irq
= vms
->irqmap
[VIRT_SMMU
];
1224 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1225 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1226 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1229 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1233 dev
= qdev_new("arm-smmuv3");
1235 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
1237 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1238 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1239 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1240 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1241 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1244 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1245 qemu_fdt_add_subnode(vms
->fdt
, node
);
1246 qemu_fdt_setprop(vms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1247 qemu_fdt_setprop_sized_cells(vms
->fdt
, node
, "reg", 2, base
, 2, size
);
1249 qemu_fdt_setprop_cells(vms
->fdt
, node
, "interrupts",
1250 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1251 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1252 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1253 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1255 qemu_fdt_setprop(vms
->fdt
, node
, "interrupt-names", irq_names
,
1258 qemu_fdt_setprop_cell(vms
->fdt
, node
, "clocks", vms
->clock_phandle
);
1259 qemu_fdt_setprop_string(vms
->fdt
, node
, "clock-names", "apb_pclk");
1260 qemu_fdt_setprop(vms
->fdt
, node
, "dma-coherent", NULL
, 0);
1262 qemu_fdt_setprop_cell(vms
->fdt
, node
, "#iommu-cells", 1);
1264 qemu_fdt_setprop_cell(vms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1268 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1270 const char compat
[] = "virtio,pci-iommu";
1271 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1274 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
1276 node
= g_strdup_printf("%s/virtio_iommu@%d", vms
->pciehb_nodename
, bdf
);
1277 qemu_fdt_add_subnode(vms
->fdt
, node
);
1278 qemu_fdt_setprop(vms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1279 qemu_fdt_setprop_sized_cells(vms
->fdt
, node
, "reg",
1280 1, bdf
<< 8, 1, 0, 1, 0,
1283 qemu_fdt_setprop_cell(vms
->fdt
, node
, "#iommu-cells", 1);
1284 qemu_fdt_setprop_cell(vms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1287 qemu_fdt_setprop_cells(vms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1288 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1289 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1292 static void create_pcie(VirtMachineState
*vms
)
1294 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1295 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1296 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1297 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1298 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1299 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1300 hwaddr base_ecam
, size_ecam
;
1301 hwaddr base
= base_mmio
;
1303 int irq
= vms
->irqmap
[VIRT_PCIE
];
1304 MemoryRegion
*mmio_alias
;
1305 MemoryRegion
*mmio_reg
;
1306 MemoryRegion
*ecam_alias
;
1307 MemoryRegion
*ecam_reg
;
1313 dev
= qdev_new(TYPE_GPEX_HOST
);
1314 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1316 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1317 base_ecam
= vms
->memmap
[ecam_id
].base
;
1318 size_ecam
= vms
->memmap
[ecam_id
].size
;
1319 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1320 /* Map only the first size_ecam bytes of ECAM space */
1321 ecam_alias
= g_new0(MemoryRegion
, 1);
1322 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1323 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1324 ecam_reg
, 0, size_ecam
);
1325 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1327 /* Map the MMIO window into system address space so as to expose
1328 * the section of PCI MMIO space which starts at the same base address
1329 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1332 mmio_alias
= g_new0(MemoryRegion
, 1);
1333 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1334 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1335 mmio_reg
, base_mmio
, size_mmio
);
1336 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1339 /* Map high MMIO space */
1340 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1342 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1343 mmio_reg
, base_mmio_high
, size_mmio_high
);
1344 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1348 /* Map IO port space */
1349 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1351 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1352 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1353 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1354 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1357 pci
= PCI_HOST_BRIDGE(dev
);
1358 vms
->bus
= pci
->bus
;
1360 for (i
= 0; i
< nb_nics
; i
++) {
1361 NICInfo
*nd
= &nd_table
[i
];
1364 nd
->model
= g_strdup("virtio");
1367 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1371 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1372 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1373 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
1374 "compatible", "pci-host-ecam-generic");
1375 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "pci");
1376 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 3);
1377 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 2);
1378 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "linux,pci-domain", 0);
1379 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "bus-range", 0,
1381 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1383 if (vms
->msi_phandle
) {
1384 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "msi-parent",
1388 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1389 2, base_ecam
, 2, size_ecam
);
1392 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1393 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1394 2, base_pio
, 2, size_pio
,
1395 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1396 2, base_mmio
, 2, size_mmio
,
1397 1, FDT_PCI_RANGE_MMIO_64BIT
,
1399 2, base_mmio_high
, 2, size_mmio_high
);
1401 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1402 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1403 2, base_pio
, 2, size_pio
,
1404 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1405 2, base_mmio
, 2, size_mmio
);
1408 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 1);
1409 create_pcie_irq_map(vms
, vms
->gic_phandle
, irq
, nodename
);
1412 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
1414 switch (vms
->iommu
) {
1415 case VIRT_IOMMU_SMMUV3
:
1416 create_smmu(vms
, vms
->bus
);
1417 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "iommu-map",
1418 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1421 g_assert_not_reached();
1426 static void create_platform_bus(VirtMachineState
*vms
)
1431 MemoryRegion
*sysmem
= get_system_memory();
1433 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1434 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1435 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1436 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1437 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1438 vms
->platform_bus_dev
= dev
;
1440 s
= SYS_BUS_DEVICE(dev
);
1441 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1442 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1443 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1446 memory_region_add_subregion(sysmem
,
1447 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1448 sysbus_mmio_get_region(s
, 0));
1451 static void create_tag_ram(MemoryRegion
*tag_sysmem
,
1452 hwaddr base
, hwaddr size
,
1455 MemoryRegion
*tagram
= g_new(MemoryRegion
, 1);
1457 memory_region_init_ram(tagram
, NULL
, name
, size
/ 32, &error_fatal
);
1458 memory_region_add_subregion(tag_sysmem
, base
/ 32, tagram
);
1461 static void create_secure_ram(VirtMachineState
*vms
,
1462 MemoryRegion
*secure_sysmem
,
1463 MemoryRegion
*secure_tag_sysmem
)
1465 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1467 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1468 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1470 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1472 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1474 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1475 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1476 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "memory");
1477 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1478 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
1479 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
1481 if (secure_tag_sysmem
) {
1482 create_tag_ram(secure_tag_sysmem
, base
, size
, "mach-virt.secure-tag");
1488 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1490 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1493 *fdt_size
= board
->fdt_size
;
1497 static void virt_build_smbios(VirtMachineState
*vms
)
1499 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1500 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1501 uint8_t *smbios_tables
, *smbios_anchor
;
1502 size_t smbios_tables_len
, smbios_anchor_len
;
1503 const char *product
= "QEMU Virtual Machine";
1505 if (kvm_enabled()) {
1506 product
= "KVM Virtual Machine";
1509 smbios_set_defaults("QEMU", product
,
1510 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1511 true, SMBIOS_ENTRY_POINT_30
);
1513 smbios_get_tables(MACHINE(vms
), NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1514 &smbios_anchor
, &smbios_anchor_len
);
1516 if (smbios_anchor
) {
1517 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1518 smbios_tables
, smbios_tables_len
);
1519 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1520 smbios_anchor
, smbios_anchor_len
);
1525 void virt_machine_done(Notifier
*notifier
, void *data
)
1527 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1529 MachineState
*ms
= MACHINE(vms
);
1530 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1531 struct arm_boot_info
*info
= &vms
->bootinfo
;
1532 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1535 * If the user provided a dtb, we assume the dynamic sysbus nodes
1536 * already are integrated there. This corresponds to a use case where
1537 * the dynamic sysbus nodes are complex and their generation is not yet
1538 * supported. In that case the user can take charge of the guest dt
1539 * while qemu takes charge of the qom stuff.
1541 if (info
->dtb_filename
== NULL
) {
1542 platform_bus_add_all_fdt_nodes(vms
->fdt
, "/intc",
1543 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1544 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1545 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1547 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1551 fw_cfg_add_extra_pci_roots(vms
->bus
, vms
->fw_cfg
);
1553 virt_acpi_setup(vms
);
1554 virt_build_smbios(vms
);
1557 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1559 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1560 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1562 if (!vmc
->disallow_affinity_adjustment
) {
1563 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1564 * GIC's target-list limitations. 32-bit KVM hosts currently
1565 * always create clusters of 4 CPUs, but that is expected to
1566 * change when they gain support for gicv3. When KVM is enabled
1567 * it will override the changes we make here, therefore our
1568 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1569 * and to improve SGI efficiency.
1571 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
1572 clustersz
= GICV3_TARGETLIST_BITS
;
1574 clustersz
= GIC_TARGETLIST_BITS
;
1577 return arm_cpu_mp_affinity(idx
, clustersz
);
1580 static void virt_set_memmap(VirtMachineState
*vms
)
1582 MachineState
*ms
= MACHINE(vms
);
1583 hwaddr base
, device_memory_base
, device_memory_size
;
1586 vms
->memmap
= extended_memmap
;
1588 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1589 vms
->memmap
[i
] = base_memmap
[i
];
1592 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1593 error_report("unsupported number of memory slots: %"PRIu64
,
1599 * We compute the base of the high IO region depending on the
1600 * amount of initial and device memory. The device memory start/size
1601 * is aligned on 1GiB. We never put the high IO region below 256GiB
1602 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1603 * The device region size assumes 1GiB page max alignment per slot.
1605 device_memory_base
=
1606 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1607 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1609 /* Base address of the high IO region */
1610 base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1611 if (base
< device_memory_base
) {
1612 error_report("maxmem/slots too huge");
1615 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1616 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1619 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1620 hwaddr size
= extended_memmap
[i
].size
;
1622 base
= ROUND_UP(base
, size
);
1623 vms
->memmap
[i
].base
= base
;
1624 vms
->memmap
[i
].size
= size
;
1627 vms
->highest_gpa
= base
- 1;
1628 if (device_memory_size
> 0) {
1629 ms
->device_memory
= g_malloc0(sizeof(*ms
->device_memory
));
1630 ms
->device_memory
->base
= device_memory_base
;
1631 memory_region_init(&ms
->device_memory
->mr
, OBJECT(vms
),
1632 "device-memory", device_memory_size
);
1637 * finalize_gic_version - Determines the final gic_version
1638 * according to the gic-version property
1640 * Default GIC type is v2
1642 static void finalize_gic_version(VirtMachineState
*vms
)
1644 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1646 if (kvm_enabled()) {
1649 if (!kvm_irqchip_in_kernel()) {
1650 switch (vms
->gic_version
) {
1651 case VIRT_GIC_VERSION_HOST
:
1653 "gic-version=host not relevant with kernel-irqchip=off "
1654 "as only userspace GICv2 is supported. Using v2 ...");
1656 case VIRT_GIC_VERSION_MAX
:
1657 case VIRT_GIC_VERSION_NOSEL
:
1658 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1660 case VIRT_GIC_VERSION_2
:
1662 case VIRT_GIC_VERSION_3
:
1664 "gic-version=3 is not supported with kernel-irqchip=off");
1669 probe_bitmap
= kvm_arm_vgic_probe();
1670 if (!probe_bitmap
) {
1671 error_report("Unable to determine GIC version supported by host");
1675 switch (vms
->gic_version
) {
1676 case VIRT_GIC_VERSION_HOST
:
1677 case VIRT_GIC_VERSION_MAX
:
1678 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1679 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1681 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1684 case VIRT_GIC_VERSION_NOSEL
:
1685 if ((probe_bitmap
& KVM_ARM_VGIC_V2
) && max_cpus
<= GIC_NCPU
) {
1686 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1687 } else if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1689 * in case the host does not support v2 in-kernel emulation or
1690 * the end-user requested more than 8 VCPUs we now default
1691 * to v3. In any case defaulting to v2 would be broken.
1693 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1694 } else if (max_cpus
> GIC_NCPU
) {
1695 error_report("host only supports in-kernel GICv2 emulation "
1696 "but more than 8 vcpus are requested");
1700 case VIRT_GIC_VERSION_2
:
1701 case VIRT_GIC_VERSION_3
:
1705 /* Check chosen version is effectively supported by the host */
1706 if (vms
->gic_version
== VIRT_GIC_VERSION_2
&&
1707 !(probe_bitmap
& KVM_ARM_VGIC_V2
)) {
1708 error_report("host does not support in-kernel GICv2 emulation");
1710 } else if (vms
->gic_version
== VIRT_GIC_VERSION_3
&&
1711 !(probe_bitmap
& KVM_ARM_VGIC_V3
)) {
1712 error_report("host does not support in-kernel GICv3 emulation");
1719 switch (vms
->gic_version
) {
1720 case VIRT_GIC_VERSION_NOSEL
:
1721 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1723 case VIRT_GIC_VERSION_MAX
:
1724 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1726 case VIRT_GIC_VERSION_HOST
:
1727 error_report("gic-version=host requires KVM");
1729 case VIRT_GIC_VERSION_2
:
1730 case VIRT_GIC_VERSION_3
:
1736 * virt_cpu_post_init() must be called after the CPUs have
1737 * been realized and the GIC has been created.
1739 static void virt_cpu_post_init(VirtMachineState
*vms
, MemoryRegion
*sysmem
)
1741 int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1742 bool aarch64
, pmu
, steal_time
;
1745 aarch64
= object_property_get_bool(OBJECT(first_cpu
), "aarch64", NULL
);
1746 pmu
= object_property_get_bool(OBJECT(first_cpu
), "pmu", NULL
);
1747 steal_time
= object_property_get_bool(OBJECT(first_cpu
),
1748 "kvm-steal-time", NULL
);
1750 if (kvm_enabled()) {
1751 hwaddr pvtime_reg_base
= vms
->memmap
[VIRT_PVTIME
].base
;
1752 hwaddr pvtime_reg_size
= vms
->memmap
[VIRT_PVTIME
].size
;
1755 MemoryRegion
*pvtime
= g_new(MemoryRegion
, 1);
1756 hwaddr pvtime_size
= max_cpus
* PVTIME_SIZE_PER_CPU
;
1758 /* The memory region size must be a multiple of host page size. */
1759 pvtime_size
= REAL_HOST_PAGE_ALIGN(pvtime_size
);
1761 if (pvtime_size
> pvtime_reg_size
) {
1762 error_report("pvtime requires a %" HWADDR_PRId
1763 " byte memory region for %d CPUs,"
1764 " but only %" HWADDR_PRId
" has been reserved",
1765 pvtime_size
, max_cpus
, pvtime_reg_size
);
1769 memory_region_init_ram(pvtime
, NULL
, "pvtime", pvtime_size
, NULL
);
1770 memory_region_add_subregion(sysmem
, pvtime_reg_base
, pvtime
);
1775 assert(arm_feature(&ARM_CPU(cpu
)->env
, ARM_FEATURE_PMU
));
1776 if (kvm_irqchip_in_kernel()) {
1777 kvm_arm_pmu_set_irq(cpu
, PPI(VIRTUAL_PMU_IRQ
));
1779 kvm_arm_pmu_init(cpu
);
1782 kvm_arm_pvtime_init(cpu
, pvtime_reg_base
+
1783 cpu
->cpu_index
* PVTIME_SIZE_PER_CPU
);
1787 if (aarch64
&& vms
->highmem
) {
1788 int requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
1789 int pamax
= arm_pamax(ARM_CPU(first_cpu
));
1791 if (pamax
< requested_pa_size
) {
1792 error_report("VCPU supports less PA bits (%d) than "
1793 "requested by the memory map (%d)",
1794 pamax
, requested_pa_size
);
1801 static void machvirt_init(MachineState
*machine
)
1803 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1804 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1805 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1806 const CPUArchIdList
*possible_cpus
;
1807 MemoryRegion
*sysmem
= get_system_memory();
1808 MemoryRegion
*secure_sysmem
= NULL
;
1809 MemoryRegion
*tag_sysmem
= NULL
;
1810 MemoryRegion
*secure_tag_sysmem
= NULL
;
1811 int n
, virt_max_cpus
;
1812 bool firmware_loaded
;
1813 bool aarch64
= true;
1814 bool has_ged
= !vmc
->no_ged
;
1815 unsigned int smp_cpus
= machine
->smp
.cpus
;
1816 unsigned int max_cpus
= machine
->smp
.max_cpus
;
1819 * In accelerated mode, the memory map is computed earlier in kvm_type()
1820 * to create a VM with the right number of IPA bits.
1823 virt_set_memmap(vms
);
1826 /* We can probe only here because during property set
1827 * KVM is not available yet
1829 finalize_gic_version(vms
);
1831 if (!cpu_type_valid(machine
->cpu_type
)) {
1832 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
1837 if (kvm_enabled()) {
1838 error_report("mach-virt: KVM does not support Security extensions");
1843 * The Secure view of the world is the same as the NonSecure,
1844 * but with a few extra devices. Create it as a container region
1845 * containing the system memory at low priority; any secure-only
1846 * devices go in at higher priority and take precedence.
1848 secure_sysmem
= g_new(MemoryRegion
, 1);
1849 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1851 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1854 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
1855 secure_sysmem
?: sysmem
);
1857 /* If we have an EL3 boot ROM then the assumption is that it will
1858 * implement PSCI itself, so disable QEMU's internal implementation
1859 * so it doesn't get in the way. Instead of starting secondary
1860 * CPUs in PSCI powerdown state we will start them all running and
1861 * let the boot ROM sort them out.
1862 * The usual case is that we do use QEMU's PSCI implementation;
1863 * if the guest has EL2 then we will use SMC as the conduit,
1864 * and otherwise we will use HVC (for backwards compatibility and
1865 * because if we're using KVM then we must use HVC).
1867 if (vms
->secure
&& firmware_loaded
) {
1868 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
1869 } else if (vms
->virt
) {
1870 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
1872 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
1875 /* The maximum number of CPUs depends on the GIC version, or on how
1876 * many redistributors we can fit into the memory map.
1878 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
1880 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
1882 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
1884 virt_max_cpus
= GIC_NCPU
;
1887 if (max_cpus
> virt_max_cpus
) {
1888 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1889 "supported by machine 'mach-virt' (%d)",
1890 max_cpus
, virt_max_cpus
);
1894 if (vms
->virt
&& kvm_enabled()) {
1895 error_report("mach-virt: KVM does not support providing "
1896 "Virtualization extensions to the guest CPU");
1900 if (vms
->mte
&& kvm_enabled()) {
1901 error_report("mach-virt: KVM does not support providing "
1902 "MTE to the guest CPU");
1908 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
1909 assert(possible_cpus
->len
== max_cpus
);
1910 for (n
= 0; n
< possible_cpus
->len
; n
++) {
1914 if (n
>= smp_cpus
) {
1918 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
1919 object_property_set_int(cpuobj
, "mp-affinity",
1920 possible_cpus
->cpus
[n
].arch_id
, NULL
);
1925 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
1928 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
1931 object_property_set_bool(cpuobj
, "has_el3", false, NULL
);
1934 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2")) {
1935 object_property_set_bool(cpuobj
, "has_el2", false, NULL
);
1938 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
) {
1939 object_property_set_int(cpuobj
, "psci-conduit", vms
->psci_conduit
,
1942 /* Secondary CPUs start in PSCI powered-down state */
1944 object_property_set_bool(cpuobj
, "start-powered-off", true,
1949 if (vmc
->kvm_no_adjvtime
&&
1950 object_property_find(cpuobj
, "kvm-no-adjvtime")) {
1951 object_property_set_bool(cpuobj
, "kvm-no-adjvtime", true, NULL
);
1954 if (vmc
->no_kvm_steal_time
&&
1955 object_property_find(cpuobj
, "kvm-steal-time")) {
1956 object_property_set_bool(cpuobj
, "kvm-steal-time", false, NULL
);
1959 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu")) {
1960 object_property_set_bool(cpuobj
, "pmu", false, NULL
);
1963 if (object_property_find(cpuobj
, "reset-cbar")) {
1964 object_property_set_int(cpuobj
, "reset-cbar",
1965 vms
->memmap
[VIRT_CPUPERIPHS
].base
,
1969 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
1972 object_property_set_link(cpuobj
, "secure-memory",
1973 OBJECT(secure_sysmem
), &error_abort
);
1977 /* Create the memory region only once, but link to all cpus. */
1980 * The property exists only if MemTag is supported.
1981 * If it is, we must allocate the ram to back that up.
1983 if (!object_property_find(cpuobj
, "tag-memory")) {
1984 error_report("MTE requested, but not supported "
1985 "by the guest CPU");
1989 tag_sysmem
= g_new(MemoryRegion
, 1);
1990 memory_region_init(tag_sysmem
, OBJECT(machine
),
1991 "tag-memory", UINT64_MAX
/ 32);
1994 secure_tag_sysmem
= g_new(MemoryRegion
, 1);
1995 memory_region_init(secure_tag_sysmem
, OBJECT(machine
),
1996 "secure-tag-memory", UINT64_MAX
/ 32);
1998 /* As with ram, secure-tag takes precedence over tag. */
1999 memory_region_add_subregion_overlap(secure_tag_sysmem
, 0,
2004 object_property_set_link(cpuobj
, "tag-memory", OBJECT(tag_sysmem
),
2007 object_property_set_link(cpuobj
, "secure-tag-memory",
2008 OBJECT(secure_tag_sysmem
),
2013 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
2014 object_unref(cpuobj
);
2016 fdt_add_timer_nodes(vms
);
2017 fdt_add_cpu_nodes(vms
);
2019 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2021 if (machine
->device_memory
) {
2022 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2023 &machine
->device_memory
->mr
);
2026 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
2030 virt_cpu_post_init(vms
, sysmem
);
2032 fdt_add_pmu_nodes(vms
);
2034 create_uart(vms
, VIRT_UART
, sysmem
, serial_hd(0));
2037 create_secure_ram(vms
, secure_sysmem
, secure_tag_sysmem
);
2038 create_uart(vms
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
2042 create_tag_ram(tag_sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2043 machine
->ram_size
, "mach-virt.tag");
2046 vms
->highmem_ecam
&= vms
->highmem
&& (!firmware_loaded
|| aarch64
);
2052 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
2053 vms
->acpi_dev
= create_acpi_ged(vms
);
2055 create_gpio_devices(vms
, VIRT_GPIO
, sysmem
);
2058 if (vms
->secure
&& !vmc
->no_secure_gpio
) {
2059 create_gpio_devices(vms
, VIRT_SECURE_GPIO
, secure_sysmem
);
2062 /* connect powerdown request */
2063 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
2064 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
2066 /* Create mmio transports, so the user can create virtio backends
2067 * (which will be automatically plugged in to the transports). If
2068 * no backend is created the transport will just sit harmlessly idle.
2070 create_virtio_devices(vms
);
2072 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
2073 rom_set_fw(vms
->fw_cfg
);
2075 create_platform_bus(vms
);
2077 if (machine
->nvdimms_state
->is_enabled
) {
2078 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio
= {
2079 .space_id
= AML_AS_SYSTEM_MEMORY
,
2080 .address
= vms
->memmap
[VIRT_NVDIMM_ACPI
].base
,
2081 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
2084 nvdimm_init_acpi_state(machine
->nvdimms_state
, sysmem
,
2085 arm_virt_nvdimm_acpi_dsmio
,
2086 vms
->fw_cfg
, OBJECT(vms
));
2089 vms
->bootinfo
.ram_size
= machine
->ram_size
;
2090 vms
->bootinfo
.nb_cpus
= smp_cpus
;
2091 vms
->bootinfo
.board_id
= -1;
2092 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
2093 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
2094 vms
->bootinfo
.skip_dtb_autoload
= true;
2095 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
2096 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
2098 vms
->machine_done
.notify
= virt_machine_done
;
2099 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
2102 static bool virt_get_secure(Object
*obj
, Error
**errp
)
2104 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2109 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
2111 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2113 vms
->secure
= value
;
2116 static bool virt_get_virt(Object
*obj
, Error
**errp
)
2118 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2123 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
2125 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2130 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
2132 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2134 return vms
->highmem
;
2137 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
2139 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2141 vms
->highmem
= value
;
2144 static bool virt_get_its(Object
*obj
, Error
**errp
)
2146 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2151 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
2153 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2158 static char *virt_get_oem_id(Object
*obj
, Error
**errp
)
2160 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2162 return g_strdup(vms
->oem_id
);
2165 static void virt_set_oem_id(Object
*obj
, const char *value
, Error
**errp
)
2167 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2168 size_t len
= strlen(value
);
2172 "User specified oem-id value is bigger than 6 bytes in size");
2176 strncpy(vms
->oem_id
, value
, 6);
2179 static char *virt_get_oem_table_id(Object
*obj
, Error
**errp
)
2181 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2183 return g_strdup(vms
->oem_table_id
);
2186 static void virt_set_oem_table_id(Object
*obj
, const char *value
,
2189 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2190 size_t len
= strlen(value
);
2194 "User specified oem-table-id value is bigger than 8 bytes in size");
2197 strncpy(vms
->oem_table_id
, value
, 8);
2201 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
2203 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
2209 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2210 void *opaque
, Error
**errp
)
2212 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2213 OnOffAuto acpi
= vms
->acpi
;
2215 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
2218 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2219 void *opaque
, Error
**errp
)
2221 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2223 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
2226 static bool virt_get_ras(Object
*obj
, Error
**errp
)
2228 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2233 static void virt_set_ras(Object
*obj
, bool value
, Error
**errp
)
2235 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2240 static bool virt_get_mte(Object
*obj
, Error
**errp
)
2242 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2247 static void virt_set_mte(Object
*obj
, bool value
, Error
**errp
)
2249 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2254 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
2256 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2257 const char *val
= vms
->gic_version
== VIRT_GIC_VERSION_3
? "3" : "2";
2259 return g_strdup(val
);
2262 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
2264 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2266 if (!strcmp(value
, "3")) {
2267 vms
->gic_version
= VIRT_GIC_VERSION_3
;
2268 } else if (!strcmp(value
, "2")) {
2269 vms
->gic_version
= VIRT_GIC_VERSION_2
;
2270 } else if (!strcmp(value
, "host")) {
2271 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
2272 } else if (!strcmp(value
, "max")) {
2273 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
2275 error_setg(errp
, "Invalid gic-version value");
2276 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
2280 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
2282 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2284 switch (vms
->iommu
) {
2285 case VIRT_IOMMU_NONE
:
2286 return g_strdup("none");
2287 case VIRT_IOMMU_SMMUV3
:
2288 return g_strdup("smmuv3");
2290 g_assert_not_reached();
2294 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2296 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2298 if (!strcmp(value
, "smmuv3")) {
2299 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2300 } else if (!strcmp(value
, "none")) {
2301 vms
->iommu
= VIRT_IOMMU_NONE
;
2303 error_setg(errp
, "Invalid iommu value");
2304 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2308 static CpuInstanceProperties
2309 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2311 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2312 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2314 assert(cpu_index
< possible_cpus
->len
);
2315 return possible_cpus
->cpus
[cpu_index
].props
;
2318 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2320 return idx
% ms
->numa_state
->num_nodes
;
2323 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2326 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2327 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2329 if (ms
->possible_cpus
) {
2330 assert(ms
->possible_cpus
->len
== max_cpus
);
2331 return ms
->possible_cpus
;
2334 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2335 sizeof(CPUArchId
) * max_cpus
);
2336 ms
->possible_cpus
->len
= max_cpus
;
2337 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2338 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2339 ms
->possible_cpus
->cpus
[n
].arch_id
=
2340 virt_cpu_mp_affinity(vms
, n
);
2341 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2342 ms
->possible_cpus
->cpus
[n
].props
.thread_id
= n
;
2344 return ms
->possible_cpus
;
2347 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2350 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2351 const MachineState
*ms
= MACHINE(hotplug_dev
);
2352 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2354 if (!vms
->acpi_dev
) {
2356 "memory hotplug is not enabled: missing acpi-ged device");
2361 error_setg(errp
, "memory hotplug is not enabled: MTE is enabled");
2365 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2366 error_setg(errp
, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2370 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), NULL
, errp
);
2373 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2374 DeviceState
*dev
, Error
**errp
)
2376 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2377 MachineState
*ms
= MACHINE(hotplug_dev
);
2378 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2380 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
));
2383 nvdimm_plug(ms
->nvdimms_state
);
2386 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2390 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2391 DeviceState
*dev
, Error
**errp
)
2393 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2395 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2396 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2397 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2398 hwaddr db_start
= 0, db_end
= 0;
2399 char *resv_prop_str
;
2401 switch (vms
->msi_controller
) {
2402 case VIRT_MSI_CTRL_NONE
:
2404 case VIRT_MSI_CTRL_ITS
:
2405 /* GITS_TRANSLATER page */
2406 db_start
= base_memmap
[VIRT_GIC_ITS
].base
+ 0x10000;
2407 db_end
= base_memmap
[VIRT_GIC_ITS
].base
+
2408 base_memmap
[VIRT_GIC_ITS
].size
- 1;
2410 case VIRT_MSI_CTRL_GICV2M
:
2411 /* MSI_SETSPI_NS page */
2412 db_start
= base_memmap
[VIRT_GIC_V2M
].base
;
2413 db_end
= db_start
+ base_memmap
[VIRT_GIC_V2M
].size
- 1;
2416 resv_prop_str
= g_strdup_printf("0x%"PRIx64
":0x%"PRIx64
":%u",
2418 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
2420 qdev_prop_set_uint32(dev
, "len-reserved-regions", 1);
2421 qdev_prop_set_string(dev
, "reserved-regions[0]", resv_prop_str
);
2422 g_free(resv_prop_str
);
2426 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2427 DeviceState
*dev
, Error
**errp
)
2429 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2431 if (vms
->platform_bus_dev
) {
2432 if (object_dynamic_cast(OBJECT(dev
), TYPE_SYS_BUS_DEVICE
)) {
2433 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2434 SYS_BUS_DEVICE(dev
));
2437 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2438 virt_memory_plug(hotplug_dev
, dev
, errp
);
2440 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2441 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2443 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2444 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2445 create_virtio_iommu_dt_bindings(vms
);
2449 static void virt_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
2450 DeviceState
*dev
, Error
**errp
)
2452 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2453 Error
*local_err
= NULL
;
2455 if (!vms
->acpi_dev
) {
2456 error_setg(&local_err
,
2457 "memory hotplug is not enabled: missing acpi-ged device");
2461 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2462 error_setg(&local_err
,
2463 "nvdimm device hot unplug is not supported yet.");
2467 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
,
2470 error_propagate(errp
, local_err
);
2473 static void virt_dimm_unplug(HotplugHandler
*hotplug_dev
,
2474 DeviceState
*dev
, Error
**errp
)
2476 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2477 Error
*local_err
= NULL
;
2479 hotplug_handler_unplug(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
, &local_err
);
2484 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(vms
));
2485 qdev_unrealize(dev
);
2488 error_propagate(errp
, local_err
);
2491 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2492 DeviceState
*dev
, Error
**errp
)
2494 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2495 virt_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2497 error_setg(errp
, "device unplug request for unsupported device"
2498 " type: %s", object_get_typename(OBJECT(dev
)));
2502 static void virt_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2503 DeviceState
*dev
, Error
**errp
)
2505 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2506 virt_dimm_unplug(hotplug_dev
, dev
, errp
);
2508 error_setg(errp
, "virt: device unplug for unsupported device"
2509 " type: %s", object_get_typename(OBJECT(dev
)));
2513 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2516 if (object_dynamic_cast(OBJECT(dev
), TYPE_SYS_BUS_DEVICE
) ||
2517 (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
))) {
2518 return HOTPLUG_HANDLER(machine
);
2520 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2521 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
2523 if (!vms
->bootinfo
.firmware_loaded
|| !virt_is_acpi_enabled(vms
)) {
2524 return HOTPLUG_HANDLER(machine
);
2531 * for arm64 kvm_type [7-0] encodes the requested number of bits
2532 * in the IPA address space
2534 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2536 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2537 int max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
);
2538 int requested_pa_size
;
2540 /* we freeze the memory map to compute the highest gpa */
2541 virt_set_memmap(vms
);
2543 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2545 if (requested_pa_size
> max_vm_pa_size
) {
2546 error_report("-m and ,maxmem option values "
2547 "require an IPA range (%d bits) larger than "
2548 "the one supported by the host (%d bits)",
2549 requested_pa_size
, max_vm_pa_size
);
2553 * By default we return 0 which corresponds to an implicit legacy
2554 * 40b IPA setting. Otherwise we return the actual requested PA
2557 return requested_pa_size
> 40 ? requested_pa_size
: 0;
2560 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
2562 MachineClass
*mc
= MACHINE_CLASS(oc
);
2563 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2565 mc
->init
= machvirt_init
;
2566 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2567 * The value may be reduced later when we have more information about the
2568 * configuration of the particular instance.
2571 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
2572 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
2573 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
2574 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
2575 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
2576 mc
->block_default_type
= IF_VIRTIO
;
2578 mc
->pci_allow_0_address
= true;
2579 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2580 mc
->minimum_page_bits
= 12;
2581 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
2582 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
2583 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
2584 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
2585 mc
->kvm_type
= virt_kvm_type
;
2586 assert(!mc
->get_hotplug_handler
);
2587 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
2588 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
2589 hc
->plug
= virt_machine_device_plug_cb
;
2590 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
2591 hc
->unplug
= virt_machine_device_unplug_cb
;
2592 mc
->nvdimm_supported
= true;
2593 mc
->auto_enable_numa_with_memhp
= true;
2594 mc
->auto_enable_numa_with_memdev
= true;
2595 mc
->default_ram_id
= "mach-virt.ram";
2597 object_class_property_add(oc
, "acpi", "OnOffAuto",
2598 virt_get_acpi
, virt_set_acpi
,
2600 object_class_property_set_description(oc
, "acpi",
2602 object_class_property_add_bool(oc
, "secure", virt_get_secure
,
2604 object_class_property_set_description(oc
, "secure",
2605 "Set on/off to enable/disable the ARM "
2606 "Security Extensions (TrustZone)");
2608 object_class_property_add_bool(oc
, "virtualization", virt_get_virt
,
2610 object_class_property_set_description(oc
, "virtualization",
2611 "Set on/off to enable/disable emulating a "
2612 "guest CPU which implements the ARM "
2613 "Virtualization Extensions");
2615 object_class_property_add_bool(oc
, "highmem", virt_get_highmem
,
2617 object_class_property_set_description(oc
, "highmem",
2618 "Set on/off to enable/disable using "
2619 "physical address space above 32 bits");
2621 object_class_property_add_str(oc
, "gic-version", virt_get_gic_version
,
2622 virt_set_gic_version
);
2623 object_class_property_set_description(oc
, "gic-version",
2625 "Valid values are 2, 3, host and max");
2627 object_class_property_add_str(oc
, "iommu", virt_get_iommu
, virt_set_iommu
);
2628 object_class_property_set_description(oc
, "iommu",
2629 "Set the IOMMU type. "
2630 "Valid values are none and smmuv3");
2632 object_class_property_add_bool(oc
, "ras", virt_get_ras
,
2634 object_class_property_set_description(oc
, "ras",
2635 "Set on/off to enable/disable reporting host memory errors "
2636 "to a KVM guest using ACPI and guest external abort exceptions");
2638 object_class_property_add_bool(oc
, "mte", virt_get_mte
, virt_set_mte
);
2639 object_class_property_set_description(oc
, "mte",
2640 "Set on/off to enable/disable emulating a "
2641 "guest CPU which implements the ARM "
2642 "Memory Tagging Extension");
2644 object_class_property_add_bool(oc
, "its", virt_get_its
,
2646 object_class_property_set_description(oc
, "its",
2647 "Set on/off to enable/disable "
2648 "ITS instantiation");
2650 object_class_property_add_str(oc
, "oem-id",
2653 object_class_property_set_description(oc
, "oem-id",
2654 "Override the default value of field OEMID "
2655 "in ACPI table header."
2656 "The string may be up to 6 bytes in size");
2659 object_class_property_add_str(oc
, "oem-table-id",
2660 virt_get_oem_table_id
,
2661 virt_set_oem_table_id
);
2662 object_class_property_set_description(oc
, "oem-table-id",
2663 "Override the default value of field OEM Table ID "
2664 "in ACPI table header."
2665 "The string may be up to 8 bytes in size");
2669 static void virt_instance_init(Object
*obj
)
2671 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2672 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
2674 /* EL3 is disabled by default on virt: this makes us consistent
2675 * between KVM and TCG for this board, and it also allows us to
2676 * boot UEFI blobs which assume no TrustZone support.
2678 vms
->secure
= false;
2680 /* EL2 is also disabled by default, for similar reasons */
2683 /* High memory is enabled by default */
2684 vms
->highmem
= true;
2685 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
2687 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
2692 /* Default allows ITS instantiation */
2696 /* Default disallows iommu instantiation */
2697 vms
->iommu
= VIRT_IOMMU_NONE
;
2699 /* Default disallows RAS instantiation */
2702 /* MTE is disabled by default. */
2705 vms
->irqmap
= a15irqmap
;
2707 virt_flash_create(vms
);
2709 vms
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
2710 vms
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
2713 static const TypeInfo virt_machine_info
= {
2714 .name
= TYPE_VIRT_MACHINE
,
2715 .parent
= TYPE_MACHINE
,
2717 .instance_size
= sizeof(VirtMachineState
),
2718 .class_size
= sizeof(VirtMachineClass
),
2719 .class_init
= virt_machine_class_init
,
2720 .instance_init
= virt_instance_init
,
2721 .interfaces
= (InterfaceInfo
[]) {
2722 { TYPE_HOTPLUG_HANDLER
},
2727 static void machvirt_machine_init(void)
2729 type_register_static(&virt_machine_info
);
2731 type_init(machvirt_machine_init
);
2733 static void virt_machine_6_0_options(MachineClass
*mc
)
2736 DEFINE_VIRT_MACHINE_AS_LATEST(6, 0)
2738 static void virt_machine_5_2_options(MachineClass
*mc
)
2740 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2742 virt_machine_6_0_options(mc
);
2743 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
2744 vmc
->no_secure_gpio
= true;
2746 DEFINE_VIRT_MACHINE(5, 2)
2748 static void virt_machine_5_1_options(MachineClass
*mc
)
2750 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2752 virt_machine_5_2_options(mc
);
2753 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
2754 vmc
->no_kvm_steal_time
= true;
2756 DEFINE_VIRT_MACHINE(5, 1)
2758 static void virt_machine_5_0_options(MachineClass
*mc
)
2760 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2762 virt_machine_5_1_options(mc
);
2763 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
2764 mc
->numa_mem_supported
= true;
2765 vmc
->acpi_expose_flash
= true;
2766 mc
->auto_enable_numa_with_memdev
= false;
2768 DEFINE_VIRT_MACHINE(5, 0)
2770 static void virt_machine_4_2_options(MachineClass
*mc
)
2772 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2774 virt_machine_5_0_options(mc
);
2775 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
2776 vmc
->kvm_no_adjvtime
= true;
2778 DEFINE_VIRT_MACHINE(4, 2)
2780 static void virt_machine_4_1_options(MachineClass
*mc
)
2782 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2784 virt_machine_4_2_options(mc
);
2785 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
2787 mc
->auto_enable_numa_with_memhp
= false;
2789 DEFINE_VIRT_MACHINE(4, 1)
2791 static void virt_machine_4_0_options(MachineClass
*mc
)
2793 virt_machine_4_1_options(mc
);
2794 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
2796 DEFINE_VIRT_MACHINE(4, 0)
2798 static void virt_machine_3_1_options(MachineClass
*mc
)
2800 virt_machine_4_0_options(mc
);
2801 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
2803 DEFINE_VIRT_MACHINE(3, 1)
2805 static void virt_machine_3_0_options(MachineClass
*mc
)
2807 virt_machine_3_1_options(mc
);
2808 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
2810 DEFINE_VIRT_MACHINE(3, 0)
2812 static void virt_machine_2_12_options(MachineClass
*mc
)
2814 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2816 virt_machine_3_0_options(mc
);
2817 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
2818 vmc
->no_highmem_ecam
= true;
2821 DEFINE_VIRT_MACHINE(2, 12)
2823 static void virt_machine_2_11_options(MachineClass
*mc
)
2825 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2827 virt_machine_2_12_options(mc
);
2828 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
2829 vmc
->smbios_old_sys_ver
= true;
2831 DEFINE_VIRT_MACHINE(2, 11)
2833 static void virt_machine_2_10_options(MachineClass
*mc
)
2835 virt_machine_2_11_options(mc
);
2836 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
2837 /* before 2.11 we never faulted accesses to bad addresses */
2838 mc
->ignore_memory_transaction_failures
= true;
2840 DEFINE_VIRT_MACHINE(2, 10)
2842 static void virt_machine_2_9_options(MachineClass
*mc
)
2844 virt_machine_2_10_options(mc
);
2845 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
2847 DEFINE_VIRT_MACHINE(2, 9)
2849 static void virt_machine_2_8_options(MachineClass
*mc
)
2851 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2853 virt_machine_2_9_options(mc
);
2854 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
2855 /* For 2.8 and earlier we falsely claimed in the DT that
2856 * our timers were edge-triggered, not level-triggered.
2858 vmc
->claim_edge_triggered_timers
= true;
2860 DEFINE_VIRT_MACHINE(2, 8)
2862 static void virt_machine_2_7_options(MachineClass
*mc
)
2864 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2866 virt_machine_2_8_options(mc
);
2867 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
2868 /* ITS was introduced with 2.8 */
2870 /* Stick with 1K pages for migration compatibility */
2871 mc
->minimum_page_bits
= 0;
2873 DEFINE_VIRT_MACHINE(2, 7)
2875 static void virt_machine_2_6_options(MachineClass
*mc
)
2877 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2879 virt_machine_2_7_options(mc
);
2880 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
2881 vmc
->disallow_affinity_adjustment
= true;
2882 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
2885 DEFINE_VIRT_MACHINE(2, 6)