include/hw/arm/armv7m.h

   1 /*
   2  * ARMv7M CPU object
   3  *
   4  * Copyright (c) 2017 Linaro Ltd
   5  * Written by Peter Maydell <peter.maydell@linaro.org>
   6  *
   7  * This code is licensed under the GPL version 2 or later.
   8  */
   9
  10 #ifndef HW_ARM_ARMV7M_H
  11 #define HW_ARM_ARMV7M_H
  12
  13 #include "hw/sysbus.h"
  14 #include "hw/arm/armv7m_nvic.h"
  15
  16 #define TYPE_BITBAND "ARM,bitband-memory"
  17 #define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
  18
  19 typedef struct {
  20     /*< private >*/
  21     SysBusDevice parent_obj;
  22     /*< public >*/
  23
  24     MemoryRegion iomem;
  25     uint32_t base;
  26 } BitBandState;
  27
  28 #define TYPE_ARMV7M "armv7m"
  29 #define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M)
  30
  31 #define ARMV7M_NUM_BITBANDS 2
  32
  33 /* ARMv7M container object.
  34  * + Unnamed GPIO input lines: external IRQ lines for the NVIC
  35  * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
  36  * + Property "cpu-model": CPU model to instantiate
  37  * + Property "num-irq": number of external IRQ lines
  38  * + Property "memory": MemoryRegion defining the physical address space
  39  *   that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
  40  *   devices will be automatically layered on top of this view.)
  41  */
  42 typedef struct ARMv7MState {
  43     /*< private >*/
  44     SysBusDevice parent_obj;
  45     /*< public >*/
  46     NVICState nvic;
  47     BitBandState bitband[ARMV7M_NUM_BITBANDS];
  48     ARMCPU *cpu;
  49
  50     /* MemoryRegion we pass to the CPU, with our devices layered on
  51      * top of the ones the board provides in board_memory.
  52      */
  53     MemoryRegion container;
  54
  55     /* Properties */
  56     char *cpu_model;
  57     /* MemoryRegion the board provides to us (with its devices, RAM, etc) */
  58     MemoryRegion *board_memory;
  59 } ARMv7MState;
  60
  61 #endif