target/tricore/cpu.h

   1 /*
   2  *  TriCore emulation for qemu: main CPU struct.
   3  *
   4  *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef TRICORE_CPU_H
  21 #define TRICORE_CPU_H
  22
  23 #include "cpu-qom.h"
  24 #include "exec/cpu-defs.h"
  25 #include "tricore-defs.h"
  26
  27 struct tricore_boot_info;
  28
  29 typedef struct tricore_def_t tricore_def_t;
  30
  31 typedef struct CPUTriCoreState CPUTriCoreState;
  32 struct CPUTriCoreState {
  33     /* GPR Register */
  34     uint32_t gpr_a[16];
  35     uint32_t gpr_d[16];
  36     /* CSFR Register */
  37     uint32_t PCXI;
  38 /* Frequently accessed PSW_USB bits are stored separately for efficiency.
  39        This contains all the other bits.  Use psw_{read,write} to access
  40        the whole PSW.  */
  41     uint32_t PSW;
  42
  43     /* PSW flag cache for faster execution
  44     */
  45     uint32_t PSW_USB_C;
  46     uint32_t PSW_USB_V;   /* Only if bit 31 set, then flag is set  */
  47     uint32_t PSW_USB_SV;  /* Only if bit 31 set, then flag is set  */
  48     uint32_t PSW_USB_AV;  /* Only if bit 31 set, then flag is set. */
  49     uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
  50
  51     uint32_t PC;
  52     uint32_t SYSCON;
  53     uint32_t CPU_ID;
  54     uint32_t CORE_ID;
  55     uint32_t BIV;
  56     uint32_t BTV;
  57     uint32_t ISP;
  58     uint32_t ICR;
  59     uint32_t FCX;
  60     uint32_t LCX;
  61     uint32_t COMPAT;
  62
  63     /* Mem Protection Register */
  64     uint32_t DPR0_0L;
  65     uint32_t DPR0_0U;
  66     uint32_t DPR0_1L;
  67     uint32_t DPR0_1U;
  68     uint32_t DPR0_2L;
  69     uint32_t DPR0_2U;
  70     uint32_t DPR0_3L;
  71     uint32_t DPR0_3U;
  72
  73     uint32_t DPR1_0L;
  74     uint32_t DPR1_0U;
  75     uint32_t DPR1_1L;
  76     uint32_t DPR1_1U;
  77     uint32_t DPR1_2L;
  78     uint32_t DPR1_2U;
  79     uint32_t DPR1_3L;
  80     uint32_t DPR1_3U;
  81
  82     uint32_t DPR2_0L;
  83     uint32_t DPR2_0U;
  84     uint32_t DPR2_1L;
  85     uint32_t DPR2_1U;
  86     uint32_t DPR2_2L;
  87     uint32_t DPR2_2U;
  88     uint32_t DPR2_3L;
  89     uint32_t DPR2_3U;
  90
  91     uint32_t DPR3_0L;
  92     uint32_t DPR3_0U;
  93     uint32_t DPR3_1L;
  94     uint32_t DPR3_1U;
  95     uint32_t DPR3_2L;
  96     uint32_t DPR3_2U;
  97     uint32_t DPR3_3L;
  98     uint32_t DPR3_3U;
  99
 100     uint32_t CPR0_0L;
 101     uint32_t CPR0_0U;
 102     uint32_t CPR0_1L;
 103     uint32_t CPR0_1U;
 104     uint32_t CPR0_2L;
 105     uint32_t CPR0_2U;
 106     uint32_t CPR0_3L;
 107     uint32_t CPR0_3U;
 108
 109     uint32_t CPR1_0L;
 110     uint32_t CPR1_0U;
 111     uint32_t CPR1_1L;
 112     uint32_t CPR1_1U;
 113     uint32_t CPR1_2L;
 114     uint32_t CPR1_2U;
 115     uint32_t CPR1_3L;
 116     uint32_t CPR1_3U;
 117
 118     uint32_t CPR2_0L;
 119     uint32_t CPR2_0U;
 120     uint32_t CPR2_1L;
 121     uint32_t CPR2_1U;
 122     uint32_t CPR2_2L;
 123     uint32_t CPR2_2U;
 124     uint32_t CPR2_3L;
 125     uint32_t CPR2_3U;
 126
 127     uint32_t CPR3_0L;
 128     uint32_t CPR3_0U;
 129     uint32_t CPR3_1L;
 130     uint32_t CPR3_1U;
 131     uint32_t CPR3_2L;
 132     uint32_t CPR3_2U;
 133     uint32_t CPR3_3L;
 134     uint32_t CPR3_3U;
 135
 136     uint32_t DPM0;
 137     uint32_t DPM1;
 138     uint32_t DPM2;
 139     uint32_t DPM3;
 140
 141     uint32_t CPM0;
 142     uint32_t CPM1;
 143     uint32_t CPM2;
 144     uint32_t CPM3;
 145
 146     /* Memory Management Registers */
 147     uint32_t MMU_CON;
 148     uint32_t MMU_ASI;
 149     uint32_t MMU_TVA;
 150     uint32_t MMU_TPA;
 151     uint32_t MMU_TPX;
 152     uint32_t MMU_TFA;
 153     /* {1.3.1 only */
 154     uint32_t BMACON;
 155     uint32_t SMACON;
 156     uint32_t DIEAR;
 157     uint32_t DIETR;
 158     uint32_t CCDIER;
 159     uint32_t MIECON;
 160     uint32_t PIEAR;
 161     uint32_t PIETR;
 162     uint32_t CCPIER;
 163     /*} */
 164     /* Debug Registers */
 165     uint32_t DBGSR;
 166     uint32_t EXEVT;
 167     uint32_t CREVT;
 168     uint32_t SWEVT;
 169     uint32_t TR0EVT;
 170     uint32_t TR1EVT;
 171     uint32_t DMS;
 172     uint32_t DCX;
 173     uint32_t DBGTCR;
 174     uint32_t CCTRL;
 175     uint32_t CCNT;
 176     uint32_t ICNT;
 177     uint32_t M1CNT;
 178     uint32_t M2CNT;
 179     uint32_t M3CNT;
 180     /* Floating Point Registers */
 181     float_status fp_status;
 182     /* QEMU */
 183     int error_code;
 184     uint32_t hflags;    /* CPU State */
 185
 186     /* Internal CPU feature flags.  */
 187     uint64_t features;
 188
 189     const tricore_def_t *cpu_model;
 190     void *irq[8];
 191     struct QEMUTimer *timer; /* Internal timer */
 192 };
 193
 194 /**
 195  * TriCoreCPU:
 196  * @env: #CPUTriCoreState
 197  *
 198  * A TriCore CPU.
 199  */
 200 struct TriCoreCPU {
 201     /*< private >*/
 202     CPUState parent_obj;
 203     /*< public >*/
 204
 205     CPUNegativeOffsetState neg;
 206     CPUTriCoreState env;
 207 };
 208
 209
 210 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 211 void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 212
 213
 214 #define MASK_PCXI_PCPN 0xff000000
 215 #define MASK_PCXI_PIE_1_3  0x00800000
 216 #define MASK_PCXI_PIE_1_6  0x00200000
 217 #define MASK_PCXI_UL   0x00400000
 218 #define MASK_PCXI_PCXS 0x000f0000
 219 #define MASK_PCXI_PCXO 0x0000ffff
 220
 221 #define MASK_PSW_USB 0xff000000
 222 #define MASK_USB_C   0x80000000
 223 #define MASK_USB_V   0x40000000
 224 #define MASK_USB_SV  0x20000000
 225 #define MASK_USB_AV  0x10000000
 226 #define MASK_USB_SAV 0x08000000
 227 #define MASK_PSW_PRS 0x00003000
 228 #define MASK_PSW_IO  0x00000c00
 229 #define MASK_PSW_IS  0x00000200
 230 #define MASK_PSW_GW  0x00000100
 231 #define MASK_PSW_CDE 0x00000080
 232 #define MASK_PSW_CDC 0x0000007f
 233 #define MASK_PSW_FPU_RM 0x3000000
 234
 235 #define MASK_SYSCON_PRO_TEN 0x2
 236 #define MASK_SYSCON_FCD_SF  0x1
 237
 238 #define MASK_CPUID_MOD     0xffff0000
 239 #define MASK_CPUID_MOD_32B 0x0000ff00
 240 #define MASK_CPUID_REV     0x000000ff
 241
 242 #define MASK_ICR_PIPN 0x00ff0000
 243 #define MASK_ICR_IE_1_3   0x00000100
 244 #define MASK_ICR_IE_1_6   0x00008000
 245 #define MASK_ICR_CCPN 0x000000ff
 246
 247 #define MASK_FCX_FCXS 0x000f0000
 248 #define MASK_FCX_FCXO 0x0000ffff
 249
 250 #define MASK_LCX_LCXS 0x000f0000
 251 #define MASK_LCX_LCX0 0x0000ffff
 252
 253 #define MASK_DBGSR_DE 0x1
 254 #define MASK_DBGSR_HALT 0x6
 255 #define MASK_DBGSR_SUSP 0x10
 256 #define MASK_DBGSR_PREVSUSP 0x20
 257 #define MASK_DBGSR_PEVT 0x40
 258 #define MASK_DBGSR_EVTSRC 0x1f00
 259
 260 #define TRICORE_HFLAG_KUU     0x3
 261 #define TRICORE_HFLAG_UM0     0x00002 /* user mode-0 flag          */
 262 #define TRICORE_HFLAG_UM1     0x00001 /* user mode-1 flag          */
 263 #define TRICORE_HFLAG_SM      0x00000 /* kernel mode flag          */
 264
 265 enum tricore_features {
 266     TRICORE_FEATURE_13,
 267     TRICORE_FEATURE_131,
 268     TRICORE_FEATURE_16,
 269     TRICORE_FEATURE_161,
 270 };
 271
 272 static inline int tricore_feature(CPUTriCoreState *env, int feature)
 273 {
 274     return (env->features & (1ULL << feature)) != 0;
 275 }
 276
 277 /* TriCore Traps Classes*/
 278 enum {
 279     TRAPC_NONE     = -1,
 280     TRAPC_MMU      = 0,
 281     TRAPC_PROT     = 1,
 282     TRAPC_INSN_ERR = 2,
 283     TRAPC_CTX_MNG  = 3,
 284     TRAPC_SYSBUS   = 4,
 285     TRAPC_ASSERT   = 5,
 286     TRAPC_SYSCALL  = 6,
 287     TRAPC_NMI      = 7,
 288     TRAPC_IRQ      = 8
 289 };
 290
 291 /* Class 0 TIN */
 292 enum {
 293     TIN0_VAF = 0,
 294     TIN0_VAP = 1,
 295 };
 296
 297 /* Class 1 TIN */
 298 enum {
 299     TIN1_PRIV = 1,
 300     TIN1_MPR  = 2,
 301     TIN1_MPW  = 3,
 302     TIN1_MPX  = 4,
 303     TIN1_MPP  = 5,
 304     TIN1_MPN  = 6,
 305     TIN1_GRWP = 7,
 306 };
 307
 308 /* Class 2 TIN */
 309 enum {
 310     TIN2_IOPC = 1,
 311     TIN2_UOPC = 2,
 312     TIN2_OPD  = 3,
 313     TIN2_ALN  = 4,
 314     TIN2_MEM  = 5,
 315 };
 316
 317 /* Class 3 TIN */
 318 enum {
 319     TIN3_FCD  = 1,
 320     TIN3_CDO  = 2,
 321     TIN3_CDU  = 3,
 322     TIN3_FCU  = 4,
 323     TIN3_CSU  = 5,
 324     TIN3_CTYP = 6,
 325     TIN3_NEST = 7,
 326 };
 327
 328 /* Class 4 TIN */
 329 enum {
 330     TIN4_PSE = 1,
 331     TIN4_DSE = 2,
 332     TIN4_DAE = 3,
 333     TIN4_CAE = 4,
 334     TIN4_PIE = 5,
 335     TIN4_DIE = 6,
 336 };
 337
 338 /* Class 5 TIN */
 339 enum {
 340     TIN5_OVF  = 1,
 341     TIN5_SOVF = 1,
 342 };
 343
 344 /* Class 6 TIN
 345  *
 346  * Is always TIN6_SYS
 347  */
 348
 349 /* Class 7 TIN */
 350 enum {
 351     TIN7_NMI = 0,
 352 };
 353
 354 uint32_t psw_read(CPUTriCoreState *env);
 355 void psw_write(CPUTriCoreState *env, uint32_t val);
 356
 357 void fpu_set_state(CPUTriCoreState *env);
 358
 359 #define MMU_USER_IDX 2
 360
 361 void tricore_cpu_list(void);
 362
 363 #define cpu_signal_handler cpu_tricore_signal_handler
 364 #define cpu_list tricore_cpu_list
 365
 366 static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
 367 {
 368     return 0;
 369 }
 370
 371 typedef CPUTriCoreState CPUArchState;
 372 typedef TriCoreCPU ArchCPU;
 373
 374 #include "exec/cpu-all.h"
 375
 376 enum {
 377     /* 1 bit to define user level / supervisor access */
 378     ACCESS_USER  = 0x00,
 379     ACCESS_SUPER = 0x01,
 380     /* 1 bit to indicate direction */
 381     ACCESS_STORE = 0x02,
 382     /* Type of instruction that generated the access */
 383     ACCESS_CODE  = 0x10, /* Code fetch access                */
 384     ACCESS_INT   = 0x20, /* Integer load/store access        */
 385     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 386 };
 387
 388 void cpu_state_reset(CPUTriCoreState *s);
 389 void tricore_tcg_init(void);
 390 int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc);
 391
 392 static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc,
 393                                         target_ulong *cs_base, uint32_t *flags)
 394 {
 395     *pc = env->PC;
 396     *cs_base = 0;
 397     *flags = 0;
 398 }
 399
 400 #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
 401 #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
 402 #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU
 403
 404 /* helpers.c */
 405 bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 406                           MMUAccessType access_type, int mmu_idx,
 407                           bool probe, uintptr_t retaddr);
 408
 409 #endif /* TRICORE_CPU_H */