hw/char/stm32f2xx_usart.c

   1 /*
   2  * STM32F2XX USART
   3  *
   4  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/char/stm32f2xx_usart.h"
  27 #include "qemu/log.h"
  28
  29 #ifndef STM_USART_ERR_DEBUG
  30 #define STM_USART_ERR_DEBUG 0
  31 #endif
  32
  33 #define DB_PRINT_L(lvl, fmt, args...) do { \
  34     if (STM_USART_ERR_DEBUG >= lvl) { \
  35         qemu_log("%s: " fmt, __func__, ## args); \
  36     } \
  37 } while (0)
  38
  39 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
  40
  41 static int stm32f2xx_usart_can_receive(void *opaque)
  42 {
  43     STM32F2XXUsartState *s = opaque;
  44
  45     if (!(s->usart_sr & USART_SR_RXNE)) {
  46         return 1;
  47     }
  48
  49     return 0;
  50 }
  51
  52 static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
  53 {
  54     STM32F2XXUsartState *s = opaque;
  55
  56     if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
  57         /* USART not enabled - drop the chars */
  58         DB_PRINT("Dropping the chars\n");
  59         return;
  60     }
  61
  62     s->usart_dr = *buf;
  63     s->usart_sr |= USART_SR_RXNE;
  64
  65     if (s->usart_cr1 & USART_CR1_RXNEIE) {
  66         qemu_set_irq(s->irq, 1);
  67     }
  68
  69     DB_PRINT("Receiving: %c\n", s->usart_dr);
  70 }
  71
  72 static void stm32f2xx_usart_reset(DeviceState *dev)
  73 {
  74     STM32F2XXUsartState *s = STM32F2XX_USART(dev);
  75
  76     s->usart_sr = USART_SR_RESET;
  77     s->usart_dr = 0x00000000;
  78     s->usart_brr = 0x00000000;
  79     s->usart_cr1 = 0x00000000;
  80     s->usart_cr2 = 0x00000000;
  81     s->usart_cr3 = 0x00000000;
  82     s->usart_gtpr = 0x00000000;
  83
  84     qemu_set_irq(s->irq, 0);
  85 }
  86
  87 static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
  88                                        unsigned int size)
  89 {
  90     STM32F2XXUsartState *s = opaque;
  91     uint64_t retvalue;
  92
  93     DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
  94
  95     switch (addr) {
  96     case USART_SR:
  97         retvalue = s->usart_sr;
  98         qemu_chr_fe_accept_input(&s->chr);
  99         return retvalue;
 100     case USART_DR:
 101         DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
 102         s->usart_sr &= ~USART_SR_RXNE;
 103         qemu_chr_fe_accept_input(&s->chr);
 104         qemu_set_irq(s->irq, 0);
 105         return s->usart_dr & 0x3FF;
 106     case USART_BRR:
 107         return s->usart_brr;
 108     case USART_CR1:
 109         return s->usart_cr1;
 110     case USART_CR2:
 111         return s->usart_cr2;
 112     case USART_CR3:
 113         return s->usart_cr3;
 114     case USART_GTPR:
 115         return s->usart_gtpr;
 116     default:
 117         qemu_log_mask(LOG_GUEST_ERROR,
 118                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 119         return 0;
 120     }
 121
 122     return 0;
 123 }
 124
 125 static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
 126                                   uint64_t val64, unsigned int size)
 127 {
 128     STM32F2XXUsartState *s = opaque;
 129     uint32_t value = val64;
 130     unsigned char ch;
 131
 132     DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);
 133
 134     switch (addr) {
 135     case USART_SR:
 136         if (value <= 0x3FF) {
 137             /* I/O being synchronous, TXE is always set. In addition, it may
 138                only be set by hardware, so keep it set here. */
 139             s->usart_sr = value | USART_SR_TXE;
 140         } else {
 141             s->usart_sr &= value;
 142         }
 143         if (!(s->usart_sr & USART_SR_RXNE)) {
 144             qemu_set_irq(s->irq, 0);
 145         }
 146         return;
 147     case USART_DR:
 148         if (value < 0xF000) {
 149             ch = value;
 150             /* XXX this blocks entire thread. Rewrite to use
 151              * qemu_chr_fe_write and background I/O callbacks */
 152             qemu_chr_fe_write_all(&s->chr, &ch, 1);
 153             /* XXX I/O are currently synchronous, making it impossible for
 154                software to observe transient states where TXE or TC aren't
 155                set. Unlike TXE however, which is read-only, software may
 156                clear TC by writing 0 to the SR register, so set it again
 157                on each write. */
 158             s->usart_sr |= USART_SR_TC;
 159         }
 160         return;
 161     case USART_BRR:
 162         s->usart_brr = value;
 163         return;
 164     case USART_CR1:
 165         s->usart_cr1 = value;
 166             if (s->usart_cr1 & USART_CR1_RXNEIE &&
 167                 s->usart_sr & USART_SR_RXNE) {
 168                 qemu_set_irq(s->irq, 1);
 169             }
 170         return;
 171     case USART_CR2:
 172         s->usart_cr2 = value;
 173         return;
 174     case USART_CR3:
 175         s->usart_cr3 = value;
 176         return;
 177     case USART_GTPR:
 178         s->usart_gtpr = value;
 179         return;
 180     default:
 181         qemu_log_mask(LOG_GUEST_ERROR,
 182                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 183     }
 184 }
 185
 186 static const MemoryRegionOps stm32f2xx_usart_ops = {
 187     .read = stm32f2xx_usart_read,
 188     .write = stm32f2xx_usart_write,
 189     .endianness = DEVICE_NATIVE_ENDIAN,
 190 };
 191
 192 static Property stm32f2xx_usart_properties[] = {
 193     DEFINE_PROP_CHR("chardev", STM32F2XXUsartState, chr),
 194     DEFINE_PROP_END_OF_LIST(),
 195 };
 196
 197 static void stm32f2xx_usart_init(Object *obj)
 198 {
 199     STM32F2XXUsartState *s = STM32F2XX_USART(obj);
 200
 201     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 202
 203     memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
 204                           TYPE_STM32F2XX_USART, 0x400);
 205     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 206 }
 207
 208 static void stm32f2xx_usart_realize(DeviceState *dev, Error **errp)
 209 {
 210     STM32F2XXUsartState *s = STM32F2XX_USART(dev);
 211
 212     qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive,
 213                              stm32f2xx_usart_receive, NULL, NULL,
 214                              s, NULL, true);
 215 }
 216
 217 static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data)
 218 {
 219     DeviceClass *dc = DEVICE_CLASS(klass);
 220
 221     dc->reset = stm32f2xx_usart_reset;
 222     dc->props = stm32f2xx_usart_properties;
 223     dc->realize = stm32f2xx_usart_realize;
 224 }
 225
 226 static const TypeInfo stm32f2xx_usart_info = {
 227     .name          = TYPE_STM32F2XX_USART,
 228     .parent        = TYPE_SYS_BUS_DEVICE,
 229     .instance_size = sizeof(STM32F2XXUsartState),
 230     .instance_init = stm32f2xx_usart_init,
 231     .class_init    = stm32f2xx_usart_class_init,
 232 };
 233
 234 static void stm32f2xx_usart_register_types(void)
 235 {
 236     type_register_static(&stm32f2xx_usart_info);
 237 }
 238
 239 type_init(stm32f2xx_usart_register_types)