hw/intc/apic_common.c

   1 /*
   2  *  APIC support - common bits of emulated and KVM kernel model
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  19  */
  20 #include "qemu/osdep.h"
  21 #include "qemu/error-report.h"
  22 #include "qapi/error.h"
  23 #include "qemu-common.h"
  24 #include "cpu.h"
  25 #include "qapi/visitor.h"
  26 #include "hw/i386/apic.h"
  27 #include "hw/i386/apic_internal.h"
  28 #include "trace.h"
  29 #include "sysemu/kvm.h"
  30 #include "hw/qdev.h"
  31 #include "hw/sysbus.h"
  32
  33 static int apic_irq_delivered;
  34 bool apic_report_tpr_access;
  35
  36 void cpu_set_apic_base(DeviceState *dev, uint64_t val)
  37 {
  38     trace_cpu_set_apic_base(val);
  39
  40     if (dev) {
  41         APICCommonState *s = APIC_COMMON(dev);
  42         APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  43         /* switching to x2APIC, reset possibly modified xAPIC ID */
  44         if (!(s->apicbase & MSR_IA32_APICBASE_EXTD) &&
  45             (val & MSR_IA32_APICBASE_EXTD)) {
  46             s->id = s->initial_apic_id;
  47         }
  48         info->set_base(s, val);
  49     }
  50 }
  51
  52 uint64_t cpu_get_apic_base(DeviceState *dev)
  53 {
  54     if (dev) {
  55         APICCommonState *s = APIC_COMMON(dev);
  56         trace_cpu_get_apic_base((uint64_t)s->apicbase);
  57         return s->apicbase;
  58     } else {
  59         trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
  60         return MSR_IA32_APICBASE_BSP;
  61     }
  62 }
  63
  64 void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
  65 {
  66     APICCommonState *s;
  67     APICCommonClass *info;
  68
  69     if (!dev) {
  70         return;
  71     }
  72
  73     s = APIC_COMMON(dev);
  74     info = APIC_COMMON_GET_CLASS(s);
  75
  76     info->set_tpr(s, val);
  77 }
  78
  79 uint8_t cpu_get_apic_tpr(DeviceState *dev)
  80 {
  81     APICCommonState *s;
  82     APICCommonClass *info;
  83
  84     if (!dev) {
  85         return 0;
  86     }
  87
  88     s = APIC_COMMON(dev);
  89     info = APIC_COMMON_GET_CLASS(s);
  90
  91     return info->get_tpr(s);
  92 }
  93
  94 void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
  95 {
  96     APICCommonState *s = APIC_COMMON(dev);
  97     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  98
  99     apic_report_tpr_access = enable;
 100     if (info->enable_tpr_reporting) {
 101         info->enable_tpr_reporting(s, enable);
 102     }
 103 }
 104
 105 void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
 106 {
 107     APICCommonState *s = APIC_COMMON(dev);
 108     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 109
 110     s->vapic_paddr = paddr;
 111     info->vapic_base_update(s);
 112 }
 113
 114 void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
 115                                    TPRAccess access)
 116 {
 117     APICCommonState *s = APIC_COMMON(dev);
 118
 119     vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
 120 }
 121
 122 void apic_report_irq_delivered(int delivered)
 123 {
 124     apic_irq_delivered += delivered;
 125
 126     trace_apic_report_irq_delivered(apic_irq_delivered);
 127 }
 128
 129 void apic_reset_irq_delivered(void)
 130 {
 131     /* Copy this into a local variable to encourage gcc to emit a plain
 132      * register for a sys/sdt.h marker.  For details on this workaround, see:
 133      * https://sourceware.org/bugzilla/show_bug.cgi?id=13296
 134      */
 135     volatile int a_i_d = apic_irq_delivered;
 136     trace_apic_reset_irq_delivered(a_i_d);
 137
 138     apic_irq_delivered = 0;
 139 }
 140
 141 int apic_get_irq_delivered(void)
 142 {
 143     trace_apic_get_irq_delivered(apic_irq_delivered);
 144
 145     return apic_irq_delivered;
 146 }
 147
 148 void apic_deliver_nmi(DeviceState *dev)
 149 {
 150     APICCommonState *s = APIC_COMMON(dev);
 151     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 152
 153     info->external_nmi(s);
 154 }
 155
 156 bool apic_next_timer(APICCommonState *s, int64_t current_time)
 157 {
 158     int64_t d;
 159
 160     /* We need to store the timer state separately to support APIC
 161      * implementations that maintain a non-QEMU timer, e.g. inside the
 162      * host kernel. This open-coded state allows us to migrate between
 163      * both models. */
 164     s->timer_expiry = -1;
 165
 166     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
 167         return false;
 168     }
 169
 170     d = (current_time - s->initial_count_load_time) >> s->count_shift;
 171
 172     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 173         if (!s->initial_count) {
 174             return false;
 175         }
 176         d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
 177             ((uint64_t)s->initial_count + 1);
 178     } else {
 179         if (d >= s->initial_count) {
 180             return false;
 181         }
 182         d = (uint64_t)s->initial_count + 1;
 183     }
 184     s->next_time = s->initial_count_load_time + (d << s->count_shift);
 185     s->timer_expiry = s->next_time;
 186     return true;
 187 }
 188
 189 void apic_init_reset(DeviceState *dev)
 190 {
 191     APICCommonState *s;
 192     APICCommonClass *info;
 193     int i;
 194
 195     if (!dev) {
 196         return;
 197     }
 198     s = APIC_COMMON(dev);
 199     s->tpr = 0;
 200     s->spurious_vec = 0xff;
 201     s->log_dest = 0;
 202     s->dest_mode = 0xf;
 203     memset(s->isr, 0, sizeof(s->isr));
 204     memset(s->tmr, 0, sizeof(s->tmr));
 205     memset(s->irr, 0, sizeof(s->irr));
 206     for (i = 0; i < APIC_LVT_NB; i++) {
 207         s->lvt[i] = APIC_LVT_MASKED;
 208     }
 209     s->esr = 0;
 210     memset(s->icr, 0, sizeof(s->icr));
 211     s->divide_conf = 0;
 212     s->count_shift = 0;
 213     s->initial_count = 0;
 214     s->initial_count_load_time = 0;
 215     s->next_time = 0;
 216     s->wait_for_sipi = !cpu_is_bsp(s->cpu);
 217
 218     if (s->timer) {
 219         timer_del(s->timer);
 220     }
 221     s->timer_expiry = -1;
 222
 223     info = APIC_COMMON_GET_CLASS(s);
 224     if (info->reset) {
 225         info->reset(s);
 226     }
 227 }
 228
 229 void apic_designate_bsp(DeviceState *dev, bool bsp)
 230 {
 231     if (dev == NULL) {
 232         return;
 233     }
 234
 235     APICCommonState *s = APIC_COMMON(dev);
 236     if (bsp) {
 237         s->apicbase |= MSR_IA32_APICBASE_BSP;
 238     } else {
 239         s->apicbase &= ~MSR_IA32_APICBASE_BSP;
 240     }
 241 }
 242
 243 static void apic_reset_common(DeviceState *dev)
 244 {
 245     APICCommonState *s = APIC_COMMON(dev);
 246     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 247     uint32_t bsp;
 248
 249     bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
 250     s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
 251     s->id = s->initial_apic_id;
 252
 253     s->vapic_paddr = 0;
 254     info->vapic_base_update(s);
 255
 256     apic_init_reset(dev);
 257 }
 258
 259 /* This function is only used for old state version 1 and 2 */
 260 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 261 {
 262     APICCommonState *s = opaque;
 263     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 264     int i;
 265
 266     if (version_id > 2) {
 267         return -EINVAL;
 268     }
 269
 270     /* XXX: what if the base changes? (registered memory regions) */
 271     qemu_get_be32s(f, &s->apicbase);
 272     qemu_get_8s(f, &s->id);
 273     qemu_get_8s(f, &s->arb_id);
 274     qemu_get_8s(f, &s->tpr);
 275     qemu_get_be32s(f, &s->spurious_vec);
 276     qemu_get_8s(f, &s->log_dest);
 277     qemu_get_8s(f, &s->dest_mode);
 278     for (i = 0; i < 8; i++) {
 279         qemu_get_be32s(f, &s->isr[i]);
 280         qemu_get_be32s(f, &s->tmr[i]);
 281         qemu_get_be32s(f, &s->irr[i]);
 282     }
 283     for (i = 0; i < APIC_LVT_NB; i++) {
 284         qemu_get_be32s(f, &s->lvt[i]);
 285     }
 286     qemu_get_be32s(f, &s->esr);
 287     qemu_get_be32s(f, &s->icr[0]);
 288     qemu_get_be32s(f, &s->icr[1]);
 289     qemu_get_be32s(f, &s->divide_conf);
 290     s->count_shift = qemu_get_be32(f);
 291     qemu_get_be32s(f, &s->initial_count);
 292     s->initial_count_load_time = qemu_get_be64(f);
 293     s->next_time = qemu_get_be64(f);
 294
 295     if (version_id >= 2) {
 296         s->timer_expiry = qemu_get_be64(f);
 297     }
 298
 299     if (info->post_load) {
 300         info->post_load(s);
 301     }
 302     return 0;
 303 }
 304
 305 static const VMStateDescription vmstate_apic_common;
 306
 307 static void apic_common_realize(DeviceState *dev, Error **errp)
 308 {
 309     APICCommonState *s = APIC_COMMON(dev);
 310     APICCommonClass *info;
 311     static DeviceState *vapic;
 312     int instance_id = s->id;
 313
 314     info = APIC_COMMON_GET_CLASS(s);
 315     info->realize(dev, errp);
 316
 317     /* Note: We need at least 1M to map the VAPIC option ROM */
 318     if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
 319         ram_size >= 1024 * 1024) {
 320         vapic = sysbus_create_simple("kvmvapic", -1, NULL);
 321     }
 322     s->vapic = vapic;
 323     if (apic_report_tpr_access && info->enable_tpr_reporting) {
 324         info->enable_tpr_reporting(s, true);
 325     }
 326
 327     if (s->legacy_instance_id) {
 328         instance_id = -1;
 329     }
 330     vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common,
 331                                    s, -1, 0);
 332 }
 333
 334 static void apic_common_unrealize(DeviceState *dev, Error **errp)
 335 {
 336     APICCommonState *s = APIC_COMMON(dev);
 337     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 338
 339     vmstate_unregister(NULL, &vmstate_apic_common, s);
 340     info->unrealize(dev, errp);
 341
 342     if (apic_report_tpr_access && info->enable_tpr_reporting) {
 343         info->enable_tpr_reporting(s, false);
 344     }
 345 }
 346
 347 static int apic_pre_load(void *opaque)
 348 {
 349     APICCommonState *s = APIC_COMMON(opaque);
 350
 351     /* The default is !cpu_is_bsp(s->cpu), but the common value is 0
 352      * so that's what apic_common_sipi_needed checks for.  Reset to
 353      * the value that is assumed when the apic_sipi subsection is
 354      * absent.
 355      */
 356     s->wait_for_sipi = 0;
 357     return 0;
 358 }
 359
 360 static void apic_dispatch_pre_save(void *opaque)
 361 {
 362     APICCommonState *s = APIC_COMMON(opaque);
 363     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 364
 365     if (info->pre_save) {
 366         info->pre_save(s);
 367     }
 368 }
 369
 370 static int apic_dispatch_post_load(void *opaque, int version_id)
 371 {
 372     APICCommonState *s = APIC_COMMON(opaque);
 373     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 374
 375     if (info->post_load) {
 376         info->post_load(s);
 377     }
 378     return 0;
 379 }
 380
 381 static bool apic_common_sipi_needed(void *opaque)
 382 {
 383     APICCommonState *s = APIC_COMMON(opaque);
 384     return s->wait_for_sipi != 0;
 385 }
 386
 387 static const VMStateDescription vmstate_apic_common_sipi = {
 388     .name = "apic_sipi",
 389     .version_id = 1,
 390     .minimum_version_id = 1,
 391     .needed = apic_common_sipi_needed,
 392     .fields = (VMStateField[]) {
 393         VMSTATE_INT32(sipi_vector, APICCommonState),
 394         VMSTATE_INT32(wait_for_sipi, APICCommonState),
 395         VMSTATE_END_OF_LIST()
 396     }
 397 };
 398
 399 static const VMStateDescription vmstate_apic_common = {
 400     .name = "apic",
 401     .version_id = 3,
 402     .minimum_version_id = 3,
 403     .minimum_version_id_old = 1,
 404     .load_state_old = apic_load_old,
 405     .pre_load = apic_pre_load,
 406     .pre_save = apic_dispatch_pre_save,
 407     .post_load = apic_dispatch_post_load,
 408     .fields = (VMStateField[]) {
 409         VMSTATE_UINT32(apicbase, APICCommonState),
 410         VMSTATE_UINT8(id, APICCommonState),
 411         VMSTATE_UINT8(arb_id, APICCommonState),
 412         VMSTATE_UINT8(tpr, APICCommonState),
 413         VMSTATE_UINT32(spurious_vec, APICCommonState),
 414         VMSTATE_UINT8(log_dest, APICCommonState),
 415         VMSTATE_UINT8(dest_mode, APICCommonState),
 416         VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
 417         VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
 418         VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
 419         VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
 420         VMSTATE_UINT32(esr, APICCommonState),
 421         VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
 422         VMSTATE_UINT32(divide_conf, APICCommonState),
 423         VMSTATE_INT32(count_shift, APICCommonState),
 424         VMSTATE_UINT32(initial_count, APICCommonState),
 425         VMSTATE_INT64(initial_count_load_time, APICCommonState),
 426         VMSTATE_INT64(next_time, APICCommonState),
 427         VMSTATE_INT64(timer_expiry,
 428                       APICCommonState), /* open-coded timer state */
 429         VMSTATE_END_OF_LIST()
 430     },
 431     .subsections = (const VMStateDescription*[]) {
 432         &vmstate_apic_common_sipi,
 433         NULL
 434     }
 435 };
 436
 437 static Property apic_properties_common[] = {
 438     DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
 439     DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
 440                     true),
 441     DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id,
 442                      false),
 443     DEFINE_PROP_END_OF_LIST(),
 444 };
 445
 446 static void apic_common_get_id(Object *obj, Visitor *v, const char *name,
 447                                void *opaque, Error **errp)
 448 {
 449     APICCommonState *s = APIC_COMMON(obj);
 450     int64_t value;
 451
 452     value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id;
 453     visit_type_int(v, name, &value, errp);
 454 }
 455
 456 static void apic_common_set_id(Object *obj, Visitor *v, const char *name,
 457                                void *opaque, Error **errp)
 458 {
 459     APICCommonState *s = APIC_COMMON(obj);
 460     DeviceState *dev = DEVICE(obj);
 461     Error *local_err = NULL;
 462     int64_t value;
 463
 464     if (dev->realized) {
 465         qdev_prop_set_after_realize(dev, name, errp);
 466         return;
 467     }
 468
 469     visit_type_int(v, name, &value, &local_err);
 470     if (local_err) {
 471         error_propagate(errp, local_err);
 472         return;
 473     }
 474
 475     s->initial_apic_id = value;
 476     s->id = (uint8_t)value;
 477 }
 478
 479 static void apic_common_initfn(Object *obj)
 480 {
 481     APICCommonState *s = APIC_COMMON(obj);
 482
 483     s->id = s->initial_apic_id = -1;
 484     object_property_add(obj, "id", "int",
 485                         apic_common_get_id,
 486                         apic_common_set_id, NULL, NULL, NULL);
 487 }
 488
 489 static void apic_common_class_init(ObjectClass *klass, void *data)
 490 {
 491     DeviceClass *dc = DEVICE_CLASS(klass);
 492
 493     dc->reset = apic_reset_common;
 494     dc->props = apic_properties_common;
 495     dc->realize = apic_common_realize;
 496     dc->unrealize = apic_common_unrealize;
 497     /*
 498      * Reason: APIC and CPU need to be wired up by
 499      * x86_cpu_apic_create()
 500      */
 501     dc->cannot_instantiate_with_device_add_yet = true;
 502 }
 503
 504 static const TypeInfo apic_common_type = {
 505     .name = TYPE_APIC_COMMON,
 506     .parent = TYPE_DEVICE,
 507     .instance_size = sizeof(APICCommonState),
 508     .instance_init = apic_common_initfn,
 509     .class_size = sizeof(APICCommonClass),
 510     .class_init = apic_common_class_init,
 511     .abstract = true,
 512 };
 513
 514 static void apic_common_register_types(void)
 515 {
 516     type_register_static(&apic_common_type);
 517 }
 518
 519 type_init(apic_common_register_types)