hw/arm/allwinner-a10.c

   1 /*
   2  * Allwinner A10 SoC emulation
   3  *
   4  * Copyright (C) 2013 Li Guang
   5  * Written by Li Guang <lig.fnst@cn.fujitsu.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu/module.h"
  21 #include "hw/char/serial.h"
  22 #include "hw/sysbus.h"
  23 #include "hw/arm/allwinner-a10.h"
  24 #include "hw/misc/unimp.h"
  25 #include "sysemu/sysemu.h"
  26 #include "hw/boards.h"
  27 #include "hw/usb/hcd-ohci.h"
  28 #include "hw/loader.h"
  29
  30 #define AW_A10_SRAM_A_BASE      0x00000000
  31 #define AW_A10_DRAMC_BASE       0x01c01000
  32 #define AW_A10_MMC0_BASE        0x01c0f000
  33 #define AW_A10_CCM_BASE         0x01c20000
  34 #define AW_A10_PIC_REG_BASE     0x01c20400
  35 #define AW_A10_PIT_REG_BASE     0x01c20c00
  36 #define AW_A10_UART0_REG_BASE   0x01c28000
  37 #define AW_A10_EMAC_BASE        0x01c0b000
  38 #define AW_A10_EHCI_BASE        0x01c14000
  39 #define AW_A10_OHCI_BASE        0x01c14400
  40 #define AW_A10_SATA_BASE        0x01c18000
  41 #define AW_A10_WDT_BASE         0x01c20c90
  42 #define AW_A10_RTC_BASE         0x01c20d00
  43 #define AW_A10_I2C0_BASE        0x01c2ac00
  44
  45 void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk)
  46 {
  47     const int64_t rom_size = 32 * KiB;
  48     g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
  49
  50     if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
  51         error_setg(&error_fatal, "%s: failed to read BlockBackend data",
  52                    __func__);
  53         return;
  54     }
  55
  56     rom_add_blob("allwinner-a10.bootrom", buffer, rom_size,
  57                   rom_size, AW_A10_SRAM_A_BASE,
  58                   NULL, NULL, NULL, NULL, false);
  59 }
  60
  61 static void aw_a10_init(Object *obj)
  62 {
  63     AwA10State *s = AW_A10(obj);
  64
  65     object_initialize_child(obj, "cpu", &s->cpu,
  66                             ARM_CPU_TYPE_NAME("cortex-a8"));
  67
  68     object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC);
  69
  70     object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
  71
  72     object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
  73
  74     object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC);
  75
  76     object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
  77
  78     object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
  79
  80     object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C);
  81
  82     for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
  83         object_initialize_child(obj, "ehci[*]", &s->ehci[i],
  84                                 TYPE_PLATFORM_EHCI);
  85         object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_OHCI);
  86     }
  87
  88     object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);
  89
  90     object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);
  91
  92     object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I);
  93 }
  94
  95 static void aw_a10_realize(DeviceState *dev, Error **errp)
  96 {
  97     AwA10State *s = AW_A10(dev);
  98     SysBusDevice *sysbusdev;
  99
 100     if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
 101         return;
 102     }
 103
 104     if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) {
 105         return;
 106     }
 107     sysbusdev = SYS_BUS_DEVICE(&s->intc);
 108     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
 109     sysbus_connect_irq(sysbusdev, 0,
 110                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
 111     sysbus_connect_irq(sysbusdev, 1,
 112                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
 113     qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
 114
 115     if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
 116         return;
 117     }
 118     sysbusdev = SYS_BUS_DEVICE(&s->timer);
 119     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
 120     sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22));
 121     sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23));
 122     sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24));
 123     sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25));
 124     sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67));
 125     sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68));
 126
 127     memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
 128                            &error_fatal);
 129     memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
 130     create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
 131
 132     /* Clock Control Module */
 133     sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
 134     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
 135
 136     /* DRAM Control Module */
 137     sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
 138     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE);
 139
 140     /* FIXME use qdev NIC properties instead of nd_table[] */
 141     if (nd_table[0].used) {
 142         qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
 143         qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
 144     }
 145     if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) {
 146         return;
 147     }
 148     sysbusdev = SYS_BUS_DEVICE(&s->emac);
 149     sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
 150     sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));
 151
 152     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
 153         return;
 154     }
 155     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
 156     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56));
 157
 158     /* FIXME use a qdev chardev prop instead of serial_hd() */
 159     serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
 160                    qdev_get_gpio_in(dev, 1),
 161                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
 162
 163     for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
 164         g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
 165
 166         object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable",
 167                                  true, &error_fatal);
 168         sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
 169         sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
 170                         AW_A10_EHCI_BASE + i * 0x8000);
 171         sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
 172                            qdev_get_gpio_in(dev, 39 + i));
 173
 174         object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
 175                                 &error_fatal);
 176         sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
 177         sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
 178                         AW_A10_OHCI_BASE + i * 0x8000);
 179         sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
 180                            qdev_get_gpio_in(dev, 64 + i));
 181     }
 182
 183     /* SD/MMC */
 184     object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
 185                              OBJECT(get_system_memory()), &error_fatal);
 186     sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
 187     sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
 188     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
 189     object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
 190                               "sd-bus");
 191
 192     /* RTC */
 193     sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
 194     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
 195
 196     /* I2C */
 197     sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
 198     sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);
 199     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));
 200
 201     /* WDT */
 202     sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
 203     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0, AW_A10_WDT_BASE, 1);
 204 }
 205
 206 static void aw_a10_class_init(ObjectClass *oc, void *data)
 207 {
 208     DeviceClass *dc = DEVICE_CLASS(oc);
 209
 210     dc->realize = aw_a10_realize;
 211     /* Reason: Uses serial_hds and nd_table in realize function */
 212     dc->user_creatable = false;
 213 }
 214
 215 static const TypeInfo aw_a10_type_info = {
 216     .name = TYPE_AW_A10,
 217     .parent = TYPE_DEVICE,
 218     .instance_size = sizeof(AwA10State),
 219     .instance_init = aw_a10_init,
 220     .class_init = aw_a10_class_init,
 221 };
 222
 223 static void aw_a10_register_types(void)
 224 {
 225     type_register_static(&aw_a10_type_info);
 226 }
 227
 228 type_init(aw_a10_register_types)