2 * ARM Integrator CP System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
13 #include "hw/sysbus.h"
14 #include "hw/boards.h"
15 #include "hw/arm/boot.h"
16 #include "hw/misc/arm_integrator_debug.h"
17 #include "hw/net/smc91c111.h"
19 #include "exec/address-spaces.h"
20 #include "sysemu/sysemu.h"
21 #include "qemu/error-report.h"
22 #include "hw/char/pl011.h"
24 #define TYPE_INTEGRATOR_CM "integrator_core"
25 #define INTEGRATOR_CM(obj) \
26 OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
28 typedef struct IntegratorCMState
{
30 SysBusDevice parent_obj
;
44 uint32_t cm_refcnt_offset
;
50 static uint8_t integrator_spd
[128] = {
51 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
52 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
55 static const VMStateDescription vmstate_integratorcm
= {
56 .name
= "integratorcm",
58 .minimum_version_id
= 1,
59 .fields
= (VMStateField
[]) {
60 VMSTATE_UINT32(cm_osc
, IntegratorCMState
),
61 VMSTATE_UINT32(cm_ctrl
, IntegratorCMState
),
62 VMSTATE_UINT32(cm_lock
, IntegratorCMState
),
63 VMSTATE_UINT32(cm_auxosc
, IntegratorCMState
),
64 VMSTATE_UINT32(cm_sdram
, IntegratorCMState
),
65 VMSTATE_UINT32(cm_init
, IntegratorCMState
),
66 VMSTATE_UINT32(cm_flags
, IntegratorCMState
),
67 VMSTATE_UINT32(cm_nvflags
, IntegratorCMState
),
68 VMSTATE_UINT32(int_level
, IntegratorCMState
),
69 VMSTATE_UINT32(irq_enabled
, IntegratorCMState
),
70 VMSTATE_UINT32(fiq_enabled
, IntegratorCMState
),
75 static uint64_t integratorcm_read(void *opaque
, hwaddr offset
,
78 IntegratorCMState
*s
= opaque
;
79 if (offset
>= 0x100 && offset
< 0x200) {
83 return integrator_spd
[offset
>> 2];
85 switch (offset
>> 2) {
97 if (s
->cm_lock
== 0xa05f) {
102 case 6: /* CM_LMBUSCNT */
103 /* ??? High frequency timer. */
104 hw_error("integratorcm_read: CM_LMBUSCNT");
105 case 7: /* CM_AUXOSC */
107 case 8: /* CM_SDRAM */
109 case 9: /* CM_INIT */
111 case 10: /* CM_REFCNT */
112 /* This register, CM_REFCNT, provides a 32-bit count value.
113 * The count increments at the fixed reference clock frequency of 24MHz
114 * and can be used as a real-time counter.
116 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), 24,
117 1000) - s
->cm_refcnt_offset
;
118 case 12: /* CM_FLAGS */
120 case 14: /* CM_NVFLAGS */
121 return s
->cm_nvflags
;
122 case 16: /* CM_IRQ_STAT */
123 return s
->int_level
& s
->irq_enabled
;
124 case 17: /* CM_IRQ_RSTAT */
126 case 18: /* CM_IRQ_ENSET */
127 return s
->irq_enabled
;
128 case 20: /* CM_SOFT_INTSET */
129 return s
->int_level
& 1;
130 case 24: /* CM_FIQ_STAT */
131 return s
->int_level
& s
->fiq_enabled
;
132 case 25: /* CM_FIQ_RSTAT */
134 case 26: /* CM_FIQ_ENSET */
135 return s
->fiq_enabled
;
136 case 32: /* CM_VOLTAGE_CTL0 */
137 case 33: /* CM_VOLTAGE_CTL1 */
138 case 34: /* CM_VOLTAGE_CTL2 */
139 case 35: /* CM_VOLTAGE_CTL3 */
140 /* ??? Voltage control unimplemented. */
143 hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
149 static void integratorcm_do_remap(IntegratorCMState
*s
)
151 /* Sync memory region state with CM_CTRL REMAP bit:
152 * bit 0 => flash at address 0; bit 1 => RAM
154 memory_region_set_enabled(&s
->flash
, !(s
->cm_ctrl
& 4));
157 static void integratorcm_set_ctrl(IntegratorCMState
*s
, uint32_t value
)
160 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
162 if ((s
->cm_ctrl
^ value
) & 1) {
163 /* (value & 1) != 0 means the green "MISC LED" is lit.
164 * We don't have any nice place to display LEDs. printf is a bad
165 * idea because Linux uses the LED as a heartbeat and the output
166 * will swamp anything else on the terminal.
169 /* Note that the RESET bit [3] always reads as zero */
170 s
->cm_ctrl
= (s
->cm_ctrl
& ~5) | (value
& 5);
171 integratorcm_do_remap(s
);
174 static void integratorcm_update(IntegratorCMState
*s
)
176 /* ??? The CPU irq/fiq is raised when either the core module or base PIC
178 if (s
->int_level
& (s
->irq_enabled
| s
->fiq_enabled
))
179 hw_error("Core module interrupt\n");
182 static void integratorcm_write(void *opaque
, hwaddr offset
,
183 uint64_t value
, unsigned size
)
185 IntegratorCMState
*s
= opaque
;
186 switch (offset
>> 2) {
188 if (s
->cm_lock
== 0xa05f)
191 case 3: /* CM_CTRL */
192 integratorcm_set_ctrl(s
, value
);
194 case 5: /* CM_LOCK */
195 s
->cm_lock
= value
& 0xffff;
197 case 7: /* CM_AUXOSC */
198 if (s
->cm_lock
== 0xa05f)
199 s
->cm_auxosc
= value
;
201 case 8: /* CM_SDRAM */
204 case 9: /* CM_INIT */
205 /* ??? This can change the memory bus frequency. */
208 case 12: /* CM_FLAGSS */
209 s
->cm_flags
|= value
;
211 case 13: /* CM_FLAGSC */
212 s
->cm_flags
&= ~value
;
214 case 14: /* CM_NVFLAGSS */
215 s
->cm_nvflags
|= value
;
217 case 15: /* CM_NVFLAGSS */
218 s
->cm_nvflags
&= ~value
;
220 case 18: /* CM_IRQ_ENSET */
221 s
->irq_enabled
|= value
;
222 integratorcm_update(s
);
224 case 19: /* CM_IRQ_ENCLR */
225 s
->irq_enabled
&= ~value
;
226 integratorcm_update(s
);
228 case 20: /* CM_SOFT_INTSET */
229 s
->int_level
|= (value
& 1);
230 integratorcm_update(s
);
232 case 21: /* CM_SOFT_INTCLR */
233 s
->int_level
&= ~(value
& 1);
234 integratorcm_update(s
);
236 case 26: /* CM_FIQ_ENSET */
237 s
->fiq_enabled
|= value
;
238 integratorcm_update(s
);
240 case 27: /* CM_FIQ_ENCLR */
241 s
->fiq_enabled
&= ~value
;
242 integratorcm_update(s
);
244 case 32: /* CM_VOLTAGE_CTL0 */
245 case 33: /* CM_VOLTAGE_CTL1 */
246 case 34: /* CM_VOLTAGE_CTL2 */
247 case 35: /* CM_VOLTAGE_CTL3 */
248 /* ??? Voltage control unimplemented. */
251 hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
257 /* Integrator/CM control registers. */
259 static const MemoryRegionOps integratorcm_ops
= {
260 .read
= integratorcm_read
,
261 .write
= integratorcm_write
,
262 .endianness
= DEVICE_NATIVE_ENDIAN
,
265 static void integratorcm_init(Object
*obj
)
267 IntegratorCMState
*s
= INTEGRATOR_CM(obj
);
269 s
->cm_osc
= 0x01000048;
270 /* ??? What should the high bits of this value be? */
271 s
->cm_auxosc
= 0x0007feff;
272 s
->cm_sdram
= 0x00011122;
273 memcpy(integrator_spd
+ 73, "QEMU-MEMORY", 11);
274 s
->cm_init
= 0x00000112;
275 s
->cm_refcnt_offset
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), 24,
278 /* ??? Save/restore. */
281 static void integratorcm_realize(DeviceState
*d
, Error
**errp
)
283 IntegratorCMState
*s
= INTEGRATOR_CM(d
);
284 SysBusDevice
*dev
= SYS_BUS_DEVICE(d
);
285 Error
*local_err
= NULL
;
287 memory_region_init_ram(&s
->flash
, OBJECT(d
), "integrator.flash", 0x100000,
290 error_propagate(errp
, local_err
);
294 memory_region_init_io(&s
->iomem
, OBJECT(d
), &integratorcm_ops
, s
,
295 "integratorcm", 0x00800000);
296 sysbus_init_mmio(dev
, &s
->iomem
);
298 integratorcm_do_remap(s
);
300 if (s
->memsz
>= 256) {
301 integrator_spd
[31] = 64;
303 } else if (s
->memsz
>= 128) {
304 integrator_spd
[31] = 32;
306 } else if (s
->memsz
>= 64) {
307 integrator_spd
[31] = 16;
309 } else if (s
->memsz
>= 32) {
310 integrator_spd
[31] = 4;
313 integrator_spd
[31] = 2;
317 /* Integrator/CP hardware emulation. */
318 /* Primary interrupt controller. */
320 #define TYPE_INTEGRATOR_PIC "integrator_pic"
321 #define INTEGRATOR_PIC(obj) \
322 OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
324 typedef struct icp_pic_state
{
326 SysBusDevice parent_obj
;
331 uint32_t irq_enabled
;
332 uint32_t fiq_enabled
;
337 static const VMStateDescription vmstate_icp_pic
= {
340 .minimum_version_id
= 1,
341 .fields
= (VMStateField
[]) {
342 VMSTATE_UINT32(level
, icp_pic_state
),
343 VMSTATE_UINT32(irq_enabled
, icp_pic_state
),
344 VMSTATE_UINT32(fiq_enabled
, icp_pic_state
),
345 VMSTATE_END_OF_LIST()
349 static void icp_pic_update(icp_pic_state
*s
)
353 flags
= (s
->level
& s
->irq_enabled
);
354 qemu_set_irq(s
->parent_irq
, flags
!= 0);
355 flags
= (s
->level
& s
->fiq_enabled
);
356 qemu_set_irq(s
->parent_fiq
, flags
!= 0);
359 static void icp_pic_set_irq(void *opaque
, int irq
, int level
)
361 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
363 s
->level
|= 1 << irq
;
365 s
->level
&= ~(1 << irq
);
369 static uint64_t icp_pic_read(void *opaque
, hwaddr offset
,
372 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
374 switch (offset
>> 2) {
375 case 0: /* IRQ_STATUS */
376 return s
->level
& s
->irq_enabled
;
377 case 1: /* IRQ_RAWSTAT */
379 case 2: /* IRQ_ENABLESET */
380 return s
->irq_enabled
;
381 case 4: /* INT_SOFTSET */
383 case 8: /* FRQ_STATUS */
384 return s
->level
& s
->fiq_enabled
;
385 case 9: /* FRQ_RAWSTAT */
387 case 10: /* FRQ_ENABLESET */
388 return s
->fiq_enabled
;
389 case 3: /* IRQ_ENABLECLR */
390 case 5: /* INT_SOFTCLR */
391 case 11: /* FRQ_ENABLECLR */
393 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset
);
398 static void icp_pic_write(void *opaque
, hwaddr offset
,
399 uint64_t value
, unsigned size
)
401 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
403 switch (offset
>> 2) {
404 case 2: /* IRQ_ENABLESET */
405 s
->irq_enabled
|= value
;
407 case 3: /* IRQ_ENABLECLR */
408 s
->irq_enabled
&= ~value
;
410 case 4: /* INT_SOFTSET */
412 icp_pic_set_irq(s
, 0, 1);
414 case 5: /* INT_SOFTCLR */
416 icp_pic_set_irq(s
, 0, 0);
418 case 10: /* FRQ_ENABLESET */
419 s
->fiq_enabled
|= value
;
421 case 11: /* FRQ_ENABLECLR */
422 s
->fiq_enabled
&= ~value
;
424 case 0: /* IRQ_STATUS */
425 case 1: /* IRQ_RAWSTAT */
426 case 8: /* FRQ_STATUS */
427 case 9: /* FRQ_RAWSTAT */
429 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset
);
435 static const MemoryRegionOps icp_pic_ops
= {
436 .read
= icp_pic_read
,
437 .write
= icp_pic_write
,
438 .endianness
= DEVICE_NATIVE_ENDIAN
,
441 static void icp_pic_init(Object
*obj
)
443 DeviceState
*dev
= DEVICE(obj
);
444 icp_pic_state
*s
= INTEGRATOR_PIC(obj
);
445 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
447 qdev_init_gpio_in(dev
, icp_pic_set_irq
, 32);
448 sysbus_init_irq(sbd
, &s
->parent_irq
);
449 sysbus_init_irq(sbd
, &s
->parent_fiq
);
450 memory_region_init_io(&s
->iomem
, obj
, &icp_pic_ops
, s
,
451 "icp-pic", 0x00800000);
452 sysbus_init_mmio(sbd
, &s
->iomem
);
455 /* CP control registers. */
457 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
458 #define ICP_CONTROL_REGS(obj) \
459 OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS)
461 typedef struct ICPCtrlRegsState
{
463 SysBusDevice parent_obj
;
469 uint32_t intreg_state
;
472 #define ICP_GPIO_MMC_WPROT "mmc-wprot"
473 #define ICP_GPIO_MMC_CARDIN "mmc-cardin"
475 #define ICP_INTREG_WPROT (1 << 0)
476 #define ICP_INTREG_CARDIN (1 << 3)
478 static const VMStateDescription vmstate_icp_control
= {
479 .name
= "icp_control",
481 .minimum_version_id
= 1,
482 .fields
= (VMStateField
[]) {
483 VMSTATE_UINT32(intreg_state
, ICPCtrlRegsState
),
484 VMSTATE_END_OF_LIST()
488 static uint64_t icp_control_read(void *opaque
, hwaddr offset
,
491 ICPCtrlRegsState
*s
= opaque
;
493 switch (offset
>> 2) {
494 case 0: /* CP_IDFIELD */
496 case 1: /* CP_FLASHPROG */
498 case 2: /* CP_INTREG */
499 return s
->intreg_state
;
500 case 3: /* CP_DECODE */
503 hw_error("icp_control_read: Bad offset %x\n", (int)offset
);
508 static void icp_control_write(void *opaque
, hwaddr offset
,
509 uint64_t value
, unsigned size
)
511 ICPCtrlRegsState
*s
= opaque
;
513 switch (offset
>> 2) {
514 case 2: /* CP_INTREG */
515 s
->intreg_state
&= ~(value
& ICP_INTREG_CARDIN
);
516 qemu_set_irq(s
->mmc_irq
, !!(s
->intreg_state
& ICP_INTREG_CARDIN
));
518 case 1: /* CP_FLASHPROG */
519 case 3: /* CP_DECODE */
520 /* Nothing interesting implemented yet. */
523 hw_error("icp_control_write: Bad offset %x\n", (int)offset
);
527 static const MemoryRegionOps icp_control_ops
= {
528 .read
= icp_control_read
,
529 .write
= icp_control_write
,
530 .endianness
= DEVICE_NATIVE_ENDIAN
,
533 static void icp_control_mmc_wprot(void *opaque
, int line
, int level
)
535 ICPCtrlRegsState
*s
= opaque
;
537 s
->intreg_state
&= ~ICP_INTREG_WPROT
;
539 s
->intreg_state
|= ICP_INTREG_WPROT
;
543 static void icp_control_mmc_cardin(void *opaque
, int line
, int level
)
545 ICPCtrlRegsState
*s
= opaque
;
547 /* line is released by writing to CP_INTREG */
549 s
->intreg_state
|= ICP_INTREG_CARDIN
;
550 qemu_set_irq(s
->mmc_irq
, 1);
554 static void icp_control_init(Object
*obj
)
556 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
557 ICPCtrlRegsState
*s
= ICP_CONTROL_REGS(obj
);
558 DeviceState
*dev
= DEVICE(obj
);
560 memory_region_init_io(&s
->iomem
, OBJECT(s
), &icp_control_ops
, s
,
561 "icp_ctrl_regs", 0x00800000);
562 sysbus_init_mmio(sbd
, &s
->iomem
);
564 qdev_init_gpio_in_named(dev
, icp_control_mmc_wprot
, ICP_GPIO_MMC_WPROT
, 1);
565 qdev_init_gpio_in_named(dev
, icp_control_mmc_cardin
,
566 ICP_GPIO_MMC_CARDIN
, 1);
567 sysbus_init_irq(sbd
, &s
->mmc_irq
);
573 static struct arm_boot_info integrator_binfo
= {
578 static void integratorcp_init(MachineState
*machine
)
580 ram_addr_t ram_size
= machine
->ram_size
;
581 const char *kernel_filename
= machine
->kernel_filename
;
582 const char *kernel_cmdline
= machine
->kernel_cmdline
;
583 const char *initrd_filename
= machine
->initrd_filename
;
586 MemoryRegion
*address_space_mem
= get_system_memory();
587 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
588 MemoryRegion
*ram_alias
= g_new(MemoryRegion
, 1);
590 DeviceState
*dev
, *sic
, *icp
;
593 cpuobj
= object_new(machine
->cpu_type
);
595 /* By default ARM1176 CPUs have EL3 enabled. This board does not
596 * currently support EL3 so the CPU EL3 property is disabled before
599 if (object_property_find(cpuobj
, "has_el3", NULL
)) {
600 object_property_set_bool(cpuobj
, false, "has_el3", &error_fatal
);
603 object_property_set_bool(cpuobj
, true, "realized", &error_fatal
);
605 cpu
= ARM_CPU(cpuobj
);
607 memory_region_allocate_system_memory(ram
, NULL
, "integrator.ram",
609 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
610 /* ??? RAM should repeat to fill physical memory space. */
611 /* SDRAM at address zero*/
612 memory_region_add_subregion(address_space_mem
, 0, ram
);
613 /* And again at address 0x80000000 */
614 memory_region_init_alias(ram_alias
, NULL
, "ram.alias", ram
, 0, ram_size
);
615 memory_region_add_subregion(address_space_mem
, 0x80000000, ram_alias
);
617 dev
= qdev_create(NULL
, TYPE_INTEGRATOR_CM
);
618 qdev_prop_set_uint32(dev
, "memsz", ram_size
>> 20);
619 qdev_init_nofail(dev
);
620 sysbus_mmio_map((SysBusDevice
*)dev
, 0, 0x10000000);
622 dev
= sysbus_create_varargs(TYPE_INTEGRATOR_PIC
, 0x14000000,
623 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_IRQ
),
624 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_FIQ
),
626 for (i
= 0; i
< 32; i
++) {
627 pic
[i
] = qdev_get_gpio_in(dev
, i
);
629 sic
= sysbus_create_simple(TYPE_INTEGRATOR_PIC
, 0xca000000, pic
[26]);
630 sysbus_create_varargs("integrator_pit", 0x13000000,
631 pic
[5], pic
[6], pic
[7], NULL
);
632 sysbus_create_simple("pl031", 0x15000000, pic
[8]);
633 pl011_create(0x16000000, pic
[1], serial_hd(0));
634 pl011_create(0x17000000, pic
[2], serial_hd(1));
635 icp
= sysbus_create_simple(TYPE_ICP_CONTROL_REGS
, 0xcb000000,
636 qdev_get_gpio_in(sic
, 3));
637 sysbus_create_simple("pl050_keyboard", 0x18000000, pic
[3]);
638 sysbus_create_simple("pl050_mouse", 0x19000000, pic
[4]);
639 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG
, 0x1a000000, 0);
641 dev
= sysbus_create_varargs("pl181", 0x1c000000, pic
[23], pic
[24], NULL
);
642 qdev_connect_gpio_out(dev
, 0,
643 qdev_get_gpio_in_named(icp
, ICP_GPIO_MMC_WPROT
, 0));
644 qdev_connect_gpio_out(dev
, 1,
645 qdev_get_gpio_in_named(icp
, ICP_GPIO_MMC_CARDIN
, 0));
647 if (nd_table
[0].used
)
648 smc91c111_init(&nd_table
[0], 0xc8000000, pic
[27]);
650 sysbus_create_simple("pl110", 0xc0000000, pic
[22]);
652 integrator_binfo
.ram_size
= ram_size
;
653 integrator_binfo
.kernel_filename
= kernel_filename
;
654 integrator_binfo
.kernel_cmdline
= kernel_cmdline
;
655 integrator_binfo
.initrd_filename
= initrd_filename
;
656 arm_load_kernel(cpu
, &integrator_binfo
);
659 static void integratorcp_machine_init(MachineClass
*mc
)
661 mc
->desc
= "ARM Integrator/CP (ARM926EJ-S)";
662 mc
->init
= integratorcp_init
;
663 mc
->ignore_memory_transaction_failures
= true;
664 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("arm926");
667 DEFINE_MACHINE("integratorcp", integratorcp_machine_init
)
669 static Property core_properties
[] = {
670 DEFINE_PROP_UINT32("memsz", IntegratorCMState
, memsz
, 0),
671 DEFINE_PROP_END_OF_LIST(),
674 static void core_class_init(ObjectClass
*klass
, void *data
)
676 DeviceClass
*dc
= DEVICE_CLASS(klass
);
678 dc
->props
= core_properties
;
679 dc
->realize
= integratorcm_realize
;
680 dc
->vmsd
= &vmstate_integratorcm
;
683 static void icp_pic_class_init(ObjectClass
*klass
, void *data
)
685 DeviceClass
*dc
= DEVICE_CLASS(klass
);
687 dc
->vmsd
= &vmstate_icp_pic
;
690 static void icp_control_class_init(ObjectClass
*klass
, void *data
)
692 DeviceClass
*dc
= DEVICE_CLASS(klass
);
694 dc
->vmsd
= &vmstate_icp_control
;
697 static const TypeInfo core_info
= {
698 .name
= TYPE_INTEGRATOR_CM
,
699 .parent
= TYPE_SYS_BUS_DEVICE
,
700 .instance_size
= sizeof(IntegratorCMState
),
701 .instance_init
= integratorcm_init
,
702 .class_init
= core_class_init
,
705 static const TypeInfo icp_pic_info
= {
706 .name
= TYPE_INTEGRATOR_PIC
,
707 .parent
= TYPE_SYS_BUS_DEVICE
,
708 .instance_size
= sizeof(icp_pic_state
),
709 .instance_init
= icp_pic_init
,
710 .class_init
= icp_pic_class_init
,
713 static const TypeInfo icp_ctrl_regs_info
= {
714 .name
= TYPE_ICP_CONTROL_REGS
,
715 .parent
= TYPE_SYS_BUS_DEVICE
,
716 .instance_size
= sizeof(ICPCtrlRegsState
),
717 .instance_init
= icp_control_init
,
718 .class_init
= icp_control_class_init
,
721 static void integratorcp_register_types(void)
723 type_register_static(&icp_pic_info
);
724 type_register_static(&core_info
);
725 type_register_static(&icp_ctrl_regs_info
);
728 type_init(integratorcp_register_types
)