x86/cpu: Populate SVM CPUID feature bits
[qemu/ar7.git] / tcg / arm / tcg-target-con-str.h
bloba0ab7747dbc60e04f3e81286016d32f6f4604a1e
1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Define Arm target-specific operand constraints.
4 * Copyright (c) 2021 Linaro
5 */
7 /*
8 * Define constraint letters for register sets:
9 * REGS(letter, register_mask)
11 REGS('r', ALL_GENERAL_REGS)
12 REGS('l', ALL_QLOAD_REGS)
13 REGS('s', ALL_QSTORE_REGS)
16 * Define constraint letters for constants:
17 * CONST(letter, TCG_CT_CONST_* bit set)
19 CONST('I', TCG_CT_CONST_ARM)
20 CONST('K', TCG_CT_CONST_INV)
21 CONST('N', TCG_CT_CONST_NEG)
22 CONST('Z', TCG_CT_CONST_ZERO)