| commit | 5447089c2b3b084b51670af36fc86ee3979e04be | |
| author | Wei Huang <wei.huang2@amd.com> | |
| Tue, 26 Jan 2021 20:24:56 +0000 (26 14:24 -0600) | ||
| committer | Paolo Bonzini <pbonzini@redhat.com> | |
| Mon, 8 Feb 2021 13:43:54 +0000 (8 14:43 +0100) | ||
| tree | 1efbe8b7df78168638b603ca66ea6909b06737fd | treesnapshot (tar.gz zip) |
| parent | c518d6c2bffdef9d98177dba7f25d5cb4193822e | commitdiff |
x86/cpu: Populate SVM CPUID feature bits
Newer AMD CPUs will add CPUID_0x8000000A_EDX[28] bit, which indicates
that SVM instructions (VMRUN/VMSAVE/VMLOAD) will trigger #VMEXIT before
CPU checking their EAX against reserved memory regions. This change will
allow the hypervisor to avoid intercepting #GP and emulating SVM
instructions. KVM turns on this CPUID bit for nested VMs. In order to
support it, let us populate this bit, along with other SVM feature bits,
in FEAT_SVM.
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Message-Id: <20210126202456.589932-1-wei.huang2@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Newer AMD CPUs will add CPUID_0x8000000A_EDX[28] bit, which indicates
that SVM instructions (VMRUN/VMSAVE/VMLOAD) will trigger #VMEXIT before
CPU checking their EAX against reserved memory regions. This change will
allow the hypervisor to avoid intercepting #GP and emulating SVM
instructions. KVM turns on this CPUID bit for nested VMs. In order to
support it, let us populate this bit, along with other SVM feature bits,
in FEAT_SVM.
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Message-Id: <20210126202456.589932-1-wei.huang2@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| target/i386/cpu.c | diffblobblamehistory | |
| target/i386/cpu.h | diffblobblamehistory |