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hw/riscv: sifive_u: Add reset functionality
[qemu/ar7.git] / hw / misc / aspeed_scu.c
blobec4fef900e27c63bdd6665ec346a822da24a01e2
1 /*
2 * ASPEED System Control Unit
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "hw/misc/aspeed_scu.h"
14 #include "hw/qdev-properties.h"
15 #include "migration/vmstate.h"
16 #include "qapi/error.h"
17 #include "qapi/visitor.h"
18 #include "qemu/bitops.h"
19 #include "qemu/log.h"
20 #include "qemu/guest-random.h"
21 #include "qemu/module.h"
22 #include "trace.h"
23
24 #define TO_REG(offset) ((offset) >> 2)
25
26 #define PROT_KEY TO_REG(0x00)
27 #define SYS_RST_CTRL TO_REG(0x04)
28 #define CLK_SEL TO_REG(0x08)
29 #define CLK_STOP_CTRL TO_REG(0x0C)
30 #define FREQ_CNTR_CTRL TO_REG(0x10)
31 #define FREQ_CNTR_EVAL TO_REG(0x14)
32 #define IRQ_CTRL TO_REG(0x18)
33 #define D2PLL_PARAM TO_REG(0x1C)
34 #define MPLL_PARAM TO_REG(0x20)
35 #define HPLL_PARAM TO_REG(0x24)
36 #define FREQ_CNTR_RANGE TO_REG(0x28)
37 #define MISC_CTRL1 TO_REG(0x2C)
38 #define PCI_CTRL1 TO_REG(0x30)
39 #define PCI_CTRL2 TO_REG(0x34)
40 #define PCI_CTRL3 TO_REG(0x38)
41 #define SYS_RST_STATUS TO_REG(0x3C)
42 #define SOC_SCRATCH1 TO_REG(0x40)
43 #define SOC_SCRATCH2 TO_REG(0x44)
44 #define MAC_CLK_DELAY TO_REG(0x48)
45 #define MISC_CTRL2 TO_REG(0x4C)
46 #define VGA_SCRATCH1 TO_REG(0x50)
47 #define VGA_SCRATCH2 TO_REG(0x54)
48 #define VGA_SCRATCH3 TO_REG(0x58)
49 #define VGA_SCRATCH4 TO_REG(0x5C)
50 #define VGA_SCRATCH5 TO_REG(0x60)
51 #define VGA_SCRATCH6 TO_REG(0x64)
52 #define VGA_SCRATCH7 TO_REG(0x68)
53 #define VGA_SCRATCH8 TO_REG(0x6C)
54 #define HW_STRAP1 TO_REG(0x70)
55 #define RNG_CTRL TO_REG(0x74)
56 #define RNG_DATA TO_REG(0x78)
57 #define SILICON_REV TO_REG(0x7C)
58 #define PINMUX_CTRL1 TO_REG(0x80)
59 #define PINMUX_CTRL2 TO_REG(0x84)
60 #define PINMUX_CTRL3 TO_REG(0x88)
61 #define PINMUX_CTRL4 TO_REG(0x8C)
62 #define PINMUX_CTRL5 TO_REG(0x90)
63 #define PINMUX_CTRL6 TO_REG(0x94)
64 #define WDT_RST_CTRL TO_REG(0x9C)
65 #define PINMUX_CTRL7 TO_REG(0xA0)
66 #define PINMUX_CTRL8 TO_REG(0xA4)
67 #define PINMUX_CTRL9 TO_REG(0xA8)
68 #define WAKEUP_EN TO_REG(0xC0)
69 #define WAKEUP_CTRL TO_REG(0xC4)
70 #define HW_STRAP2 TO_REG(0xD0)
71 #define FREE_CNTR4 TO_REG(0xE0)
72 #define FREE_CNTR4_EXT TO_REG(0xE4)
73 #define CPU2_CTRL TO_REG(0x100)
74 #define CPU2_BASE_SEG1 TO_REG(0x104)
75 #define CPU2_BASE_SEG2 TO_REG(0x108)
76 #define CPU2_BASE_SEG3 TO_REG(0x10C)
77 #define CPU2_BASE_SEG4 TO_REG(0x110)
78 #define CPU2_BASE_SEG5 TO_REG(0x114)
79 #define CPU2_CACHE_CTRL TO_REG(0x118)
80 #define CHIP_ID0 TO_REG(0x150)
81 #define CHIP_ID1 TO_REG(0x154)
82 #define UART_HPLL_CLK TO_REG(0x160)
83 #define PCIE_CTRL TO_REG(0x180)
84 #define BMC_MMIO_CTRL TO_REG(0x184)
85 #define RELOC_DECODE_BASE1 TO_REG(0x188)
86 #define RELOC_DECODE_BASE2 TO_REG(0x18C)
87 #define MAILBOX_DECODE_BASE TO_REG(0x190)
88 #define SRAM_DECODE_BASE1 TO_REG(0x194)
89 #define SRAM_DECODE_BASE2 TO_REG(0x198)
90 #define BMC_REV TO_REG(0x19C)
91 #define BMC_DEV_ID TO_REG(0x1A4)
92
93 #define AST2600_PROT_KEY TO_REG(0x00)
94 #define AST2600_SILICON_REV TO_REG(0x04)
95 #define AST2600_SILICON_REV2 TO_REG(0x14)
96 #define AST2600_SYS_RST_CTRL TO_REG(0x40)
97 #define AST2600_SYS_RST_CTRL_CLR TO_REG(0x44)
98 #define AST2600_SYS_RST_CTRL2 TO_REG(0x50)
99 #define AST2600_SYS_RST_CTRL2_CLR TO_REG(0x54)
100 #define AST2600_CLK_STOP_CTRL TO_REG(0x80)
101 #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84)
102 #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90)
103 #define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94)
104 #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100)
105 #define AST2600_HPLL_PARAM TO_REG(0x200)
106 #define AST2600_HPLL_EXT TO_REG(0x204)
107 #define AST2600_MPLL_EXT TO_REG(0x224)
108 #define AST2600_EPLL_EXT TO_REG(0x244)
109 #define AST2600_CLK_SEL TO_REG(0x300)
110 #define AST2600_CLK_SEL2 TO_REG(0x304)
111 #define AST2600_CLK_SEL3 TO_REG(0x310)
112 #define AST2600_HW_STRAP1 TO_REG(0x500)
113 #define AST2600_HW_STRAP1_CLR TO_REG(0x504)
114 #define AST2600_HW_STRAP1_PROT TO_REG(0x508)
115 #define AST2600_HW_STRAP2 TO_REG(0x510)
116 #define AST2600_HW_STRAP2_CLR TO_REG(0x514)
117 #define AST2600_HW_STRAP2_PROT TO_REG(0x518)
118 #define AST2600_RNG_CTRL TO_REG(0x524)
119 #define AST2600_RNG_DATA TO_REG(0x540)
120 #define AST2600_CHIP_ID0 TO_REG(0x5B0)
121 #define AST2600_CHIP_ID1 TO_REG(0x5B4)
122
123 #define AST2600_CLK TO_REG(0x40)
124
125 #define SCU_IO_REGION_SIZE 0x1000
126
127 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
128 [SYS_RST_CTRL] = 0xFFCFFEDCU,
129 [CLK_SEL] = 0xF3F40000U,
130 [CLK_STOP_CTRL] = 0x19FC3E8BU,
131 [D2PLL_PARAM] = 0x00026108U,
132 [MPLL_PARAM] = 0x00030291U,
133 [HPLL_PARAM] = 0x00000291U,
134 [MISC_CTRL1] = 0x00000010U,
135 [PCI_CTRL1] = 0x20001A03U,
136 [PCI_CTRL2] = 0x20001A03U,
137 [PCI_CTRL3] = 0x04000030U,
138 [SYS_RST_STATUS] = 0x00000001U,
139 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
140 [MISC_CTRL2] = 0x00000023U,
141 [RNG_CTRL] = 0x0000000EU,
142 [PINMUX_CTRL2] = 0x0000F000U,
143 [PINMUX_CTRL3] = 0x01000000U,
144 [PINMUX_CTRL4] = 0x000000FFU,
145 [PINMUX_CTRL5] = 0x0000A000U,
146 [WDT_RST_CTRL] = 0x003FFFF3U,
147 [PINMUX_CTRL8] = 0xFFFF0000U,
148 [PINMUX_CTRL9] = 0x000FFFFFU,
149 [FREE_CNTR4] = 0x000000FFU,
150 [FREE_CNTR4_EXT] = 0x000000FFU,
151 [CPU2_BASE_SEG1] = 0x80000000U,
152 [CPU2_BASE_SEG4] = 0x1E600000U,
153 [CPU2_BASE_SEG5] = 0xC0000000U,
154 [UART_HPLL_CLK] = 0x00001903U,
155 [PCIE_CTRL] = 0x0000007BU,
156 [BMC_DEV_ID] = 0x00002402U
157 };
158
159 /* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
160 /* AST2500 revision A1 */
161
162 static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
163 [SYS_RST_CTRL] = 0xFFCFFEDCU,
164 [CLK_SEL] = 0xF3F40000U,
165 [CLK_STOP_CTRL] = 0x19FC3E8BU,
166 [D2PLL_PARAM] = 0x00026108U,
167 [MPLL_PARAM] = 0x00030291U,
168 [HPLL_PARAM] = 0x93000400U,
169 [MISC_CTRL1] = 0x00000010U,
170 [PCI_CTRL1] = 0x20001A03U,
171 [PCI_CTRL2] = 0x20001A03U,
172 [PCI_CTRL3] = 0x04000030U,
173 [SYS_RST_STATUS] = 0x00000001U,
174 [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
175 [MISC_CTRL2] = 0x00000023U,
176 [RNG_CTRL] = 0x0000000EU,
177 [PINMUX_CTRL2] = 0x0000F000U,
178 [PINMUX_CTRL3] = 0x03000000U,
179 [PINMUX_CTRL4] = 0x00000000U,
180 [PINMUX_CTRL5] = 0x0000A000U,
181 [WDT_RST_CTRL] = 0x023FFFF3U,
182 [PINMUX_CTRL8] = 0xFFFF0000U,
183 [PINMUX_CTRL9] = 0x000FFFFFU,
184 [FREE_CNTR4] = 0x000000FFU,
185 [FREE_CNTR4_EXT] = 0x000000FFU,
186 [CPU2_BASE_SEG1] = 0x80000000U,
187 [CPU2_BASE_SEG4] = 0x1E600000U,
188 [CPU2_BASE_SEG5] = 0xC0000000U,
189 [CHIP_ID0] = 0x1234ABCDU,
190 [CHIP_ID1] = 0x88884444U,
191 [UART_HPLL_CLK] = 0x00001903U,
192 [PCIE_CTRL] = 0x0000007BU,
193 [BMC_DEV_ID] = 0x00002402U
194 };
195
196 static uint32_t aspeed_scu_get_random(void)
197 {
198 uint32_t num;
199 qemu_guest_getrandom_nofail(&num, sizeof(num));
200 return num;
201 }
202
203 uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s)
204 {
205 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
206 uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]);
207
208 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1)
209 / asc->apb_divider;
210 }
211
212 static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
213 {
214 AspeedSCUState *s = ASPEED_SCU(opaque);
215 int reg = TO_REG(offset);
216
217 if (reg >= ASPEED_SCU_NR_REGS) {
218 qemu_log_mask(LOG_GUEST_ERROR,
219 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
220 __func__, offset);
221 return 0;
222 }
223
224 switch (reg) {
225 case RNG_DATA:
226 /* On hardware, RNG_DATA works regardless of
227 * the state of the enable bit in RNG_CTRL
228 */
229 s->regs[RNG_DATA] = aspeed_scu_get_random();
230 break;
231 case WAKEUP_EN:
232 qemu_log_mask(LOG_GUEST_ERROR,
233 "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
234 __func__, offset);
235 break;
236 }
237
238 return s->regs[reg];
239 }
240
241 static void aspeed_ast2400_scu_write(void *opaque, hwaddr offset,
242 uint64_t data, unsigned size)
243 {
244 AspeedSCUState *s = ASPEED_SCU(opaque);
245 int reg = TO_REG(offset);
246
247 if (reg >= ASPEED_SCU_NR_REGS) {
248 qemu_log_mask(LOG_GUEST_ERROR,
249 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
250 __func__, offset);
251 return;
252 }
253
254 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
255 !s->regs[PROT_KEY]) {
256 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
257 }
258
259 trace_aspeed_scu_write(offset, size, data);
260
261 switch (reg) {
262 case PROT_KEY:
263 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
264 return;
265 case SILICON_REV:
266 case FREQ_CNTR_EVAL:
267 case VGA_SCRATCH1 ... VGA_SCRATCH8:
268 case RNG_DATA:
269 case FREE_CNTR4:
270 case FREE_CNTR4_EXT:
271 qemu_log_mask(LOG_GUEST_ERROR,
272 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
273 __func__, offset);
274 return;
275 }
276
277 s->regs[reg] = data;
278 }
279
280 static void aspeed_ast2500_scu_write(void *opaque, hwaddr offset,
281 uint64_t data, unsigned size)
282 {
283 AspeedSCUState *s = ASPEED_SCU(opaque);
284 int reg = TO_REG(offset);
285
286 if (reg >= ASPEED_SCU_NR_REGS) {
287 qemu_log_mask(LOG_GUEST_ERROR,
288 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
289 __func__, offset);
290 return;
291 }
292
293 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
294 !s->regs[PROT_KEY]) {
295 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
296 return;
297 }
298
299 trace_aspeed_scu_write(offset, size, data);
300
301 switch (reg) {
302 case PROT_KEY:
303 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
304 return;
305 case HW_STRAP1:
306 s->regs[HW_STRAP1] |= data;
307 return;
308 case SILICON_REV:
309 s->regs[HW_STRAP1] &= ~data;
310 return;
311 case FREQ_CNTR_EVAL:
312 case VGA_SCRATCH1 ... VGA_SCRATCH8:
313 case RNG_DATA:
314 case FREE_CNTR4:
315 case FREE_CNTR4_EXT:
316 case CHIP_ID0:
317 case CHIP_ID1:
318 qemu_log_mask(LOG_GUEST_ERROR,
319 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
320 __func__, offset);
321 return;
322 }
323
324 s->regs[reg] = data;
325 }
326
327 static const MemoryRegionOps aspeed_ast2400_scu_ops = {
328 .read = aspeed_scu_read,
329 .write = aspeed_ast2400_scu_write,
330 .endianness = DEVICE_LITTLE_ENDIAN,
331 .valid.min_access_size = 4,
332 .valid.max_access_size = 4,
333 .valid.unaligned = false,
334 };
335
336 static const MemoryRegionOps aspeed_ast2500_scu_ops = {
337 .read = aspeed_scu_read,
338 .write = aspeed_ast2500_scu_write,
339 .endianness = DEVICE_LITTLE_ENDIAN,
340 .valid.min_access_size = 4,
341 .valid.max_access_size = 4,
342 .valid.unaligned = false,
343 };
344
345 static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s)
346 {
347 if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) {
348 return 25000000;
349 } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) {
350 return 48000000;
351 } else {
352 return 24000000;
353 }
354 }
355
356 /*
357 * Strapped frequencies for the AST2400 in MHz. They depend on the
358 * clkin frequency.
359 */
360 static const uint32_t hpll_ast2400_freqs[][4] = {
361 { 384, 360, 336, 408 }, /* 24MHz or 48MHz */
362 { 400, 375, 350, 425 }, /* 25MHz */
363 };
364
365 static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
366 {
367 uint8_t freq_select;
368 bool clk_25m_in;
369 uint32_t clkin = aspeed_scu_get_clkin(s);
370
371 if (hpll_reg & SCU_AST2400_H_PLL_OFF) {
372 return 0;
373 }
374
375 if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) {
376 uint32_t multiplier = 1;
377
378 if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) {
379 uint32_t n = (hpll_reg >> 5) & 0x3f;
380 uint32_t od = (hpll_reg >> 4) & 0x1;
381 uint32_t d = hpll_reg & 0xf;
382
383 multiplier = (2 - od) * ((n + 2) / (d + 1));
384 }
385
386 return clkin * multiplier;
387 }
388
389 /* HW strapping */
390 clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN);
391 freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1);
392
393 return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000;
394 }
395
396 static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
397 {
398 uint32_t multiplier = 1;
399 uint32_t clkin = aspeed_scu_get_clkin(s);
400
401 if (hpll_reg & SCU_H_PLL_OFF) {
402 return 0;
403 }
404
405 if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) {
406 uint32_t p = (hpll_reg >> 13) & 0x3f;
407 uint32_t m = (hpll_reg >> 5) & 0xff;
408 uint32_t n = hpll_reg & 0x1f;
409
410 multiplier = ((m + 1) / (n + 1)) / (p + 1);
411 }
412
413 return clkin * multiplier;
414 }
415
416 static void aspeed_scu_reset(DeviceState *dev)
417 {
418 AspeedSCUState *s = ASPEED_SCU(dev);
419 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
420
421 memcpy(s->regs, asc->resets, asc->nr_regs * 4);
422 s->regs[SILICON_REV] = s->silicon_rev;
423 s->regs[HW_STRAP1] = s->hw_strap1;
424 s->regs[HW_STRAP2] = s->hw_strap2;
425 s->regs[PROT_KEY] = s->hw_prot_key;
426 }
427
428 static uint32_t aspeed_silicon_revs[] = {
429 AST2400_A0_SILICON_REV,
430 AST2400_A1_SILICON_REV,
431 AST2500_A0_SILICON_REV,
432 AST2500_A1_SILICON_REV,
433 AST2600_A0_SILICON_REV,
434 AST2600_A1_SILICON_REV,
435 };
436
437 bool is_supported_silicon_rev(uint32_t silicon_rev)
438 {
439 int i;
440
441 for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) {
442 if (silicon_rev == aspeed_silicon_revs[i]) {
443 return true;
444 }
445 }
446
447 return false;
448 }
449
450 static void aspeed_scu_realize(DeviceState *dev, Error **errp)
451 {
452 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
453 AspeedSCUState *s = ASPEED_SCU(dev);
454 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
455
456 if (!is_supported_silicon_rev(s->silicon_rev)) {
457 error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
458 s->silicon_rev);
459 return;
460 }
461
462 memory_region_init_io(&s->iomem, OBJECT(s), asc->ops, s,
463 TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);
464
465 sysbus_init_mmio(sbd, &s->iomem);
466 }
467
468 static const VMStateDescription vmstate_aspeed_scu = {
469 .name = "aspeed.scu",
470 .version_id = 2,
471 .minimum_version_id = 2,
472 .fields = (VMStateField[]) {
473 VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_REGS),
474 VMSTATE_END_OF_LIST()
475 }
476 };
477
478 static Property aspeed_scu_properties[] = {
479 DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
480 DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
481 DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
482 DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
483 DEFINE_PROP_END_OF_LIST(),
484 };
485
486 static void aspeed_scu_class_init(ObjectClass *klass, void *data)
487 {
488 DeviceClass *dc = DEVICE_CLASS(klass);
489 dc->realize = aspeed_scu_realize;
490 dc->reset = aspeed_scu_reset;
491 dc->desc = "ASPEED System Control Unit";
492 dc->vmsd = &vmstate_aspeed_scu;
493 device_class_set_props(dc, aspeed_scu_properties);
494 }
495
496 static const TypeInfo aspeed_scu_info = {
497 .name = TYPE_ASPEED_SCU,
498 .parent = TYPE_SYS_BUS_DEVICE,
499 .instance_size = sizeof(AspeedSCUState),
500 .class_init = aspeed_scu_class_init,
501 .class_size = sizeof(AspeedSCUClass),
502 .abstract = true,
503 };
504
505 static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data)
506 {
507 DeviceClass *dc = DEVICE_CLASS(klass);
508 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
509
510 dc->desc = "ASPEED 2400 System Control Unit";
511 asc->resets = ast2400_a0_resets;
512 asc->calc_hpll = aspeed_2400_scu_calc_hpll;
513 asc->apb_divider = 2;
514 asc->nr_regs = ASPEED_SCU_NR_REGS;
515 asc->ops = &aspeed_ast2400_scu_ops;
516 }
517
518 static const TypeInfo aspeed_2400_scu_info = {
519 .name = TYPE_ASPEED_2400_SCU,
520 .parent = TYPE_ASPEED_SCU,
521 .instance_size = sizeof(AspeedSCUState),
522 .class_init = aspeed_2400_scu_class_init,
523 };
524
525 static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data)
526 {
527 DeviceClass *dc = DEVICE_CLASS(klass);
528 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
529
530 dc->desc = "ASPEED 2500 System Control Unit";
531 asc->resets = ast2500_a1_resets;
532 asc->calc_hpll = aspeed_2500_scu_calc_hpll;
533 asc->apb_divider = 4;
534 asc->nr_regs = ASPEED_SCU_NR_REGS;
535 asc->ops = &aspeed_ast2500_scu_ops;
536 }
537
538 static const TypeInfo aspeed_2500_scu_info = {
539 .name = TYPE_ASPEED_2500_SCU,
540 .parent = TYPE_ASPEED_SCU,
541 .instance_size = sizeof(AspeedSCUState),
542 .class_init = aspeed_2500_scu_class_init,
543 };
544
545 static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset,
546 unsigned size)
547 {
548 AspeedSCUState *s = ASPEED_SCU(opaque);
549 int reg = TO_REG(offset);
550
551 if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
552 qemu_log_mask(LOG_GUEST_ERROR,
553 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
554 __func__, offset);
555 return 0;
556 }
557
558 switch (reg) {
559 case AST2600_HPLL_EXT:
560 case AST2600_EPLL_EXT:
561 case AST2600_MPLL_EXT:
562 /* PLLs are always "locked" */
563 return s->regs[reg] | BIT(31);
564 case AST2600_RNG_DATA:
565 /*
566 * On hardware, RNG_DATA works regardless of the state of the
567 * enable bit in RNG_CTRL
568 *
569 * TODO: Check this is true for ast2600
570 */
571 s->regs[AST2600_RNG_DATA] = aspeed_scu_get_random();
572 break;
573 }
574
575 return s->regs[reg];
576 }
577
578 static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset,
579 uint64_t data64, unsigned size)
580 {
581 AspeedSCUState *s = ASPEED_SCU(opaque);
582 int reg = TO_REG(offset);
583 /* Truncate here so bitwise operations below behave as expected */
584 uint32_t data = data64;
585
586 if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
587 qemu_log_mask(LOG_GUEST_ERROR,
588 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
589 __func__, offset);
590 return;
591 }
592
593 if (reg > PROT_KEY && !s->regs[PROT_KEY]) {
594 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
595 }
596
597 trace_aspeed_scu_write(offset, size, data);
598
599 switch (reg) {
600 case AST2600_PROT_KEY:
601 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
602 return;
603 case AST2600_HW_STRAP1:
604 case AST2600_HW_STRAP2:
605 if (s->regs[reg + 2]) {
606 return;
607 }
608 /* fall through */
609 case AST2600_SYS_RST_CTRL:
610 case AST2600_SYS_RST_CTRL2:
611 case AST2600_CLK_STOP_CTRL:
612 case AST2600_CLK_STOP_CTRL2:
613 /* W1S (Write 1 to set) registers */
614 s->regs[reg] |= data;
615 return;
616 case AST2600_SYS_RST_CTRL_CLR:
617 case AST2600_SYS_RST_CTRL2_CLR:
618 case AST2600_CLK_STOP_CTRL_CLR:
619 case AST2600_CLK_STOP_CTRL2_CLR:
620 case AST2600_HW_STRAP1_CLR:
621 case AST2600_HW_STRAP2_CLR:
622 /*
623 * W1C (Write 1 to clear) registers are offset by one address from
624 * the data register
625 */
626 s->regs[reg - 1] &= ~data;
627 return;
628
629 case AST2600_RNG_DATA:
630 case AST2600_SILICON_REV:
631 case AST2600_SILICON_REV2:
632 case AST2600_CHIP_ID0:
633 case AST2600_CHIP_ID1:
634 /* Add read only registers here */
635 qemu_log_mask(LOG_GUEST_ERROR,
636 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
637 __func__, offset);
638 return;
639 }
640
641 s->regs[reg] = data;
642 }
643
644 static const MemoryRegionOps aspeed_ast2600_scu_ops = {
645 .read = aspeed_ast2600_scu_read,
646 .write = aspeed_ast2600_scu_write,
647 .endianness = DEVICE_LITTLE_ENDIAN,
648 .valid.min_access_size = 4,
649 .valid.max_access_size = 4,
650 .valid.unaligned = false,
651 };
652
653 static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
654 [AST2600_SYS_RST_CTRL] = 0xF7C3FED8,
655 [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC,
656 [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A,
657 [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
658 [AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */
659 [AST2600_HPLL_PARAM] = 0x1000405F,
660 [AST2600_CHIP_ID0] = 0x1234ABCD,
661 [AST2600_CHIP_ID1] = 0x88884444,
662
663 };
664
665 static void aspeed_ast2600_scu_reset(DeviceState *dev)
666 {
667 AspeedSCUState *s = ASPEED_SCU(dev);
668 AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
669
670 memcpy(s->regs, asc->resets, asc->nr_regs * 4);
671
672 s->regs[AST2600_SILICON_REV] = s->silicon_rev;
673 s->regs[AST2600_SILICON_REV2] = s->silicon_rev;
674 s->regs[AST2600_HW_STRAP1] = s->hw_strap1;
675 s->regs[AST2600_HW_STRAP2] = s->hw_strap2;
676 s->regs[PROT_KEY] = s->hw_prot_key;
677 }
678
679 static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
680 {
681 DeviceClass *dc = DEVICE_CLASS(klass);
682 AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
683
684 dc->desc = "ASPEED 2600 System Control Unit";
685 dc->reset = aspeed_ast2600_scu_reset;
686 asc->resets = ast2600_a1_resets;
687 asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */
688 asc->apb_divider = 4;
689 asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
690 asc->ops = &aspeed_ast2600_scu_ops;
691 }
692
693 static const TypeInfo aspeed_2600_scu_info = {
694 .name = TYPE_ASPEED_2600_SCU,
695 .parent = TYPE_ASPEED_SCU,
696 .instance_size = sizeof(AspeedSCUState),
697 .class_init = aspeed_2600_scu_class_init,
698 };
699
700 static void aspeed_scu_register_types(void)
701 {
702 type_register_static(&aspeed_scu_info);
703 type_register_static(&aspeed_2400_scu_info);
704 type_register_static(&aspeed_2500_scu_info);
705 type_register_static(&aspeed_2600_scu_info);
706 }
707
708 type_init(aspeed_scu_register_types);
AR7 emulation for QEMU