hw/ppc/virtex_ml507.c

   1 /*
   2  * Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
   3  *
   4  * Copyright (c) 2010 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu-common.h"
  27 #include "qemu/datadir.h"
  28 #include "qemu/units.h"
  29 #include "cpu.h"
  30 #include "hw/sysbus.h"
  31 #include "hw/char/serial.h"
  32 #include "hw/block/flash.h"
  33 #include "sysemu/sysemu.h"
  34 #include "sysemu/reset.h"
  35 #include "hw/boards.h"
  36 #include "sysemu/device_tree.h"
  37 #include "hw/loader.h"
  38 #include "elf.h"
  39 #include "qapi/error.h"
  40 #include "qemu/error-report.h"
  41 #include "qemu/log.h"
  42 #include "qemu/option.h"
  43 #include "exec/address-spaces.h"
  44
  45 #include "hw/intc/ppc-uic.h"
  46 #include "hw/ppc/ppc.h"
  47 #include "hw/ppc/ppc4xx.h"
  48 #include "hw/qdev-properties.h"
  49 #include "ppc405.h"
  50
  51 #define EPAPR_MAGIC    (0x45504150)
  52 #define FLASH_SIZE     (16 * MiB)
  53
  54 #define INTC_BASEADDR       0x81800000
  55 #define UART16550_BASEADDR  0x83e01003
  56 #define TIMER_BASEADDR      0x83c00000
  57 #define PFLASH_BASEADDR     0xfc000000
  58
  59 #define TIMER_IRQ           3
  60 #define UART16550_IRQ       9
  61
  62 static struct boot_info
  63 {
  64     uint32_t bootstrap_pc;
  65     uint32_t cmdline;
  66     uint32_t fdt;
  67     uint32_t ima_size;
  68     void *vfdt;
  69 } boot_info;
  70
  71 /* Create reset TLB entries for BookE, spanning the 32bit addr space.  */
  72 static void mmubooke_create_initial_mapping(CPUPPCState *env,
  73                                      target_ulong va,
  74                                      hwaddr pa)
  75 {
  76     ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
  77
  78     tlb->attr = 0;
  79     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
  80     tlb->size = 1U << 31; /* up to 0x80000000  */
  81     tlb->EPN = va & TARGET_PAGE_MASK;
  82     tlb->RPN = pa & TARGET_PAGE_MASK;
  83     tlb->PID = 0;
  84
  85     tlb = &env->tlb.tlbe[1];
  86     tlb->attr = 0;
  87     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
  88     tlb->size = 1U << 31; /* up to 0xffffffff  */
  89     tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
  90     tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
  91     tlb->PID = 0;
  92 }
  93
  94 static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk)
  95 {
  96     PowerPCCPU *cpu;
  97     CPUPPCState *env;
  98     DeviceState *uicdev;
  99     SysBusDevice *uicsbd;
 100
 101     cpu = POWERPC_CPU(cpu_create(cpu_type));
 102     env = &cpu->env;
 103
 104     ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);
 105
 106     ppc_dcr_init(env, NULL, NULL);
 107
 108     /* interrupt controller */
 109     uicdev = qdev_new(TYPE_PPC_UIC);
 110     uicsbd = SYS_BUS_DEVICE(uicdev);
 111
 112     object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
 113                              &error_fatal);
 114     sysbus_realize_and_unref(uicsbd, &error_fatal);
 115
 116     sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
 117                        ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
 118     sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
 119                        ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
 120
 121     /* This board doesn't wire anything up to the inputs of the UIC. */
 122     return cpu;
 123 }
 124
 125 static void main_cpu_reset(void *opaque)
 126 {
 127     PowerPCCPU *cpu = opaque;
 128     CPUPPCState *env = &cpu->env;
 129     struct boot_info *bi = env->load_info;
 130
 131     cpu_reset(CPU(cpu));
 132     /* Linux Kernel Parameters (passing device tree):
 133        *   r3: pointer to the fdt
 134        *   r4: 0
 135        *   r5: 0
 136        *   r6: epapr magic
 137        *   r7: size of IMA in bytes
 138        *   r8: 0
 139        *   r9: 0
 140     */
 141     env->gpr[1] = (16 * MiB) - 8;
 142     /* Provide a device-tree.  */
 143     env->gpr[3] = bi->fdt;
 144     env->nip = bi->bootstrap_pc;
 145
 146     /* Create a mapping for the kernel.  */
 147     mmubooke_create_initial_mapping(env, 0, 0);
 148     env->gpr[6] = tswap32(EPAPR_MAGIC);
 149     env->gpr[7] = bi->ima_size;
 150 }
 151
 152 #define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
 153 static int xilinx_load_device_tree(hwaddr addr,
 154                                       uint32_t ramsize,
 155                                       hwaddr initrd_base,
 156                                       hwaddr initrd_size,
 157                                       const char *kernel_cmdline)
 158 {
 159     char *path;
 160     int fdt_size;
 161     void *fdt = NULL;
 162     int r;
 163     const char *dtb_filename;
 164
 165     dtb_filename = current_machine->dtb;
 166     if (dtb_filename) {
 167         fdt = load_device_tree(dtb_filename, &fdt_size);
 168         if (!fdt) {
 169             error_report("Error while loading device tree file '%s'",
 170                 dtb_filename);
 171         }
 172     } else {
 173         /* Try the local "ppc.dtb" override.  */
 174         fdt = load_device_tree("ppc.dtb", &fdt_size);
 175         if (!fdt) {
 176             path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
 177             if (path) {
 178                 fdt = load_device_tree(path, &fdt_size);
 179                 g_free(path);
 180             }
 181         }
 182     }
 183     if (!fdt) {
 184         return 0;
 185     }
 186
 187     r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
 188                               initrd_base);
 189     if (r < 0) {
 190         error_report("couldn't set /chosen/linux,initrd-start");
 191     }
 192
 193     r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 194                               (initrd_base + initrd_size));
 195     if (r < 0) {
 196         error_report("couldn't set /chosen/linux,initrd-end");
 197     }
 198
 199     r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
 200     if (r < 0)
 201         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 202     cpu_physical_memory_write(addr, fdt, fdt_size);
 203     g_free(fdt);
 204     return fdt_size;
 205 }
 206
 207 static void virtex_init(MachineState *machine)
 208 {
 209     const char *kernel_filename = machine->kernel_filename;
 210     const char *kernel_cmdline = machine->kernel_cmdline;
 211     hwaddr initrd_base = 0;
 212     int initrd_size = 0;
 213     MemoryRegion *address_space_mem = get_system_memory();
 214     DeviceState *dev;
 215     PowerPCCPU *cpu;
 216     CPUPPCState *env;
 217     hwaddr ram_base = 0;
 218     DriveInfo *dinfo;
 219     qemu_irq irq[32], *cpu_irq;
 220     int kernel_size;
 221     int i;
 222
 223     /* init CPUs */
 224     cpu = ppc440_init_xilinx(machine->cpu_type, 400000000);
 225     env = &cpu->env;
 226
 227     if (env->mmu_model != POWERPC_MMU_BOOKE) {
 228         error_report("MMU model %i not supported by this machine",
 229                      env->mmu_model);
 230         exit(1);
 231     }
 232
 233     qemu_register_reset(main_cpu_reset, cpu);
 234
 235     memory_region_add_subregion(address_space_mem, ram_base, machine->ram);
 236
 237     dinfo = drive_get(IF_PFLASH, 0, 0);
 238     pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE,
 239                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 240                           64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
 241
 242     cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
 243     dev = qdev_new("xlnx.xps-intc");
 244     qdev_prop_set_uint32(dev, "kind-of-intr", 0);
 245     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 246     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
 247     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
 248     for (i = 0; i < 32; i++) {
 249         irq[i] = qdev_get_gpio_in(dev, i);
 250     }
 251
 252     serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
 253                    115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
 254
 255     /* 2 timers at irq 2 @ 62 Mhz.  */
 256     dev = qdev_new("xlnx.xps-timer");
 257     qdev_prop_set_uint32(dev, "one-timer-only", 0);
 258     qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
 259     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 260     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
 261     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
 262
 263     if (kernel_filename) {
 264         uint64_t entry, high;
 265         hwaddr boot_offset;
 266
 267         /* Boots a kernel elf binary.  */
 268         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
 269                                &entry, NULL, &high, NULL, 1, PPC_ELF_MACHINE,
 270                                0, 0);
 271         boot_info.bootstrap_pc = entry & 0x00ffffff;
 272
 273         if (kernel_size < 0) {
 274             boot_offset = 0x1200000;
 275             /* If we failed loading ELF's try a raw image.  */
 276             kernel_size = load_image_targphys(kernel_filename,
 277                                               boot_offset,
 278                                               machine->ram_size);
 279             boot_info.bootstrap_pc = boot_offset;
 280             high = boot_info.bootstrap_pc + kernel_size + 8192;
 281         }
 282
 283         boot_info.ima_size = kernel_size;
 284
 285         /* Load initrd. */
 286         if (machine->initrd_filename) {
 287             initrd_base = high = ROUND_UP(high, 4);
 288             initrd_size = load_image_targphys(machine->initrd_filename,
 289                                               high, machine->ram_size - high);
 290
 291             if (initrd_size < 0) {
 292                 error_report("couldn't load ram disk '%s'",
 293                              machine->initrd_filename);
 294                 exit(1);
 295             }
 296             high = ROUND_UP(high + initrd_size, 4);
 297         }
 298
 299         /* Provide a device-tree.  */
 300         boot_info.fdt = high + (8192 * 2);
 301         boot_info.fdt &= ~8191;
 302
 303         xilinx_load_device_tree(boot_info.fdt, machine->ram_size,
 304                                 initrd_base, initrd_size,
 305                                 kernel_cmdline);
 306     }
 307     env->load_info = &boot_info;
 308 }
 309
 310 static void virtex_machine_init(MachineClass *mc)
 311 {
 312     mc->desc = "Xilinx Virtex ML507 reference design";
 313     mc->init = virtex_init;
 314     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx");
 315     mc->default_ram_id = "ram";
 316 }
 317
 318 DEFINE_MACHINE("virtex-ml507", virtex_machine_init)