hw/i386/fw_cfg.c

   1 /*
   2  * QEMU fw_cfg helpers (X86 specific)
   3  *
   4  * Copyright (c) 2019 Red Hat, Inc.
   5  *
   6  * Author:
   7  *   Philippe Mathieu-Daudé <philmd@redhat.com>
   8  *
   9  * SPDX-License-Identifier: GPL-2.0-or-later
  10  *
  11  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  12  * See the COPYING file in the top-level directory.
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "sysemu/numa.h"
  17 #include "hw/acpi/acpi.h"
  18 #include "hw/acpi/aml-build.h"
  19 #include "hw/firmware/smbios.h"
  20 #include "hw/i386/fw_cfg.h"
  21 #include "hw/timer/hpet.h"
  22 #include "hw/nvram/fw_cfg.h"
  23 #include "e820_memory_layout.h"
  24 #include "kvm/kvm_i386.h"
  25 #include CONFIG_DEVICES
  26
  27 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  28
  29 const char *fw_cfg_arch_key_name(uint16_t key)
  30 {
  31     static const struct {
  32         uint16_t key;
  33         const char *name;
  34     } fw_cfg_arch_wellknown_keys[] = {
  35         {FW_CFG_ACPI_TABLES, "acpi_tables"},
  36         {FW_CFG_SMBIOS_ENTRIES, "smbios_entries"},
  37         {FW_CFG_IRQ0_OVERRIDE, "irq0_override"},
  38         {FW_CFG_E820_TABLE, "e820_table"},
  39         {FW_CFG_HPET, "hpet"},
  40     };
  41
  42     for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
  43         if (fw_cfg_arch_wellknown_keys[i].key == key) {
  44             return fw_cfg_arch_wellknown_keys[i].name;
  45         }
  46     }
  47     return NULL;
  48 }
  49
  50 void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg)
  51 {
  52 #ifdef CONFIG_SMBIOS
  53     uint8_t *smbios_tables, *smbios_anchor;
  54     size_t smbios_tables_len, smbios_anchor_len;
  55     struct smbios_phys_mem_area *mem_array;
  56     unsigned i, array_count;
  57     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
  58
  59     /* tell smbios about cpuid version and features */
  60     smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
  61
  62     smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
  63     if (smbios_tables) {
  64         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
  65                          smbios_tables, smbios_tables_len);
  66     }
  67
  68     /* build the array of physical mem area from e820 table */
  69     mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
  70     for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
  71         uint64_t addr, len;
  72
  73         if (e820_get_entry(i, E820_RAM, &addr, &len)) {
  74             mem_array[array_count].address = addr;
  75             mem_array[array_count].length = len;
  76             array_count++;
  77         }
  78     }
  79     smbios_get_tables(ms, mem_array, array_count,
  80                       &smbios_tables, &smbios_tables_len,
  81                       &smbios_anchor, &smbios_anchor_len);
  82     g_free(mem_array);
  83
  84     if (smbios_anchor) {
  85         fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
  86                         smbios_tables, smbios_tables_len);
  87         fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
  88                         smbios_anchor, smbios_anchor_len);
  89     }
  90 #endif
  91 }
  92
  93 FWCfgState *fw_cfg_arch_create(MachineState *ms,
  94                                       uint16_t boot_cpus,
  95                                       uint16_t apic_id_limit)
  96 {
  97     FWCfgState *fw_cfg;
  98     uint64_t *numa_fw_cfg;
  99     int i;
 100     MachineClass *mc = MACHINE_GET_CLASS(ms);
 101     const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms);
 102     int nb_numa_nodes = ms->numa_state->num_nodes;
 103
 104     fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
 105                                 &address_space_memory);
 106     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus);
 107
 108     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 109      *
 110      * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
 111      * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
 112      * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
 113      * for CPU hotplug also uses APIC ID and not "CPU index".
 114      * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
 115      * but the "limit to the APIC ID values SeaBIOS may see".
 116      *
 117      * So for compatibility reasons with old BIOSes we are stuck with
 118      * "etc/max-cpus" actually being apic_id_limit
 119      */
 120     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit);
 121     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ms->ram_size);
 122 #ifdef CONFIG_ACPI
 123     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 124                      acpi_tables, acpi_tables_len);
 125 #endif
 126     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, 1);
 127
 128     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 129                      &e820_reserve, sizeof(e820_reserve));
 130     fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
 131                     sizeof(struct e820_entry) * e820_get_num_entries());
 132
 133     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 134     /* allocate memory for the NUMA channel: one (64bit) word for the number
 135      * of nodes, one word for each VCPU->node and one word for each node to
 136      * hold the amount of memory.
 137      */
 138     numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
 139     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 140     for (i = 0; i < cpus->len; i++) {
 141         unsigned int apic_id = cpus->cpus[i].arch_id;
 142         assert(apic_id < apic_id_limit);
 143         numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
 144     }
 145     for (i = 0; i < nb_numa_nodes; i++) {
 146         numa_fw_cfg[apic_id_limit + 1 + i] =
 147             cpu_to_le64(ms->numa_state->nodes[i].node_mem);
 148     }
 149     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 150                      (1 + apic_id_limit + nb_numa_nodes) *
 151                      sizeof(*numa_fw_cfg));
 152
 153     return fw_cfg;
 154 }
 155
 156 void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg)
 157 {
 158     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
 159     CPUX86State *env = &cpu->env;
 160     uint32_t unused, ecx, edx;
 161     uint64_t feature_control_bits = 0;
 162     uint64_t *val;
 163
 164     cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
 165     if (ecx & CPUID_EXT_VMX) {
 166         feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
 167     }
 168
 169     if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
 170         (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
 171         (env->mcg_cap & MCG_LMCE_P)) {
 172         feature_control_bits |= FEATURE_CONTROL_LMCE;
 173     }
 174
 175     if (!feature_control_bits) {
 176         return;
 177     }
 178
 179     val = g_malloc(sizeof(*val));
 180     *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
 181     fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
 182 }
 183
 184 void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg)
 185 {
 186     /*
 187      * when using port i/o, the 8-bit data register *always* overlaps
 188      * with half of the 16-bit control register. Hence, the total size
 189      * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
 190      * DMA control register is located at FW_CFG_DMA_IO_BASE + 4
 191      */
 192     Object *obj = OBJECT(fw_cfg);
 193     uint8_t io_size = object_property_get_bool(obj, "dma_enabled", NULL) ?
 194         ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
 195         FW_CFG_CTL_SIZE;
 196     Aml *dev = aml_device("FWCF");
 197     Aml *crs = aml_resource_template();
 198
 199     aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
 200
 201     /* device present, functioning, decoding, not shown in UI */
 202     aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
 203
 204     aml_append(crs,
 205         aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size));
 206
 207     aml_append(dev, aml_name_decl("_CRS", crs));
 208     aml_append(scope, dev);
 209 }