hw/i386/fw_cfg.c

   1 /*
   2  * QEMU fw_cfg helpers (X86 specific)
   3  *
   4  * Copyright (c) 2019 Red Hat, Inc.
   5  *
   6  * Author:
   7  *   Philippe Mathieu-Daudé <philmd@redhat.com>
   8  *
   9  * SPDX-License-Identifier: GPL-2.0-or-later
  10  *
  11  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  12  * See the COPYING file in the top-level directory.
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "sysemu/numa.h"
  17 #include "hw/acpi/acpi.h"
  18 #include "hw/acpi/aml-build.h"
  19 #include "hw/firmware/smbios.h"
  20 #include "hw/i386/fw_cfg.h"
  21 #include "hw/timer/hpet.h"
  22 #include "hw/nvram/fw_cfg.h"
  23 #include "e820_memory_layout.h"
  24 #include "kvm/kvm_i386.h"
  25 #include "qapi/error.h"
  26 #include CONFIG_DEVICES
  27 #include "target/i386/cpu.h"
  28
  29 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  30
  31 const char *fw_cfg_arch_key_name(uint16_t key)
  32 {
  33     static const struct {
  34         uint16_t key;
  35         const char *name;
  36     } fw_cfg_arch_wellknown_keys[] = {
  37         {FW_CFG_ACPI_TABLES, "acpi_tables"},
  38         {FW_CFG_SMBIOS_ENTRIES, "smbios_entries"},
  39         {FW_CFG_IRQ0_OVERRIDE, "irq0_override"},
  40         {FW_CFG_HPET, "hpet"},
  41     };
  42
  43     for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
  44         if (fw_cfg_arch_wellknown_keys[i].key == key) {
  45             return fw_cfg_arch_wellknown_keys[i].name;
  46         }
  47     }
  48     return NULL;
  49 }
  50
  51 /* Add etc/e820 late, once all regions should be present */
  52 void fw_cfg_add_e820(FWCfgState *fw_cfg)
  53 {
  54     struct e820_entry *table;
  55     int nr_e820 = e820_get_table(&table);
  56
  57     fw_cfg_add_file(fw_cfg, "etc/e820", table, nr_e820 * sizeof(*table));
  58 }
  59
  60 void fw_cfg_build_smbios(PCMachineState *pcms, FWCfgState *fw_cfg,
  61                          SmbiosEntryPointType ep_type)
  62 {
  63 #ifdef CONFIG_SMBIOS
  64     uint8_t *smbios_tables, *smbios_anchor;
  65     size_t smbios_tables_len, smbios_anchor_len;
  66     struct smbios_phys_mem_area *mem_array;
  67     unsigned i, array_count;
  68     MachineState *ms = MACHINE(pcms);
  69     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
  70     MachineClass *mc = MACHINE_GET_CLASS(pcms);
  71     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
  72     int nr_e820;
  73
  74     if (pcmc->smbios_defaults) {
  75         /* These values are guest ABI, do not change */
  76         smbios_set_defaults("QEMU", mc->desc, mc->name);
  77     }
  78
  79     /* tell smbios about cpuid version and features */
  80     smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
  81
  82     if (pcmc->smbios_legacy_mode) {
  83         smbios_tables = smbios_get_table_legacy(&smbios_tables_len,
  84                                                 &error_fatal);
  85         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
  86                          smbios_tables, smbios_tables_len);
  87         return;
  88     }
  89
  90     /* build the array of physical mem area from e820 table */
  91     nr_e820 = e820_get_table(NULL);
  92     mem_array = g_malloc0(sizeof(*mem_array) * nr_e820);
  93     for (i = 0, array_count = 0; i < nr_e820; i++) {
  94         uint64_t addr, len;
  95
  96         if (e820_get_entry(i, E820_RAM, &addr, &len)) {
  97             mem_array[array_count].address = addr;
  98             mem_array[array_count].length = len;
  99             array_count++;
 100         }
 101     }
 102     smbios_get_tables(ms, ep_type, mem_array, array_count,
 103                       &smbios_tables, &smbios_tables_len,
 104                       &smbios_anchor, &smbios_anchor_len,
 105                       &error_fatal);
 106     g_free(mem_array);
 107
 108     if (smbios_anchor) {
 109         fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
 110                         smbios_tables, smbios_tables_len);
 111         fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
 112                         smbios_anchor, smbios_anchor_len);
 113     }
 114 #endif
 115 }
 116
 117 FWCfgState *fw_cfg_arch_create(MachineState *ms,
 118                                       uint16_t boot_cpus,
 119                                       uint16_t apic_id_limit)
 120 {
 121     FWCfgState *fw_cfg;
 122     uint64_t *numa_fw_cfg;
 123     int i;
 124     MachineClass *mc = MACHINE_GET_CLASS(ms);
 125     const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms);
 126     int nb_numa_nodes = ms->numa_state->num_nodes;
 127
 128     fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
 129                                 &address_space_memory);
 130     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus);
 131
 132     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 133      *
 134      * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
 135      * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
 136      * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
 137      * for CPU hotplug also uses APIC ID and not "CPU index".
 138      * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
 139      * but the "limit to the APIC ID values SeaBIOS may see".
 140      *
 141      * So for compatibility reasons with old BIOSes we are stuck with
 142      * "etc/max-cpus" actually being apic_id_limit
 143      */
 144     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit);
 145     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ms->ram_size);
 146 #ifdef CONFIG_ACPI
 147     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 148                      acpi_tables, acpi_tables_len);
 149 #endif
 150     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, 1);
 151
 152     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 153     /* allocate memory for the NUMA channel: one (64bit) word for the number
 154      * of nodes, one word for each VCPU->node and one word for each node to
 155      * hold the amount of memory.
 156      */
 157     numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
 158     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 159     for (i = 0; i < cpus->len; i++) {
 160         unsigned int apic_id = cpus->cpus[i].arch_id;
 161         assert(apic_id < apic_id_limit);
 162         numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
 163     }
 164     for (i = 0; i < nb_numa_nodes; i++) {
 165         numa_fw_cfg[apic_id_limit + 1 + i] =
 166             cpu_to_le64(ms->numa_state->nodes[i].node_mem);
 167     }
 168     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 169                      (1 + apic_id_limit + nb_numa_nodes) *
 170                      sizeof(*numa_fw_cfg));
 171
 172     return fw_cfg;
 173 }
 174
 175 void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg)
 176 {
 177     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
 178     CPUX86State *env = &cpu->env;
 179     uint32_t unused, ebx, ecx, edx;
 180     uint64_t feature_control_bits = 0;
 181     uint64_t *val;
 182
 183     cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
 184     if (ecx & CPUID_EXT_VMX) {
 185         feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
 186     }
 187
 188     if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
 189         (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
 190         (env->mcg_cap & MCG_LMCE_P)) {
 191         feature_control_bits |= FEATURE_CONTROL_LMCE;
 192     }
 193
 194     if (env->cpuid_level >= 7) {
 195         cpu_x86_cpuid(env, 0x7, 0, &unused, &ebx, &ecx, &unused);
 196         if (ebx & CPUID_7_0_EBX_SGX) {
 197             feature_control_bits |= FEATURE_CONTROL_SGX;
 198         }
 199         if (ecx & CPUID_7_0_ECX_SGX_LC) {
 200             feature_control_bits |= FEATURE_CONTROL_SGX_LC;
 201         }
 202     }
 203
 204     if (!feature_control_bits) {
 205         return;
 206     }
 207
 208     val = g_malloc(sizeof(*val));
 209     *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
 210     fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
 211 }
 212
 213 #ifdef CONFIG_ACPI
 214 void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg)
 215 {
 216     /*
 217      * when using port i/o, the 8-bit data register *always* overlaps
 218      * with half of the 16-bit control register. Hence, the total size
 219      * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
 220      * DMA control register is located at FW_CFG_DMA_IO_BASE + 4
 221      */
 222     Object *obj = OBJECT(fw_cfg);
 223     uint8_t io_size = object_property_get_bool(obj, "dma_enabled", NULL) ?
 224         ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
 225         FW_CFG_CTL_SIZE;
 226     Aml *dev = aml_device("FWCF");
 227     Aml *crs = aml_resource_template();
 228
 229     aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
 230
 231     /* device present, functioning, decoding, not shown in UI */
 232     aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
 233
 234     aml_append(crs,
 235         aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size));
 236
 237     aml_append(dev, aml_name_decl("_CRS", crs));
 238     aml_append(scope, dev);
 239 }
 240 #endif