2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
25 #include "hw/sysbus.h"
26 #include "exec/address-spaces.h"
27 #include "intel_iommu_internal.h"
28 #include "hw/pci/pci.h"
29 #include "hw/pci/pci_bus.h"
30 #include "hw/i386/pc.h"
31 #include "hw/i386/apic-msidef.h"
32 #include "hw/boards.h"
33 #include "hw/i386/x86-iommu.h"
34 #include "hw/pci-host/q35.h"
35 #include "sysemu/kvm.h"
36 #include "hw/i386/apic_internal.h"
40 static void vtd_define_quad(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
,
41 uint64_t wmask
, uint64_t w1cmask
)
43 stq_le_p(&s
->csr
[addr
], val
);
44 stq_le_p(&s
->wmask
[addr
], wmask
);
45 stq_le_p(&s
->w1cmask
[addr
], w1cmask
);
48 static void vtd_define_quad_wo(IntelIOMMUState
*s
, hwaddr addr
, uint64_t mask
)
50 stq_le_p(&s
->womask
[addr
], mask
);
53 static void vtd_define_long(IntelIOMMUState
*s
, hwaddr addr
, uint32_t val
,
54 uint32_t wmask
, uint32_t w1cmask
)
56 stl_le_p(&s
->csr
[addr
], val
);
57 stl_le_p(&s
->wmask
[addr
], wmask
);
58 stl_le_p(&s
->w1cmask
[addr
], w1cmask
);
61 static void vtd_define_long_wo(IntelIOMMUState
*s
, hwaddr addr
, uint32_t mask
)
63 stl_le_p(&s
->womask
[addr
], mask
);
66 /* "External" get/set operations */
67 static void vtd_set_quad(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
)
69 uint64_t oldval
= ldq_le_p(&s
->csr
[addr
]);
70 uint64_t wmask
= ldq_le_p(&s
->wmask
[addr
]);
71 uint64_t w1cmask
= ldq_le_p(&s
->w1cmask
[addr
]);
72 stq_le_p(&s
->csr
[addr
],
73 ((oldval
& ~wmask
) | (val
& wmask
)) & ~(w1cmask
& val
));
76 static void vtd_set_long(IntelIOMMUState
*s
, hwaddr addr
, uint32_t val
)
78 uint32_t oldval
= ldl_le_p(&s
->csr
[addr
]);
79 uint32_t wmask
= ldl_le_p(&s
->wmask
[addr
]);
80 uint32_t w1cmask
= ldl_le_p(&s
->w1cmask
[addr
]);
81 stl_le_p(&s
->csr
[addr
],
82 ((oldval
& ~wmask
) | (val
& wmask
)) & ~(w1cmask
& val
));
85 static uint64_t vtd_get_quad(IntelIOMMUState
*s
, hwaddr addr
)
87 uint64_t val
= ldq_le_p(&s
->csr
[addr
]);
88 uint64_t womask
= ldq_le_p(&s
->womask
[addr
]);
92 static uint32_t vtd_get_long(IntelIOMMUState
*s
, hwaddr addr
)
94 uint32_t val
= ldl_le_p(&s
->csr
[addr
]);
95 uint32_t womask
= ldl_le_p(&s
->womask
[addr
]);
99 /* "Internal" get/set operations */
100 static uint64_t vtd_get_quad_raw(IntelIOMMUState
*s
, hwaddr addr
)
102 return ldq_le_p(&s
->csr
[addr
]);
105 static uint32_t vtd_get_long_raw(IntelIOMMUState
*s
, hwaddr addr
)
107 return ldl_le_p(&s
->csr
[addr
]);
110 static void vtd_set_quad_raw(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
)
112 stq_le_p(&s
->csr
[addr
], val
);
115 static uint32_t vtd_set_clear_mask_long(IntelIOMMUState
*s
, hwaddr addr
,
116 uint32_t clear
, uint32_t mask
)
118 uint32_t new_val
= (ldl_le_p(&s
->csr
[addr
]) & ~clear
) | mask
;
119 stl_le_p(&s
->csr
[addr
], new_val
);
123 static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState
*s
, hwaddr addr
,
124 uint64_t clear
, uint64_t mask
)
126 uint64_t new_val
= (ldq_le_p(&s
->csr
[addr
]) & ~clear
) | mask
;
127 stq_le_p(&s
->csr
[addr
], new_val
);
131 static inline void vtd_iommu_lock(IntelIOMMUState
*s
)
133 qemu_mutex_lock(&s
->iommu_lock
);
136 static inline void vtd_iommu_unlock(IntelIOMMUState
*s
)
138 qemu_mutex_unlock(&s
->iommu_lock
);
141 /* Whether the address space needs to notify new mappings */
142 static inline gboolean
vtd_as_has_map_notifier(VTDAddressSpace
*as
)
144 return as
->notifier_flags
& IOMMU_NOTIFIER_MAP
;
147 /* GHashTable functions */
148 static gboolean
vtd_uint64_equal(gconstpointer v1
, gconstpointer v2
)
150 return *((const uint64_t *)v1
) == *((const uint64_t *)v2
);
153 static guint
vtd_uint64_hash(gconstpointer v
)
155 return (guint
)*(const uint64_t *)v
;
158 static gboolean
vtd_hash_remove_by_domain(gpointer key
, gpointer value
,
161 VTDIOTLBEntry
*entry
= (VTDIOTLBEntry
*)value
;
162 uint16_t domain_id
= *(uint16_t *)user_data
;
163 return entry
->domain_id
== domain_id
;
166 /* The shift of an addr for a certain level of paging structure */
167 static inline uint32_t vtd_slpt_level_shift(uint32_t level
)
170 return VTD_PAGE_SHIFT_4K
+ (level
- 1) * VTD_SL_LEVEL_BITS
;
173 static inline uint64_t vtd_slpt_level_page_mask(uint32_t level
)
175 return ~((1ULL << vtd_slpt_level_shift(level
)) - 1);
178 static gboolean
vtd_hash_remove_by_page(gpointer key
, gpointer value
,
181 VTDIOTLBEntry
*entry
= (VTDIOTLBEntry
*)value
;
182 VTDIOTLBPageInvInfo
*info
= (VTDIOTLBPageInvInfo
*)user_data
;
183 uint64_t gfn
= (info
->addr
>> VTD_PAGE_SHIFT_4K
) & info
->mask
;
184 uint64_t gfn_tlb
= (info
->addr
& entry
->mask
) >> VTD_PAGE_SHIFT_4K
;
185 return (entry
->domain_id
== info
->domain_id
) &&
186 (((entry
->gfn
& info
->mask
) == gfn
) ||
187 (entry
->gfn
== gfn_tlb
));
190 /* Reset all the gen of VTDAddressSpace to zero and set the gen of
191 * IntelIOMMUState to 1. Must be called with IOMMU lock held.
193 static void vtd_reset_context_cache_locked(IntelIOMMUState
*s
)
195 VTDAddressSpace
*vtd_as
;
197 GHashTableIter bus_it
;
200 trace_vtd_context_cache_reset();
202 g_hash_table_iter_init(&bus_it
, s
->vtd_as_by_busptr
);
204 while (g_hash_table_iter_next (&bus_it
, NULL
, (void**)&vtd_bus
)) {
205 for (devfn_it
= 0; devfn_it
< PCI_DEVFN_MAX
; ++devfn_it
) {
206 vtd_as
= vtd_bus
->dev_as
[devfn_it
];
210 vtd_as
->context_cache_entry
.context_cache_gen
= 0;
213 s
->context_cache_gen
= 1;
216 /* Must be called with IOMMU lock held. */
217 static void vtd_reset_iotlb_locked(IntelIOMMUState
*s
)
220 g_hash_table_remove_all(s
->iotlb
);
223 static void vtd_reset_iotlb(IntelIOMMUState
*s
)
226 vtd_reset_iotlb_locked(s
);
230 static uint64_t vtd_get_iotlb_key(uint64_t gfn
, uint16_t source_id
,
233 return gfn
| ((uint64_t)(source_id
) << VTD_IOTLB_SID_SHIFT
) |
234 ((uint64_t)(level
) << VTD_IOTLB_LVL_SHIFT
);
237 static uint64_t vtd_get_iotlb_gfn(hwaddr addr
, uint32_t level
)
239 return (addr
& vtd_slpt_level_page_mask(level
)) >> VTD_PAGE_SHIFT_4K
;
242 /* Must be called with IOMMU lock held */
243 static VTDIOTLBEntry
*vtd_lookup_iotlb(IntelIOMMUState
*s
, uint16_t source_id
,
246 VTDIOTLBEntry
*entry
;
250 for (level
= VTD_SL_PT_LEVEL
; level
< VTD_SL_PML4_LEVEL
; level
++) {
251 key
= vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr
, level
),
253 entry
= g_hash_table_lookup(s
->iotlb
, &key
);
263 /* Must be with IOMMU lock held */
264 static void vtd_update_iotlb(IntelIOMMUState
*s
, uint16_t source_id
,
265 uint16_t domain_id
, hwaddr addr
, uint64_t slpte
,
266 uint8_t access_flags
, uint32_t level
)
268 VTDIOTLBEntry
*entry
= g_malloc(sizeof(*entry
));
269 uint64_t *key
= g_malloc(sizeof(*key
));
270 uint64_t gfn
= vtd_get_iotlb_gfn(addr
, level
);
272 trace_vtd_iotlb_page_update(source_id
, addr
, slpte
, domain_id
);
273 if (g_hash_table_size(s
->iotlb
) >= VTD_IOTLB_MAX_SIZE
) {
274 trace_vtd_iotlb_reset("iotlb exceeds size limit");
275 vtd_reset_iotlb_locked(s
);
279 entry
->domain_id
= domain_id
;
280 entry
->slpte
= slpte
;
281 entry
->access_flags
= access_flags
;
282 entry
->mask
= vtd_slpt_level_page_mask(level
);
283 *key
= vtd_get_iotlb_key(gfn
, source_id
, level
);
284 g_hash_table_replace(s
->iotlb
, key
, entry
);
287 /* Given the reg addr of both the message data and address, generate an
290 static void vtd_generate_interrupt(IntelIOMMUState
*s
, hwaddr mesg_addr_reg
,
291 hwaddr mesg_data_reg
)
295 assert(mesg_data_reg
< DMAR_REG_SIZE
);
296 assert(mesg_addr_reg
< DMAR_REG_SIZE
);
298 msi
.address
= vtd_get_long_raw(s
, mesg_addr_reg
);
299 msi
.data
= vtd_get_long_raw(s
, mesg_data_reg
);
301 trace_vtd_irq_generate(msi
.address
, msi
.data
);
303 apic_get_class()->send_msi(&msi
);
306 /* Generate a fault event to software via MSI if conditions are met.
307 * Notice that the value of FSTS_REG being passed to it should be the one
310 static void vtd_generate_fault_event(IntelIOMMUState
*s
, uint32_t pre_fsts
)
312 if (pre_fsts
& VTD_FSTS_PPF
|| pre_fsts
& VTD_FSTS_PFO
||
313 pre_fsts
& VTD_FSTS_IQE
) {
314 trace_vtd_err("There are previous interrupt conditions "
315 "to be serviced by software, fault event "
316 "is not generated.");
319 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, 0, VTD_FECTL_IP
);
320 if (vtd_get_long_raw(s
, DMAR_FECTL_REG
) & VTD_FECTL_IM
) {
321 trace_vtd_err("Interrupt Mask set, irq is not generated.");
323 vtd_generate_interrupt(s
, DMAR_FEADDR_REG
, DMAR_FEDATA_REG
);
324 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
328 /* Check if the Fault (F) field of the Fault Recording Register referenced by
331 static bool vtd_is_frcd_set(IntelIOMMUState
*s
, uint16_t index
)
333 /* Each reg is 128-bit */
334 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
335 addr
+= 8; /* Access the high 64-bit half */
337 assert(index
< DMAR_FRCD_REG_NR
);
339 return vtd_get_quad_raw(s
, addr
) & VTD_FRCD_F
;
342 /* Update the PPF field of Fault Status Register.
343 * Should be called whenever change the F field of any fault recording
346 static void vtd_update_fsts_ppf(IntelIOMMUState
*s
)
349 uint32_t ppf_mask
= 0;
351 for (i
= 0; i
< DMAR_FRCD_REG_NR
; i
++) {
352 if (vtd_is_frcd_set(s
, i
)) {
353 ppf_mask
= VTD_FSTS_PPF
;
357 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, VTD_FSTS_PPF
, ppf_mask
);
358 trace_vtd_fsts_ppf(!!ppf_mask
);
361 static void vtd_set_frcd_and_update_ppf(IntelIOMMUState
*s
, uint16_t index
)
363 /* Each reg is 128-bit */
364 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
365 addr
+= 8; /* Access the high 64-bit half */
367 assert(index
< DMAR_FRCD_REG_NR
);
369 vtd_set_clear_mask_quad(s
, addr
, 0, VTD_FRCD_F
);
370 vtd_update_fsts_ppf(s
);
373 /* Must not update F field now, should be done later */
374 static void vtd_record_frcd(IntelIOMMUState
*s
, uint16_t index
,
375 uint16_t source_id
, hwaddr addr
,
376 VTDFaultReason fault
, bool is_write
)
379 hwaddr frcd_reg_addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
381 assert(index
< DMAR_FRCD_REG_NR
);
383 lo
= VTD_FRCD_FI(addr
);
384 hi
= VTD_FRCD_SID(source_id
) | VTD_FRCD_FR(fault
);
388 vtd_set_quad_raw(s
, frcd_reg_addr
, lo
);
389 vtd_set_quad_raw(s
, frcd_reg_addr
+ 8, hi
);
391 trace_vtd_frr_new(index
, hi
, lo
);
394 /* Try to collapse multiple pending faults from the same requester */
395 static bool vtd_try_collapse_fault(IntelIOMMUState
*s
, uint16_t source_id
)
399 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ 8; /* The high 64-bit half */
401 for (i
= 0; i
< DMAR_FRCD_REG_NR
; i
++) {
402 frcd_reg
= vtd_get_quad_raw(s
, addr
);
403 if ((frcd_reg
& VTD_FRCD_F
) &&
404 ((frcd_reg
& VTD_FRCD_SID_MASK
) == source_id
)) {
407 addr
+= 16; /* 128-bit for each */
412 /* Log and report an DMAR (address translation) fault to software */
413 static void vtd_report_dmar_fault(IntelIOMMUState
*s
, uint16_t source_id
,
414 hwaddr addr
, VTDFaultReason fault
,
417 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
419 assert(fault
< VTD_FR_MAX
);
421 if (fault
== VTD_FR_RESERVED_ERR
) {
422 /* This is not a normal fault reason case. Drop it. */
426 trace_vtd_dmar_fault(source_id
, fault
, addr
, is_write
);
428 if (fsts_reg
& VTD_FSTS_PFO
) {
429 trace_vtd_err("New fault is not recorded due to "
430 "Primary Fault Overflow.");
434 if (vtd_try_collapse_fault(s
, source_id
)) {
435 trace_vtd_err("New fault is not recorded due to "
436 "compression of faults.");
440 if (vtd_is_frcd_set(s
, s
->next_frcd_reg
)) {
441 trace_vtd_err("Next Fault Recording Reg is used, "
442 "new fault is not recorded, set PFO field.");
443 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, 0, VTD_FSTS_PFO
);
447 vtd_record_frcd(s
, s
->next_frcd_reg
, source_id
, addr
, fault
, is_write
);
449 if (fsts_reg
& VTD_FSTS_PPF
) {
450 trace_vtd_err("There are pending faults already, "
451 "fault event is not generated.");
452 vtd_set_frcd_and_update_ppf(s
, s
->next_frcd_reg
);
454 if (s
->next_frcd_reg
== DMAR_FRCD_REG_NR
) {
455 s
->next_frcd_reg
= 0;
458 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, VTD_FSTS_FRI_MASK
,
459 VTD_FSTS_FRI(s
->next_frcd_reg
));
460 vtd_set_frcd_and_update_ppf(s
, s
->next_frcd_reg
); /* Will set PPF */
462 if (s
->next_frcd_reg
== DMAR_FRCD_REG_NR
) {
463 s
->next_frcd_reg
= 0;
465 /* This case actually cause the PPF to be Set.
466 * So generate fault event (interrupt).
468 vtd_generate_fault_event(s
, fsts_reg
);
472 /* Handle Invalidation Queue Errors of queued invalidation interface error
475 static void vtd_handle_inv_queue_error(IntelIOMMUState
*s
)
477 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
479 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, 0, VTD_FSTS_IQE
);
480 vtd_generate_fault_event(s
, fsts_reg
);
483 /* Set the IWC field and try to generate an invalidation completion interrupt */
484 static void vtd_generate_completion_event(IntelIOMMUState
*s
)
486 if (vtd_get_long_raw(s
, DMAR_ICS_REG
) & VTD_ICS_IWC
) {
487 trace_vtd_inv_desc_wait_irq("One pending, skip current");
490 vtd_set_clear_mask_long(s
, DMAR_ICS_REG
, 0, VTD_ICS_IWC
);
491 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, 0, VTD_IECTL_IP
);
492 if (vtd_get_long_raw(s
, DMAR_IECTL_REG
) & VTD_IECTL_IM
) {
493 trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, "
494 "new event not generated");
497 /* Generate the interrupt event */
498 trace_vtd_inv_desc_wait_irq("Generating complete event");
499 vtd_generate_interrupt(s
, DMAR_IEADDR_REG
, DMAR_IEDATA_REG
);
500 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
504 static inline bool vtd_root_entry_present(VTDRootEntry
*root
)
506 return root
->val
& VTD_ROOT_ENTRY_P
;
509 static int vtd_get_root_entry(IntelIOMMUState
*s
, uint8_t index
,
514 addr
= s
->root
+ index
* sizeof(*re
);
515 if (dma_memory_read(&address_space_memory
, addr
, re
, sizeof(*re
))) {
516 trace_vtd_re_invalid(re
->rsvd
, re
->val
);
518 return -VTD_FR_ROOT_TABLE_INV
;
520 re
->val
= le64_to_cpu(re
->val
);
524 static inline bool vtd_ce_present(VTDContextEntry
*context
)
526 return context
->lo
& VTD_CONTEXT_ENTRY_P
;
529 static int vtd_get_context_entry_from_root(VTDRootEntry
*root
, uint8_t index
,
534 /* we have checked that root entry is present */
535 addr
= (root
->val
& VTD_ROOT_ENTRY_CTP
) + index
* sizeof(*ce
);
536 if (dma_memory_read(&address_space_memory
, addr
, ce
, sizeof(*ce
))) {
537 trace_vtd_re_invalid(root
->rsvd
, root
->val
);
538 return -VTD_FR_CONTEXT_TABLE_INV
;
540 ce
->lo
= le64_to_cpu(ce
->lo
);
541 ce
->hi
= le64_to_cpu(ce
->hi
);
545 static inline dma_addr_t
vtd_ce_get_slpt_base(VTDContextEntry
*ce
)
547 return ce
->lo
& VTD_CONTEXT_ENTRY_SLPTPTR
;
550 static inline uint64_t vtd_get_slpte_addr(uint64_t slpte
, uint8_t aw
)
552 return slpte
& VTD_SL_PT_BASE_ADDR_MASK(aw
);
555 /* Whether the pte indicates the address of the page frame */
556 static inline bool vtd_is_last_slpte(uint64_t slpte
, uint32_t level
)
558 return level
== VTD_SL_PT_LEVEL
|| (slpte
& VTD_SL_PT_PAGE_SIZE_MASK
);
561 /* Get the content of a spte located in @base_addr[@index] */
562 static uint64_t vtd_get_slpte(dma_addr_t base_addr
, uint32_t index
)
566 assert(index
< VTD_SL_PT_ENTRY_NR
);
568 if (dma_memory_read(&address_space_memory
,
569 base_addr
+ index
* sizeof(slpte
), &slpte
,
571 slpte
= (uint64_t)-1;
574 slpte
= le64_to_cpu(slpte
);
578 /* Given an iova and the level of paging structure, return the offset
581 static inline uint32_t vtd_iova_level_offset(uint64_t iova
, uint32_t level
)
583 return (iova
>> vtd_slpt_level_shift(level
)) &
584 ((1ULL << VTD_SL_LEVEL_BITS
) - 1);
587 /* Check Capability Register to see if the @level of page-table is supported */
588 static inline bool vtd_is_level_supported(IntelIOMMUState
*s
, uint32_t level
)
590 return VTD_CAP_SAGAW_MASK
& s
->cap
&
591 (1ULL << (level
- 2 + VTD_CAP_SAGAW_SHIFT
));
594 /* Get the page-table level that hardware should use for the second-level
595 * page-table walk from the Address Width field of context-entry.
597 static inline uint32_t vtd_ce_get_level(VTDContextEntry
*ce
)
599 return 2 + (ce
->hi
& VTD_CONTEXT_ENTRY_AW
);
602 static inline uint32_t vtd_ce_get_agaw(VTDContextEntry
*ce
)
604 return 30 + (ce
->hi
& VTD_CONTEXT_ENTRY_AW
) * 9;
607 static inline uint32_t vtd_ce_get_type(VTDContextEntry
*ce
)
609 return ce
->lo
& VTD_CONTEXT_ENTRY_TT
;
612 /* Return true if check passed, otherwise false */
613 static inline bool vtd_ce_type_check(X86IOMMUState
*x86_iommu
,
616 switch (vtd_ce_get_type(ce
)) {
617 case VTD_CONTEXT_TT_MULTI_LEVEL
:
618 /* Always supported */
620 case VTD_CONTEXT_TT_DEV_IOTLB
:
621 if (!x86_iommu
->dt_supported
) {
625 case VTD_CONTEXT_TT_PASS_THROUGH
:
626 if (!x86_iommu
->pt_supported
) {
637 static inline uint64_t vtd_iova_limit(VTDContextEntry
*ce
, uint8_t aw
)
639 uint32_t ce_agaw
= vtd_ce_get_agaw(ce
);
640 return 1ULL << MIN(ce_agaw
, aw
);
643 /* Return true if IOVA passes range check, otherwise false. */
644 static inline bool vtd_iova_range_check(uint64_t iova
, VTDContextEntry
*ce
,
648 * Check if @iova is above 2^X-1, where X is the minimum of MGAW
649 * in CAP_REG and AW in context-entry.
651 return !(iova
& ~(vtd_iova_limit(ce
, aw
) - 1));
655 * Rsvd field masks for spte:
656 * Index [1] to [4] 4k pages
657 * Index [5] to [8] large pages
659 static uint64_t vtd_paging_entry_rsvd_field
[9];
661 static bool vtd_slpte_nonzero_rsvd(uint64_t slpte
, uint32_t level
)
663 if (slpte
& VTD_SL_PT_PAGE_SIZE_MASK
) {
664 /* Maybe large page */
665 return slpte
& vtd_paging_entry_rsvd_field
[level
+ 4];
667 return slpte
& vtd_paging_entry_rsvd_field
[level
];
671 /* Find the VTD address space associated with a given bus number */
672 static VTDBus
*vtd_find_as_from_bus_num(IntelIOMMUState
*s
, uint8_t bus_num
)
674 VTDBus
*vtd_bus
= s
->vtd_as_by_bus_num
[bus_num
];
677 * Iterate over the registered buses to find the one which
678 * currently hold this bus number, and update the bus_num
683 g_hash_table_iter_init(&iter
, s
->vtd_as_by_busptr
);
684 while (g_hash_table_iter_next(&iter
, NULL
, (void **)&vtd_bus
)) {
685 if (pci_bus_num(vtd_bus
->bus
) == bus_num
) {
686 s
->vtd_as_by_bus_num
[bus_num
] = vtd_bus
;
694 /* Given the @iova, get relevant @slptep. @slpte_level will be the last level
695 * of the translation, can be used for deciding the size of large page.
697 static int vtd_iova_to_slpte(VTDContextEntry
*ce
, uint64_t iova
, bool is_write
,
698 uint64_t *slptep
, uint32_t *slpte_level
,
699 bool *reads
, bool *writes
, uint8_t aw_bits
)
701 dma_addr_t addr
= vtd_ce_get_slpt_base(ce
);
702 uint32_t level
= vtd_ce_get_level(ce
);
705 uint64_t access_right_check
;
707 if (!vtd_iova_range_check(iova
, ce
, aw_bits
)) {
708 trace_vtd_err_dmar_iova_overflow(iova
);
709 return -VTD_FR_ADDR_BEYOND_MGAW
;
712 /* FIXME: what is the Atomics request here? */
713 access_right_check
= is_write
? VTD_SL_W
: VTD_SL_R
;
716 offset
= vtd_iova_level_offset(iova
, level
);
717 slpte
= vtd_get_slpte(addr
, offset
);
719 if (slpte
== (uint64_t)-1) {
720 trace_vtd_err_dmar_slpte_read_error(iova
, level
);
721 if (level
== vtd_ce_get_level(ce
)) {
722 /* Invalid programming of context-entry */
723 return -VTD_FR_CONTEXT_ENTRY_INV
;
725 return -VTD_FR_PAGING_ENTRY_INV
;
728 *reads
= (*reads
) && (slpte
& VTD_SL_R
);
729 *writes
= (*writes
) && (slpte
& VTD_SL_W
);
730 if (!(slpte
& access_right_check
)) {
731 trace_vtd_err_dmar_slpte_perm_error(iova
, level
, slpte
, is_write
);
732 return is_write
? -VTD_FR_WRITE
: -VTD_FR_READ
;
734 if (vtd_slpte_nonzero_rsvd(slpte
, level
)) {
735 trace_vtd_err_dmar_slpte_resv_error(iova
, level
, slpte
);
736 return -VTD_FR_PAGING_ENTRY_RSVD
;
739 if (vtd_is_last_slpte(slpte
, level
)) {
741 *slpte_level
= level
;
744 addr
= vtd_get_slpte_addr(slpte
, aw_bits
);
749 typedef int (*vtd_page_walk_hook
)(IOMMUTLBEntry
*entry
, void *private);
751 static int vtd_page_walk_one(IOMMUTLBEntry
*entry
, int level
,
752 vtd_page_walk_hook hook_fn
, void *private)
755 trace_vtd_page_walk_one(level
, entry
->iova
, entry
->translated_addr
,
756 entry
->addr_mask
, entry
->perm
);
757 return hook_fn(entry
, private);
761 * vtd_page_walk_level - walk over specific level for IOVA range
763 * @addr: base GPA addr to start the walk
764 * @start: IOVA range start address
765 * @end: IOVA range end address (start <= addr < end)
766 * @hook_fn: hook func to be called when detected page
767 * @private: private data to be passed into hook func
768 * @read: whether parent level has read permission
769 * @write: whether parent level has write permission
770 * @notify_unmap: whether we should notify invalid entries
771 * @aw: maximum address width
773 static int vtd_page_walk_level(dma_addr_t addr
, uint64_t start
,
774 uint64_t end
, vtd_page_walk_hook hook_fn
,
775 void *private, uint32_t level
, bool read
,
776 bool write
, bool notify_unmap
, uint8_t aw
)
778 bool read_cur
, write_cur
, entry_valid
;
781 uint64_t subpage_size
, subpage_mask
;
783 uint64_t iova
= start
;
787 trace_vtd_page_walk_level(addr
, level
, start
, end
);
789 subpage_size
= 1ULL << vtd_slpt_level_shift(level
);
790 subpage_mask
= vtd_slpt_level_page_mask(level
);
793 iova_next
= (iova
& subpage_mask
) + subpage_size
;
795 offset
= vtd_iova_level_offset(iova
, level
);
796 slpte
= vtd_get_slpte(addr
, offset
);
798 if (slpte
== (uint64_t)-1) {
799 trace_vtd_page_walk_skip_read(iova
, iova_next
);
803 if (vtd_slpte_nonzero_rsvd(slpte
, level
)) {
804 trace_vtd_page_walk_skip_reserve(iova
, iova_next
);
808 /* Permissions are stacked with parents' */
809 read_cur
= read
&& (slpte
& VTD_SL_R
);
810 write_cur
= write
&& (slpte
& VTD_SL_W
);
813 * As long as we have either read/write permission, this is a
814 * valid entry. The rule works for both page entries and page
817 entry_valid
= read_cur
| write_cur
;
819 entry
.target_as
= &address_space_memory
;
820 entry
.iova
= iova
& subpage_mask
;
821 entry
.perm
= IOMMU_ACCESS_FLAG(read_cur
, write_cur
);
822 entry
.addr_mask
= ~subpage_mask
;
824 if (vtd_is_last_slpte(slpte
, level
)) {
825 /* NOTE: this is only meaningful if entry_valid == true */
826 entry
.translated_addr
= vtd_get_slpte_addr(slpte
, aw
);
827 if (!entry_valid
&& !notify_unmap
) {
828 trace_vtd_page_walk_skip_perm(iova
, iova_next
);
831 ret
= vtd_page_walk_one(&entry
, level
, hook_fn
, private);
839 * The whole entry is invalid; unmap it all.
840 * Translated address is meaningless, zero it.
842 entry
.translated_addr
= 0x0;
843 ret
= vtd_page_walk_one(&entry
, level
, hook_fn
, private);
848 trace_vtd_page_walk_skip_perm(iova
, iova_next
);
852 ret
= vtd_page_walk_level(vtd_get_slpte_addr(slpte
, aw
), iova
,
853 MIN(iova_next
, end
), hook_fn
, private,
854 level
- 1, read_cur
, write_cur
,
869 * vtd_page_walk - walk specific IOVA range, and call the hook
871 * @ce: context entry to walk upon
872 * @start: IOVA address to start the walk
873 * @end: IOVA range end address (start <= addr < end)
874 * @hook_fn: the hook that to be called for each detected area
875 * @private: private data for the hook function
876 * @aw: maximum address width
878 static int vtd_page_walk(VTDContextEntry
*ce
, uint64_t start
, uint64_t end
,
879 vtd_page_walk_hook hook_fn
, void *private,
880 bool notify_unmap
, uint8_t aw
)
882 dma_addr_t addr
= vtd_ce_get_slpt_base(ce
);
883 uint32_t level
= vtd_ce_get_level(ce
);
885 if (!vtd_iova_range_check(start
, ce
, aw
)) {
886 return -VTD_FR_ADDR_BEYOND_MGAW
;
889 if (!vtd_iova_range_check(end
, ce
, aw
)) {
890 /* Fix end so that it reaches the maximum */
891 end
= vtd_iova_limit(ce
, aw
);
894 return vtd_page_walk_level(addr
, start
, end
, hook_fn
, private,
895 level
, true, true, notify_unmap
, aw
);
898 /* Map a device to its corresponding domain (context-entry) */
899 static int vtd_dev_to_context_entry(IntelIOMMUState
*s
, uint8_t bus_num
,
900 uint8_t devfn
, VTDContextEntry
*ce
)
904 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
906 ret_fr
= vtd_get_root_entry(s
, bus_num
, &re
);
911 if (!vtd_root_entry_present(&re
)) {
912 /* Not error - it's okay we don't have root entry. */
913 trace_vtd_re_not_present(bus_num
);
914 return -VTD_FR_ROOT_ENTRY_P
;
917 if (re
.rsvd
|| (re
.val
& VTD_ROOT_ENTRY_RSVD(s
->aw_bits
))) {
918 trace_vtd_re_invalid(re
.rsvd
, re
.val
);
919 return -VTD_FR_ROOT_ENTRY_RSVD
;
922 ret_fr
= vtd_get_context_entry_from_root(&re
, devfn
, ce
);
927 if (!vtd_ce_present(ce
)) {
928 /* Not error - it's okay we don't have context entry. */
929 trace_vtd_ce_not_present(bus_num
, devfn
);
930 return -VTD_FR_CONTEXT_ENTRY_P
;
933 if ((ce
->hi
& VTD_CONTEXT_ENTRY_RSVD_HI
) ||
934 (ce
->lo
& VTD_CONTEXT_ENTRY_RSVD_LO(s
->aw_bits
))) {
935 trace_vtd_ce_invalid(ce
->hi
, ce
->lo
);
936 return -VTD_FR_CONTEXT_ENTRY_RSVD
;
939 /* Check if the programming of context-entry is valid */
940 if (!vtd_is_level_supported(s
, vtd_ce_get_level(ce
))) {
941 trace_vtd_ce_invalid(ce
->hi
, ce
->lo
);
942 return -VTD_FR_CONTEXT_ENTRY_INV
;
945 /* Do translation type check */
946 if (!vtd_ce_type_check(x86_iommu
, ce
)) {
947 trace_vtd_ce_invalid(ce
->hi
, ce
->lo
);
948 return -VTD_FR_CONTEXT_ENTRY_INV
;
955 * Fetch translation type for specific device. Returns <0 if error
956 * happens, otherwise return the shifted type to check against
959 static int vtd_dev_get_trans_type(VTDAddressSpace
*as
)
967 ret
= vtd_dev_to_context_entry(s
, pci_bus_num(as
->bus
),
973 return vtd_ce_get_type(&ce
);
976 static bool vtd_dev_pt_enabled(VTDAddressSpace
*as
)
982 ret
= vtd_dev_get_trans_type(as
);
985 * Possibly failed to parse the context entry for some reason
986 * (e.g., during init, or any guest configuration errors on
987 * context entries). We should assume PT not enabled for
993 return ret
== VTD_CONTEXT_TT_PASS_THROUGH
;
996 /* Return whether the device is using IOMMU translation. */
997 static bool vtd_switch_address_space(VTDAddressSpace
*as
)
1000 /* Whether we need to take the BQL on our own */
1001 bool take_bql
= !qemu_mutex_iothread_locked();
1005 use_iommu
= as
->iommu_state
->dmar_enabled
& !vtd_dev_pt_enabled(as
);
1007 trace_vtd_switch_address_space(pci_bus_num(as
->bus
),
1008 VTD_PCI_SLOT(as
->devfn
),
1009 VTD_PCI_FUNC(as
->devfn
),
1013 * It's possible that we reach here without BQL, e.g., when called
1014 * from vtd_pt_enable_fast_path(). However the memory APIs need
1015 * it. We'd better make sure we have had it already, or, take it.
1018 qemu_mutex_lock_iothread();
1021 /* Turn off first then on the other */
1023 memory_region_set_enabled(&as
->sys_alias
, false);
1024 memory_region_set_enabled(MEMORY_REGION(&as
->iommu
), true);
1026 memory_region_set_enabled(MEMORY_REGION(&as
->iommu
), false);
1027 memory_region_set_enabled(&as
->sys_alias
, true);
1031 qemu_mutex_unlock_iothread();
1037 static void vtd_switch_address_space_all(IntelIOMMUState
*s
)
1039 GHashTableIter iter
;
1043 g_hash_table_iter_init(&iter
, s
->vtd_as_by_busptr
);
1044 while (g_hash_table_iter_next(&iter
, NULL
, (void **)&vtd_bus
)) {
1045 for (i
= 0; i
< PCI_DEVFN_MAX
; i
++) {
1046 if (!vtd_bus
->dev_as
[i
]) {
1049 vtd_switch_address_space(vtd_bus
->dev_as
[i
]);
1054 static inline uint16_t vtd_make_source_id(uint8_t bus_num
, uint8_t devfn
)
1056 return ((bus_num
& 0xffUL
) << 8) | (devfn
& 0xffUL
);
1059 static const bool vtd_qualified_faults
[] = {
1060 [VTD_FR_RESERVED
] = false,
1061 [VTD_FR_ROOT_ENTRY_P
] = false,
1062 [VTD_FR_CONTEXT_ENTRY_P
] = true,
1063 [VTD_FR_CONTEXT_ENTRY_INV
] = true,
1064 [VTD_FR_ADDR_BEYOND_MGAW
] = true,
1065 [VTD_FR_WRITE
] = true,
1066 [VTD_FR_READ
] = true,
1067 [VTD_FR_PAGING_ENTRY_INV
] = true,
1068 [VTD_FR_ROOT_TABLE_INV
] = false,
1069 [VTD_FR_CONTEXT_TABLE_INV
] = false,
1070 [VTD_FR_ROOT_ENTRY_RSVD
] = false,
1071 [VTD_FR_PAGING_ENTRY_RSVD
] = true,
1072 [VTD_FR_CONTEXT_ENTRY_TT
] = true,
1073 [VTD_FR_RESERVED_ERR
] = false,
1074 [VTD_FR_MAX
] = false,
1077 /* To see if a fault condition is "qualified", which is reported to software
1078 * only if the FPD field in the context-entry used to process the faulting
1081 static inline bool vtd_is_qualified_fault(VTDFaultReason fault
)
1083 return vtd_qualified_faults
[fault
];
1086 static inline bool vtd_is_interrupt_addr(hwaddr addr
)
1088 return VTD_INTERRUPT_ADDR_FIRST
<= addr
&& addr
<= VTD_INTERRUPT_ADDR_LAST
;
1091 static void vtd_pt_enable_fast_path(IntelIOMMUState
*s
, uint16_t source_id
)
1094 VTDAddressSpace
*vtd_as
;
1095 bool success
= false;
1097 vtd_bus
= vtd_find_as_from_bus_num(s
, VTD_SID_TO_BUS(source_id
));
1102 vtd_as
= vtd_bus
->dev_as
[VTD_SID_TO_DEVFN(source_id
)];
1107 if (vtd_switch_address_space(vtd_as
) == false) {
1108 /* We switched off IOMMU region successfully. */
1113 trace_vtd_pt_enable_fast_path(source_id
, success
);
1116 /* Map dev to context-entry then do a paging-structures walk to do a iommu
1119 * Called from RCU critical section.
1121 * @bus_num: The bus number
1122 * @devfn: The devfn, which is the combined of device and function number
1123 * @is_write: The access is a write operation
1124 * @entry: IOMMUTLBEntry that contain the addr to be translated and result
1126 * Returns true if translation is successful, otherwise false.
1128 static bool vtd_do_iommu_translate(VTDAddressSpace
*vtd_as
, PCIBus
*bus
,
1129 uint8_t devfn
, hwaddr addr
, bool is_write
,
1130 IOMMUTLBEntry
*entry
)
1132 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
1134 uint8_t bus_num
= pci_bus_num(bus
);
1135 VTDContextCacheEntry
*cc_entry
;
1136 uint64_t slpte
, page_mask
;
1138 uint16_t source_id
= vtd_make_source_id(bus_num
, devfn
);
1140 bool is_fpd_set
= false;
1143 uint8_t access_flags
;
1144 VTDIOTLBEntry
*iotlb_entry
;
1147 * We have standalone memory region for interrupt addresses, we
1148 * should never receive translation requests in this region.
1150 assert(!vtd_is_interrupt_addr(addr
));
1154 cc_entry
= &vtd_as
->context_cache_entry
;
1156 /* Try to fetch slpte form IOTLB */
1157 iotlb_entry
= vtd_lookup_iotlb(s
, source_id
, addr
);
1159 trace_vtd_iotlb_page_hit(source_id
, addr
, iotlb_entry
->slpte
,
1160 iotlb_entry
->domain_id
);
1161 slpte
= iotlb_entry
->slpte
;
1162 access_flags
= iotlb_entry
->access_flags
;
1163 page_mask
= iotlb_entry
->mask
;
1167 /* Try to fetch context-entry from cache first */
1168 if (cc_entry
->context_cache_gen
== s
->context_cache_gen
) {
1169 trace_vtd_iotlb_cc_hit(bus_num
, devfn
, cc_entry
->context_entry
.hi
,
1170 cc_entry
->context_entry
.lo
,
1171 cc_entry
->context_cache_gen
);
1172 ce
= cc_entry
->context_entry
;
1173 is_fpd_set
= ce
.lo
& VTD_CONTEXT_ENTRY_FPD
;
1175 ret_fr
= vtd_dev_to_context_entry(s
, bus_num
, devfn
, &ce
);
1176 is_fpd_set
= ce
.lo
& VTD_CONTEXT_ENTRY_FPD
;
1179 if (is_fpd_set
&& vtd_is_qualified_fault(ret_fr
)) {
1180 trace_vtd_fault_disabled();
1182 vtd_report_dmar_fault(s
, source_id
, addr
, ret_fr
, is_write
);
1186 /* Update context-cache */
1187 trace_vtd_iotlb_cc_update(bus_num
, devfn
, ce
.hi
, ce
.lo
,
1188 cc_entry
->context_cache_gen
,
1189 s
->context_cache_gen
);
1190 cc_entry
->context_entry
= ce
;
1191 cc_entry
->context_cache_gen
= s
->context_cache_gen
;
1195 * We don't need to translate for pass-through context entries.
1196 * Also, let's ignore IOTLB caching as well for PT devices.
1198 if (vtd_ce_get_type(&ce
) == VTD_CONTEXT_TT_PASS_THROUGH
) {
1199 entry
->iova
= addr
& VTD_PAGE_MASK_4K
;
1200 entry
->translated_addr
= entry
->iova
;
1201 entry
->addr_mask
= ~VTD_PAGE_MASK_4K
;
1202 entry
->perm
= IOMMU_RW
;
1203 trace_vtd_translate_pt(source_id
, entry
->iova
);
1206 * When this happens, it means firstly caching-mode is not
1207 * enabled, and this is the first passthrough translation for
1208 * the device. Let's enable the fast path for passthrough.
1210 * When passthrough is disabled again for the device, we can
1211 * capture it via the context entry invalidation, then the
1212 * IOMMU region can be swapped back.
1214 vtd_pt_enable_fast_path(s
, source_id
);
1215 vtd_iommu_unlock(s
);
1219 ret_fr
= vtd_iova_to_slpte(&ce
, addr
, is_write
, &slpte
, &level
,
1220 &reads
, &writes
, s
->aw_bits
);
1223 if (is_fpd_set
&& vtd_is_qualified_fault(ret_fr
)) {
1224 trace_vtd_fault_disabled();
1226 vtd_report_dmar_fault(s
, source_id
, addr
, ret_fr
, is_write
);
1231 page_mask
= vtd_slpt_level_page_mask(level
);
1232 access_flags
= IOMMU_ACCESS_FLAG(reads
, writes
);
1233 vtd_update_iotlb(s
, source_id
, VTD_CONTEXT_ENTRY_DID(ce
.hi
), addr
, slpte
,
1234 access_flags
, level
);
1236 vtd_iommu_unlock(s
);
1237 entry
->iova
= addr
& page_mask
;
1238 entry
->translated_addr
= vtd_get_slpte_addr(slpte
, s
->aw_bits
) & page_mask
;
1239 entry
->addr_mask
= ~page_mask
;
1240 entry
->perm
= access_flags
;
1244 vtd_iommu_unlock(s
);
1246 entry
->translated_addr
= 0;
1247 entry
->addr_mask
= 0;
1248 entry
->perm
= IOMMU_NONE
;
1252 static void vtd_root_table_setup(IntelIOMMUState
*s
)
1254 s
->root
= vtd_get_quad_raw(s
, DMAR_RTADDR_REG
);
1255 s
->root_extended
= s
->root
& VTD_RTADDR_RTT
;
1256 s
->root
&= VTD_RTADDR_ADDR_MASK(s
->aw_bits
);
1258 trace_vtd_reg_dmar_root(s
->root
, s
->root_extended
);
1261 static void vtd_iec_notify_all(IntelIOMMUState
*s
, bool global
,
1262 uint32_t index
, uint32_t mask
)
1264 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s
), global
, index
, mask
);
1267 static void vtd_interrupt_remap_table_setup(IntelIOMMUState
*s
)
1270 value
= vtd_get_quad_raw(s
, DMAR_IRTA_REG
);
1271 s
->intr_size
= 1UL << ((value
& VTD_IRTA_SIZE_MASK
) + 1);
1272 s
->intr_root
= value
& VTD_IRTA_ADDR_MASK(s
->aw_bits
);
1273 s
->intr_eime
= value
& VTD_IRTA_EIME
;
1275 /* Notify global invalidation */
1276 vtd_iec_notify_all(s
, true, 0, 0);
1278 trace_vtd_reg_ir_root(s
->intr_root
, s
->intr_size
);
1281 static void vtd_iommu_replay_all(IntelIOMMUState
*s
)
1283 VTDAddressSpace
*vtd_as
;
1285 QLIST_FOREACH(vtd_as
, &s
->vtd_as_with_notifiers
, next
) {
1286 memory_region_iommu_replay_all(&vtd_as
->iommu
);
1290 static void vtd_context_global_invalidate(IntelIOMMUState
*s
)
1292 trace_vtd_inv_desc_cc_global();
1293 /* Protects context cache */
1295 s
->context_cache_gen
++;
1296 if (s
->context_cache_gen
== VTD_CONTEXT_CACHE_GEN_MAX
) {
1297 vtd_reset_context_cache_locked(s
);
1299 vtd_iommu_unlock(s
);
1300 vtd_switch_address_space_all(s
);
1302 * From VT-d spec 6.5.2.1, a global context entry invalidation
1303 * should be followed by a IOTLB global invalidation, so we should
1304 * be safe even without this. Hoewever, let's replay the region as
1305 * well to be safer, and go back here when we need finer tunes for
1306 * VT-d emulation codes.
1308 vtd_iommu_replay_all(s
);
1311 /* Do a context-cache device-selective invalidation.
1312 * @func_mask: FM field after shifting
1314 static void vtd_context_device_invalidate(IntelIOMMUState
*s
,
1320 VTDAddressSpace
*vtd_as
;
1321 uint8_t bus_n
, devfn
;
1324 trace_vtd_inv_desc_cc_devices(source_id
, func_mask
);
1326 switch (func_mask
& 3) {
1328 mask
= 0; /* No bits in the SID field masked */
1331 mask
= 4; /* Mask bit 2 in the SID field */
1334 mask
= 6; /* Mask bit 2:1 in the SID field */
1337 mask
= 7; /* Mask bit 2:0 in the SID field */
1342 bus_n
= VTD_SID_TO_BUS(source_id
);
1343 vtd_bus
= vtd_find_as_from_bus_num(s
, bus_n
);
1345 devfn
= VTD_SID_TO_DEVFN(source_id
);
1346 for (devfn_it
= 0; devfn_it
< PCI_DEVFN_MAX
; ++devfn_it
) {
1347 vtd_as
= vtd_bus
->dev_as
[devfn_it
];
1348 if (vtd_as
&& ((devfn_it
& mask
) == (devfn
& mask
))) {
1349 trace_vtd_inv_desc_cc_device(bus_n
, VTD_PCI_SLOT(devfn_it
),
1350 VTD_PCI_FUNC(devfn_it
));
1352 vtd_as
->context_cache_entry
.context_cache_gen
= 0;
1353 vtd_iommu_unlock(s
);
1355 * Do switch address space when needed, in case if the
1356 * device passthrough bit is switched.
1358 vtd_switch_address_space(vtd_as
);
1360 * So a device is moving out of (or moving into) a
1361 * domain, a replay() suites here to notify all the
1362 * IOMMU_NOTIFIER_MAP registers about this change.
1363 * This won't bring bad even if we have no such
1364 * notifier registered - the IOMMU notification
1365 * framework will skip MAP notifications if that
1368 memory_region_iommu_replay_all(&vtd_as
->iommu
);
1374 /* Context-cache invalidation
1375 * Returns the Context Actual Invalidation Granularity.
1376 * @val: the content of the CCMD_REG
1378 static uint64_t vtd_context_cache_invalidate(IntelIOMMUState
*s
, uint64_t val
)
1381 uint64_t type
= val
& VTD_CCMD_CIRG_MASK
;
1384 case VTD_CCMD_DOMAIN_INVL
:
1386 case VTD_CCMD_GLOBAL_INVL
:
1387 caig
= VTD_CCMD_GLOBAL_INVL_A
;
1388 vtd_context_global_invalidate(s
);
1391 case VTD_CCMD_DEVICE_INVL
:
1392 caig
= VTD_CCMD_DEVICE_INVL_A
;
1393 vtd_context_device_invalidate(s
, VTD_CCMD_SID(val
), VTD_CCMD_FM(val
));
1397 trace_vtd_err("Context cache invalidate type error.");
1403 static void vtd_iotlb_global_invalidate(IntelIOMMUState
*s
)
1405 trace_vtd_inv_desc_iotlb_global();
1407 vtd_iommu_replay_all(s
);
1410 static void vtd_iotlb_domain_invalidate(IntelIOMMUState
*s
, uint16_t domain_id
)
1413 VTDAddressSpace
*vtd_as
;
1415 trace_vtd_inv_desc_iotlb_domain(domain_id
);
1418 g_hash_table_foreach_remove(s
->iotlb
, vtd_hash_remove_by_domain
,
1420 vtd_iommu_unlock(s
);
1422 QLIST_FOREACH(vtd_as
, &s
->vtd_as_with_notifiers
, next
) {
1423 if (!vtd_dev_to_context_entry(s
, pci_bus_num(vtd_as
->bus
),
1424 vtd_as
->devfn
, &ce
) &&
1425 domain_id
== VTD_CONTEXT_ENTRY_DID(ce
.hi
)) {
1426 memory_region_iommu_replay_all(&vtd_as
->iommu
);
1431 static int vtd_page_invalidate_notify_hook(IOMMUTLBEntry
*entry
,
1434 memory_region_notify_iommu((IOMMUMemoryRegion
*)private, *entry
);
1438 static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState
*s
,
1439 uint16_t domain_id
, hwaddr addr
,
1442 VTDAddressSpace
*vtd_as
;
1445 hwaddr size
= (1 << am
) * VTD_PAGE_SIZE
;
1447 QLIST_FOREACH(vtd_as
, &(s
->vtd_as_with_notifiers
), next
) {
1448 ret
= vtd_dev_to_context_entry(s
, pci_bus_num(vtd_as
->bus
),
1449 vtd_as
->devfn
, &ce
);
1450 if (!ret
&& domain_id
== VTD_CONTEXT_ENTRY_DID(ce
.hi
)) {
1451 if (vtd_as_has_map_notifier(vtd_as
)) {
1453 * As long as we have MAP notifications registered in
1454 * any of our IOMMU notifiers, we need to sync the
1455 * shadow page table.
1457 vtd_page_walk(&ce
, addr
, addr
+ size
,
1458 vtd_page_invalidate_notify_hook
,
1459 (void *)&vtd_as
->iommu
, true, s
->aw_bits
);
1462 * For UNMAP-only notifiers, we don't need to walk the
1463 * page tables. We just deliver the PSI down to
1464 * invalidate caches.
1466 IOMMUTLBEntry entry
= {
1467 .target_as
= &address_space_memory
,
1469 .translated_addr
= 0,
1470 .addr_mask
= size
- 1,
1473 memory_region_notify_iommu(&vtd_as
->iommu
, entry
);
1479 static void vtd_iotlb_page_invalidate(IntelIOMMUState
*s
, uint16_t domain_id
,
1480 hwaddr addr
, uint8_t am
)
1482 VTDIOTLBPageInvInfo info
;
1484 trace_vtd_inv_desc_iotlb_pages(domain_id
, addr
, am
);
1486 assert(am
<= VTD_MAMV
);
1487 info
.domain_id
= domain_id
;
1489 info
.mask
= ~((1 << am
) - 1);
1491 g_hash_table_foreach_remove(s
->iotlb
, vtd_hash_remove_by_page
, &info
);
1492 vtd_iommu_unlock(s
);
1493 vtd_iotlb_page_invalidate_notify(s
, domain_id
, addr
, am
);
1497 * Returns the IOTLB Actual Invalidation Granularity.
1498 * @val: the content of the IOTLB_REG
1500 static uint64_t vtd_iotlb_flush(IntelIOMMUState
*s
, uint64_t val
)
1503 uint64_t type
= val
& VTD_TLB_FLUSH_GRANU_MASK
;
1509 case VTD_TLB_GLOBAL_FLUSH
:
1510 iaig
= VTD_TLB_GLOBAL_FLUSH_A
;
1511 vtd_iotlb_global_invalidate(s
);
1514 case VTD_TLB_DSI_FLUSH
:
1515 domain_id
= VTD_TLB_DID(val
);
1516 iaig
= VTD_TLB_DSI_FLUSH_A
;
1517 vtd_iotlb_domain_invalidate(s
, domain_id
);
1520 case VTD_TLB_PSI_FLUSH
:
1521 domain_id
= VTD_TLB_DID(val
);
1522 addr
= vtd_get_quad_raw(s
, DMAR_IVA_REG
);
1523 am
= VTD_IVA_AM(addr
);
1524 addr
= VTD_IVA_ADDR(addr
);
1525 if (am
> VTD_MAMV
) {
1526 trace_vtd_err("IOTLB PSI flush: address mask overflow.");
1530 iaig
= VTD_TLB_PSI_FLUSH_A
;
1531 vtd_iotlb_page_invalidate(s
, domain_id
, addr
, am
);
1535 trace_vtd_err("IOTLB flush: invalid granularity.");
1541 static void vtd_fetch_inv_desc(IntelIOMMUState
*s
);
1543 static inline bool vtd_queued_inv_disable_check(IntelIOMMUState
*s
)
1545 return s
->qi_enabled
&& (s
->iq_tail
== s
->iq_head
) &&
1546 (s
->iq_last_desc_type
== VTD_INV_DESC_WAIT
);
1549 static void vtd_handle_gcmd_qie(IntelIOMMUState
*s
, bool en
)
1551 uint64_t iqa_val
= vtd_get_quad_raw(s
, DMAR_IQA_REG
);
1553 trace_vtd_inv_qi_enable(en
);
1556 s
->iq
= iqa_val
& VTD_IQA_IQA_MASK(s
->aw_bits
);
1557 /* 2^(x+8) entries */
1558 s
->iq_size
= 1UL << ((iqa_val
& VTD_IQA_QS
) + 8);
1559 s
->qi_enabled
= true;
1560 trace_vtd_inv_qi_setup(s
->iq
, s
->iq_size
);
1561 /* Ok - report back to driver */
1562 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_QIES
);
1564 if (s
->iq_tail
!= 0) {
1566 * This is a spec violation but Windows guests are known to set up
1567 * Queued Invalidation this way so we allow the write and process
1568 * Invalidation Descriptors right away.
1570 trace_vtd_warn_invalid_qi_tail(s
->iq_tail
);
1571 if (!(vtd_get_long_raw(s
, DMAR_FSTS_REG
) & VTD_FSTS_IQE
)) {
1572 vtd_fetch_inv_desc(s
);
1576 if (vtd_queued_inv_disable_check(s
)) {
1577 /* disable Queued Invalidation */
1578 vtd_set_quad_raw(s
, DMAR_IQH_REG
, 0);
1580 s
->qi_enabled
= false;
1581 /* Ok - report back to driver */
1582 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_QIES
, 0);
1584 trace_vtd_err_qi_disable(s
->iq_head
, s
->iq_tail
, s
->iq_last_desc_type
);
1589 /* Set Root Table Pointer */
1590 static void vtd_handle_gcmd_srtp(IntelIOMMUState
*s
)
1592 vtd_root_table_setup(s
);
1593 /* Ok - report back to driver */
1594 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_RTPS
);
1597 /* Set Interrupt Remap Table Pointer */
1598 static void vtd_handle_gcmd_sirtp(IntelIOMMUState
*s
)
1600 vtd_interrupt_remap_table_setup(s
);
1601 /* Ok - report back to driver */
1602 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_IRTPS
);
1605 /* Handle Translation Enable/Disable */
1606 static void vtd_handle_gcmd_te(IntelIOMMUState
*s
, bool en
)
1608 if (s
->dmar_enabled
== en
) {
1612 trace_vtd_dmar_enable(en
);
1615 s
->dmar_enabled
= true;
1616 /* Ok - report back to driver */
1617 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_TES
);
1619 s
->dmar_enabled
= false;
1621 /* Clear the index of Fault Recording Register */
1622 s
->next_frcd_reg
= 0;
1623 /* Ok - report back to driver */
1624 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_TES
, 0);
1627 vtd_switch_address_space_all(s
);
1630 /* Handle Interrupt Remap Enable/Disable */
1631 static void vtd_handle_gcmd_ire(IntelIOMMUState
*s
, bool en
)
1633 trace_vtd_ir_enable(en
);
1636 s
->intr_enabled
= true;
1637 /* Ok - report back to driver */
1638 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_IRES
);
1640 s
->intr_enabled
= false;
1641 /* Ok - report back to driver */
1642 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_IRES
, 0);
1646 /* Handle write to Global Command Register */
1647 static void vtd_handle_gcmd_write(IntelIOMMUState
*s
)
1649 uint32_t status
= vtd_get_long_raw(s
, DMAR_GSTS_REG
);
1650 uint32_t val
= vtd_get_long_raw(s
, DMAR_GCMD_REG
);
1651 uint32_t changed
= status
^ val
;
1653 trace_vtd_reg_write_gcmd(status
, val
);
1654 if (changed
& VTD_GCMD_TE
) {
1655 /* Translation enable/disable */
1656 vtd_handle_gcmd_te(s
, val
& VTD_GCMD_TE
);
1658 if (val
& VTD_GCMD_SRTP
) {
1659 /* Set/update the root-table pointer */
1660 vtd_handle_gcmd_srtp(s
);
1662 if (changed
& VTD_GCMD_QIE
) {
1663 /* Queued Invalidation Enable */
1664 vtd_handle_gcmd_qie(s
, val
& VTD_GCMD_QIE
);
1666 if (val
& VTD_GCMD_SIRTP
) {
1667 /* Set/update the interrupt remapping root-table pointer */
1668 vtd_handle_gcmd_sirtp(s
);
1670 if (changed
& VTD_GCMD_IRE
) {
1671 /* Interrupt remap enable/disable */
1672 vtd_handle_gcmd_ire(s
, val
& VTD_GCMD_IRE
);
1676 /* Handle write to Context Command Register */
1677 static void vtd_handle_ccmd_write(IntelIOMMUState
*s
)
1680 uint64_t val
= vtd_get_quad_raw(s
, DMAR_CCMD_REG
);
1682 /* Context-cache invalidation request */
1683 if (val
& VTD_CCMD_ICC
) {
1684 if (s
->qi_enabled
) {
1685 trace_vtd_err("Queued Invalidation enabled, "
1686 "should not use register-based invalidation");
1689 ret
= vtd_context_cache_invalidate(s
, val
);
1690 /* Invalidation completed. Change something to show */
1691 vtd_set_clear_mask_quad(s
, DMAR_CCMD_REG
, VTD_CCMD_ICC
, 0ULL);
1692 ret
= vtd_set_clear_mask_quad(s
, DMAR_CCMD_REG
, VTD_CCMD_CAIG_MASK
,
1697 /* Handle write to IOTLB Invalidation Register */
1698 static void vtd_handle_iotlb_write(IntelIOMMUState
*s
)
1701 uint64_t val
= vtd_get_quad_raw(s
, DMAR_IOTLB_REG
);
1703 /* IOTLB invalidation request */
1704 if (val
& VTD_TLB_IVT
) {
1705 if (s
->qi_enabled
) {
1706 trace_vtd_err("Queued Invalidation enabled, "
1707 "should not use register-based invalidation.");
1710 ret
= vtd_iotlb_flush(s
, val
);
1711 /* Invalidation completed. Change something to show */
1712 vtd_set_clear_mask_quad(s
, DMAR_IOTLB_REG
, VTD_TLB_IVT
, 0ULL);
1713 ret
= vtd_set_clear_mask_quad(s
, DMAR_IOTLB_REG
,
1714 VTD_TLB_FLUSH_GRANU_MASK_A
, ret
);
1718 /* Fetch an Invalidation Descriptor from the Invalidation Queue */
1719 static bool vtd_get_inv_desc(dma_addr_t base_addr
, uint32_t offset
,
1720 VTDInvDesc
*inv_desc
)
1722 dma_addr_t addr
= base_addr
+ offset
* sizeof(*inv_desc
);
1723 if (dma_memory_read(&address_space_memory
, addr
, inv_desc
,
1724 sizeof(*inv_desc
))) {
1725 trace_vtd_err("Read INV DESC failed.");
1730 inv_desc
->lo
= le64_to_cpu(inv_desc
->lo
);
1731 inv_desc
->hi
= le64_to_cpu(inv_desc
->hi
);
1735 static bool vtd_process_wait_desc(IntelIOMMUState
*s
, VTDInvDesc
*inv_desc
)
1737 if ((inv_desc
->hi
& VTD_INV_DESC_WAIT_RSVD_HI
) ||
1738 (inv_desc
->lo
& VTD_INV_DESC_WAIT_RSVD_LO
)) {
1739 trace_vtd_inv_desc_wait_invalid(inv_desc
->hi
, inv_desc
->lo
);
1742 if (inv_desc
->lo
& VTD_INV_DESC_WAIT_SW
) {
1744 uint32_t status_data
= (uint32_t)(inv_desc
->lo
>>
1745 VTD_INV_DESC_WAIT_DATA_SHIFT
);
1747 assert(!(inv_desc
->lo
& VTD_INV_DESC_WAIT_IF
));
1749 /* FIXME: need to be masked with HAW? */
1750 dma_addr_t status_addr
= inv_desc
->hi
;
1751 trace_vtd_inv_desc_wait_sw(status_addr
, status_data
);
1752 status_data
= cpu_to_le32(status_data
);
1753 if (dma_memory_write(&address_space_memory
, status_addr
, &status_data
,
1754 sizeof(status_data
))) {
1755 trace_vtd_inv_desc_wait_write_fail(inv_desc
->hi
, inv_desc
->lo
);
1758 } else if (inv_desc
->lo
& VTD_INV_DESC_WAIT_IF
) {
1759 /* Interrupt flag */
1760 vtd_generate_completion_event(s
);
1762 trace_vtd_inv_desc_wait_invalid(inv_desc
->hi
, inv_desc
->lo
);
1768 static bool vtd_process_context_cache_desc(IntelIOMMUState
*s
,
1769 VTDInvDesc
*inv_desc
)
1771 uint16_t sid
, fmask
;
1773 if ((inv_desc
->lo
& VTD_INV_DESC_CC_RSVD
) || inv_desc
->hi
) {
1774 trace_vtd_inv_desc_cc_invalid(inv_desc
->hi
, inv_desc
->lo
);
1777 switch (inv_desc
->lo
& VTD_INV_DESC_CC_G
) {
1778 case VTD_INV_DESC_CC_DOMAIN
:
1779 trace_vtd_inv_desc_cc_domain(
1780 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc
->lo
));
1782 case VTD_INV_DESC_CC_GLOBAL
:
1783 vtd_context_global_invalidate(s
);
1786 case VTD_INV_DESC_CC_DEVICE
:
1787 sid
= VTD_INV_DESC_CC_SID(inv_desc
->lo
);
1788 fmask
= VTD_INV_DESC_CC_FM(inv_desc
->lo
);
1789 vtd_context_device_invalidate(s
, sid
, fmask
);
1793 trace_vtd_inv_desc_cc_invalid(inv_desc
->hi
, inv_desc
->lo
);
1799 static bool vtd_process_iotlb_desc(IntelIOMMUState
*s
, VTDInvDesc
*inv_desc
)
1805 if ((inv_desc
->lo
& VTD_INV_DESC_IOTLB_RSVD_LO
) ||
1806 (inv_desc
->hi
& VTD_INV_DESC_IOTLB_RSVD_HI
)) {
1807 trace_vtd_inv_desc_iotlb_invalid(inv_desc
->hi
, inv_desc
->lo
);
1811 switch (inv_desc
->lo
& VTD_INV_DESC_IOTLB_G
) {
1812 case VTD_INV_DESC_IOTLB_GLOBAL
:
1813 vtd_iotlb_global_invalidate(s
);
1816 case VTD_INV_DESC_IOTLB_DOMAIN
:
1817 domain_id
= VTD_INV_DESC_IOTLB_DID(inv_desc
->lo
);
1818 vtd_iotlb_domain_invalidate(s
, domain_id
);
1821 case VTD_INV_DESC_IOTLB_PAGE
:
1822 domain_id
= VTD_INV_DESC_IOTLB_DID(inv_desc
->lo
);
1823 addr
= VTD_INV_DESC_IOTLB_ADDR(inv_desc
->hi
);
1824 am
= VTD_INV_DESC_IOTLB_AM(inv_desc
->hi
);
1825 if (am
> VTD_MAMV
) {
1826 trace_vtd_inv_desc_iotlb_invalid(inv_desc
->hi
, inv_desc
->lo
);
1829 vtd_iotlb_page_invalidate(s
, domain_id
, addr
, am
);
1833 trace_vtd_inv_desc_iotlb_invalid(inv_desc
->hi
, inv_desc
->lo
);
1839 static bool vtd_process_inv_iec_desc(IntelIOMMUState
*s
,
1840 VTDInvDesc
*inv_desc
)
1842 trace_vtd_inv_desc_iec(inv_desc
->iec
.granularity
,
1843 inv_desc
->iec
.index
,
1844 inv_desc
->iec
.index_mask
);
1846 vtd_iec_notify_all(s
, !inv_desc
->iec
.granularity
,
1847 inv_desc
->iec
.index
,
1848 inv_desc
->iec
.index_mask
);
1852 static bool vtd_process_device_iotlb_desc(IntelIOMMUState
*s
,
1853 VTDInvDesc
*inv_desc
)
1855 VTDAddressSpace
*vtd_dev_as
;
1856 IOMMUTLBEntry entry
;
1857 struct VTDBus
*vtd_bus
;
1865 addr
= VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc
->hi
);
1866 sid
= VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc
->lo
);
1869 size
= VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc
->hi
);
1871 if ((inv_desc
->lo
& VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO
) ||
1872 (inv_desc
->hi
& VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI
)) {
1873 trace_vtd_inv_desc_iotlb_invalid(inv_desc
->hi
, inv_desc
->lo
);
1877 vtd_bus
= vtd_find_as_from_bus_num(s
, bus_num
);
1882 vtd_dev_as
= vtd_bus
->dev_as
[devfn
];
1887 /* According to ATS spec table 2.4:
1888 * S = 0, bits 15:12 = xxxx range size: 4K
1889 * S = 1, bits 15:12 = xxx0 range size: 8K
1890 * S = 1, bits 15:12 = xx01 range size: 16K
1891 * S = 1, bits 15:12 = x011 range size: 32K
1892 * S = 1, bits 15:12 = 0111 range size: 64K
1896 sz
= (VTD_PAGE_SIZE
* 2) << cto64(addr
>> VTD_PAGE_SHIFT
);
1902 entry
.target_as
= &vtd_dev_as
->as
;
1903 entry
.addr_mask
= sz
- 1;
1905 entry
.perm
= IOMMU_NONE
;
1906 entry
.translated_addr
= 0;
1907 memory_region_notify_iommu(&vtd_dev_as
->iommu
, entry
);
1913 static bool vtd_process_inv_desc(IntelIOMMUState
*s
)
1915 VTDInvDesc inv_desc
;
1918 trace_vtd_inv_qi_head(s
->iq_head
);
1919 if (!vtd_get_inv_desc(s
->iq
, s
->iq_head
, &inv_desc
)) {
1920 s
->iq_last_desc_type
= VTD_INV_DESC_NONE
;
1923 desc_type
= inv_desc
.lo
& VTD_INV_DESC_TYPE
;
1924 /* FIXME: should update at first or at last? */
1925 s
->iq_last_desc_type
= desc_type
;
1927 switch (desc_type
) {
1928 case VTD_INV_DESC_CC
:
1929 trace_vtd_inv_desc("context-cache", inv_desc
.hi
, inv_desc
.lo
);
1930 if (!vtd_process_context_cache_desc(s
, &inv_desc
)) {
1935 case VTD_INV_DESC_IOTLB
:
1936 trace_vtd_inv_desc("iotlb", inv_desc
.hi
, inv_desc
.lo
);
1937 if (!vtd_process_iotlb_desc(s
, &inv_desc
)) {
1942 case VTD_INV_DESC_WAIT
:
1943 trace_vtd_inv_desc("wait", inv_desc
.hi
, inv_desc
.lo
);
1944 if (!vtd_process_wait_desc(s
, &inv_desc
)) {
1949 case VTD_INV_DESC_IEC
:
1950 trace_vtd_inv_desc("iec", inv_desc
.hi
, inv_desc
.lo
);
1951 if (!vtd_process_inv_iec_desc(s
, &inv_desc
)) {
1956 case VTD_INV_DESC_DEVICE
:
1957 trace_vtd_inv_desc("device", inv_desc
.hi
, inv_desc
.lo
);
1958 if (!vtd_process_device_iotlb_desc(s
, &inv_desc
)) {
1964 trace_vtd_inv_desc_invalid(inv_desc
.hi
, inv_desc
.lo
);
1968 if (s
->iq_head
== s
->iq_size
) {
1974 /* Try to fetch and process more Invalidation Descriptors */
1975 static void vtd_fetch_inv_desc(IntelIOMMUState
*s
)
1977 trace_vtd_inv_qi_fetch();
1979 if (s
->iq_tail
>= s
->iq_size
) {
1980 /* Detects an invalid Tail pointer */
1981 trace_vtd_err_qi_tail(s
->iq_tail
, s
->iq_size
);
1982 vtd_handle_inv_queue_error(s
);
1985 while (s
->iq_head
!= s
->iq_tail
) {
1986 if (!vtd_process_inv_desc(s
)) {
1987 /* Invalidation Queue Errors */
1988 vtd_handle_inv_queue_error(s
);
1991 /* Must update the IQH_REG in time */
1992 vtd_set_quad_raw(s
, DMAR_IQH_REG
,
1993 (((uint64_t)(s
->iq_head
)) << VTD_IQH_QH_SHIFT
) &
1998 /* Handle write to Invalidation Queue Tail Register */
1999 static void vtd_handle_iqt_write(IntelIOMMUState
*s
)
2001 uint64_t val
= vtd_get_quad_raw(s
, DMAR_IQT_REG
);
2003 s
->iq_tail
= VTD_IQT_QT(val
);
2004 trace_vtd_inv_qi_tail(s
->iq_tail
);
2006 if (s
->qi_enabled
&& !(vtd_get_long_raw(s
, DMAR_FSTS_REG
) & VTD_FSTS_IQE
)) {
2007 /* Process Invalidation Queue here */
2008 vtd_fetch_inv_desc(s
);
2012 static void vtd_handle_fsts_write(IntelIOMMUState
*s
)
2014 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
2015 uint32_t fectl_reg
= vtd_get_long_raw(s
, DMAR_FECTL_REG
);
2016 uint32_t status_fields
= VTD_FSTS_PFO
| VTD_FSTS_PPF
| VTD_FSTS_IQE
;
2018 if ((fectl_reg
& VTD_FECTL_IP
) && !(fsts_reg
& status_fields
)) {
2019 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
2020 trace_vtd_fsts_clear_ip();
2022 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation
2023 * Descriptors if there are any when Queued Invalidation is enabled?
2027 static void vtd_handle_fectl_write(IntelIOMMUState
*s
)
2030 /* FIXME: when software clears the IM field, check the IP field. But do we
2031 * need to compare the old value and the new value to conclude that
2032 * software clears the IM field? Or just check if the IM field is zero?
2034 fectl_reg
= vtd_get_long_raw(s
, DMAR_FECTL_REG
);
2036 trace_vtd_reg_write_fectl(fectl_reg
);
2038 if ((fectl_reg
& VTD_FECTL_IP
) && !(fectl_reg
& VTD_FECTL_IM
)) {
2039 vtd_generate_interrupt(s
, DMAR_FEADDR_REG
, DMAR_FEDATA_REG
);
2040 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
2044 static void vtd_handle_ics_write(IntelIOMMUState
*s
)
2046 uint32_t ics_reg
= vtd_get_long_raw(s
, DMAR_ICS_REG
);
2047 uint32_t iectl_reg
= vtd_get_long_raw(s
, DMAR_IECTL_REG
);
2049 if ((iectl_reg
& VTD_IECTL_IP
) && !(ics_reg
& VTD_ICS_IWC
)) {
2050 trace_vtd_reg_ics_clear_ip();
2051 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
2055 static void vtd_handle_iectl_write(IntelIOMMUState
*s
)
2058 /* FIXME: when software clears the IM field, check the IP field. But do we
2059 * need to compare the old value and the new value to conclude that
2060 * software clears the IM field? Or just check if the IM field is zero?
2062 iectl_reg
= vtd_get_long_raw(s
, DMAR_IECTL_REG
);
2064 trace_vtd_reg_write_iectl(iectl_reg
);
2066 if ((iectl_reg
& VTD_IECTL_IP
) && !(iectl_reg
& VTD_IECTL_IM
)) {
2067 vtd_generate_interrupt(s
, DMAR_IEADDR_REG
, DMAR_IEDATA_REG
);
2068 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
2072 static uint64_t vtd_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
2074 IntelIOMMUState
*s
= opaque
;
2077 trace_vtd_reg_read(addr
, size
);
2079 if (addr
+ size
> DMAR_REG_SIZE
) {
2080 trace_vtd_err("Read MMIO over range.");
2081 return (uint64_t)-1;
2085 /* Root Table Address Register, 64-bit */
2086 case DMAR_RTADDR_REG
:
2088 val
= s
->root
& ((1ULL << 32) - 1);
2094 case DMAR_RTADDR_REG_HI
:
2096 val
= s
->root
>> 32;
2099 /* Invalidation Queue Address Register, 64-bit */
2101 val
= s
->iq
| (vtd_get_quad(s
, DMAR_IQA_REG
) & VTD_IQA_QS
);
2103 val
= val
& ((1ULL << 32) - 1);
2107 case DMAR_IQA_REG_HI
:
2114 val
= vtd_get_long(s
, addr
);
2116 val
= vtd_get_quad(s
, addr
);
2123 static void vtd_mem_write(void *opaque
, hwaddr addr
,
2124 uint64_t val
, unsigned size
)
2126 IntelIOMMUState
*s
= opaque
;
2128 trace_vtd_reg_write(addr
, size
, val
);
2130 if (addr
+ size
> DMAR_REG_SIZE
) {
2131 trace_vtd_err("Write MMIO over range.");
2136 /* Global Command Register, 32-bit */
2138 vtd_set_long(s
, addr
, val
);
2139 vtd_handle_gcmd_write(s
);
2142 /* Context Command Register, 64-bit */
2145 vtd_set_long(s
, addr
, val
);
2147 vtd_set_quad(s
, addr
, val
);
2148 vtd_handle_ccmd_write(s
);
2152 case DMAR_CCMD_REG_HI
:
2154 vtd_set_long(s
, addr
, val
);
2155 vtd_handle_ccmd_write(s
);
2158 /* IOTLB Invalidation Register, 64-bit */
2159 case DMAR_IOTLB_REG
:
2161 vtd_set_long(s
, addr
, val
);
2163 vtd_set_quad(s
, addr
, val
);
2164 vtd_handle_iotlb_write(s
);
2168 case DMAR_IOTLB_REG_HI
:
2170 vtd_set_long(s
, addr
, val
);
2171 vtd_handle_iotlb_write(s
);
2174 /* Invalidate Address Register, 64-bit */
2177 vtd_set_long(s
, addr
, val
);
2179 vtd_set_quad(s
, addr
, val
);
2183 case DMAR_IVA_REG_HI
:
2185 vtd_set_long(s
, addr
, val
);
2188 /* Fault Status Register, 32-bit */
2191 vtd_set_long(s
, addr
, val
);
2192 vtd_handle_fsts_write(s
);
2195 /* Fault Event Control Register, 32-bit */
2196 case DMAR_FECTL_REG
:
2198 vtd_set_long(s
, addr
, val
);
2199 vtd_handle_fectl_write(s
);
2202 /* Fault Event Data Register, 32-bit */
2203 case DMAR_FEDATA_REG
:
2205 vtd_set_long(s
, addr
, val
);
2208 /* Fault Event Address Register, 32-bit */
2209 case DMAR_FEADDR_REG
:
2211 vtd_set_long(s
, addr
, val
);
2214 * While the register is 32-bit only, some guests (Xen...) write to
2217 vtd_set_quad(s
, addr
, val
);
2221 /* Fault Event Upper Address Register, 32-bit */
2222 case DMAR_FEUADDR_REG
:
2224 vtd_set_long(s
, addr
, val
);
2227 /* Protected Memory Enable Register, 32-bit */
2230 vtd_set_long(s
, addr
, val
);
2233 /* Root Table Address Register, 64-bit */
2234 case DMAR_RTADDR_REG
:
2236 vtd_set_long(s
, addr
, val
);
2238 vtd_set_quad(s
, addr
, val
);
2242 case DMAR_RTADDR_REG_HI
:
2244 vtd_set_long(s
, addr
, val
);
2247 /* Invalidation Queue Tail Register, 64-bit */
2250 vtd_set_long(s
, addr
, val
);
2252 vtd_set_quad(s
, addr
, val
);
2254 vtd_handle_iqt_write(s
);
2257 case DMAR_IQT_REG_HI
:
2259 vtd_set_long(s
, addr
, val
);
2260 /* 19:63 of IQT_REG is RsvdZ, do nothing here */
2263 /* Invalidation Queue Address Register, 64-bit */
2266 vtd_set_long(s
, addr
, val
);
2268 vtd_set_quad(s
, addr
, val
);
2272 case DMAR_IQA_REG_HI
:
2274 vtd_set_long(s
, addr
, val
);
2277 /* Invalidation Completion Status Register, 32-bit */
2280 vtd_set_long(s
, addr
, val
);
2281 vtd_handle_ics_write(s
);
2284 /* Invalidation Event Control Register, 32-bit */
2285 case DMAR_IECTL_REG
:
2287 vtd_set_long(s
, addr
, val
);
2288 vtd_handle_iectl_write(s
);
2291 /* Invalidation Event Data Register, 32-bit */
2292 case DMAR_IEDATA_REG
:
2294 vtd_set_long(s
, addr
, val
);
2297 /* Invalidation Event Address Register, 32-bit */
2298 case DMAR_IEADDR_REG
:
2300 vtd_set_long(s
, addr
, val
);
2303 /* Invalidation Event Upper Address Register, 32-bit */
2304 case DMAR_IEUADDR_REG
:
2306 vtd_set_long(s
, addr
, val
);
2309 /* Fault Recording Registers, 128-bit */
2310 case DMAR_FRCD_REG_0_0
:
2312 vtd_set_long(s
, addr
, val
);
2314 vtd_set_quad(s
, addr
, val
);
2318 case DMAR_FRCD_REG_0_1
:
2320 vtd_set_long(s
, addr
, val
);
2323 case DMAR_FRCD_REG_0_2
:
2325 vtd_set_long(s
, addr
, val
);
2327 vtd_set_quad(s
, addr
, val
);
2328 /* May clear bit 127 (Fault), update PPF */
2329 vtd_update_fsts_ppf(s
);
2333 case DMAR_FRCD_REG_0_3
:
2335 vtd_set_long(s
, addr
, val
);
2336 /* May clear bit 127 (Fault), update PPF */
2337 vtd_update_fsts_ppf(s
);
2342 vtd_set_long(s
, addr
, val
);
2344 vtd_set_quad(s
, addr
, val
);
2348 case DMAR_IRTA_REG_HI
:
2350 vtd_set_long(s
, addr
, val
);
2355 vtd_set_long(s
, addr
, val
);
2357 vtd_set_quad(s
, addr
, val
);
2362 static IOMMUTLBEntry
vtd_iommu_translate(IOMMUMemoryRegion
*iommu
, hwaddr addr
,
2363 IOMMUAccessFlags flag
)
2365 VTDAddressSpace
*vtd_as
= container_of(iommu
, VTDAddressSpace
, iommu
);
2366 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
2367 IOMMUTLBEntry iotlb
= {
2368 /* We'll fill in the rest later. */
2369 .target_as
= &address_space_memory
,
2373 if (likely(s
->dmar_enabled
)) {
2374 success
= vtd_do_iommu_translate(vtd_as
, vtd_as
->bus
, vtd_as
->devfn
,
2375 addr
, flag
& IOMMU_WO
, &iotlb
);
2377 /* DMAR disabled, passthrough, use 4k-page*/
2378 iotlb
.iova
= addr
& VTD_PAGE_MASK_4K
;
2379 iotlb
.translated_addr
= addr
& VTD_PAGE_MASK_4K
;
2380 iotlb
.addr_mask
= ~VTD_PAGE_MASK_4K
;
2381 iotlb
.perm
= IOMMU_RW
;
2385 if (likely(success
)) {
2386 trace_vtd_dmar_translate(pci_bus_num(vtd_as
->bus
),
2387 VTD_PCI_SLOT(vtd_as
->devfn
),
2388 VTD_PCI_FUNC(vtd_as
->devfn
),
2389 iotlb
.iova
, iotlb
.translated_addr
,
2392 trace_vtd_err_dmar_translate(pci_bus_num(vtd_as
->bus
),
2393 VTD_PCI_SLOT(vtd_as
->devfn
),
2394 VTD_PCI_FUNC(vtd_as
->devfn
),
2401 static void vtd_iommu_notify_flag_changed(IOMMUMemoryRegion
*iommu
,
2402 IOMMUNotifierFlag old
,
2403 IOMMUNotifierFlag
new)
2405 VTDAddressSpace
*vtd_as
= container_of(iommu
, VTDAddressSpace
, iommu
);
2406 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
2408 if (!s
->caching_mode
&& new & IOMMU_NOTIFIER_MAP
) {
2409 error_report("We need to set caching-mode=1 for intel-iommu to enable "
2410 "device assignment with IOMMU protection.");
2414 /* Update per-address-space notifier flags */
2415 vtd_as
->notifier_flags
= new;
2417 if (old
== IOMMU_NOTIFIER_NONE
) {
2418 QLIST_INSERT_HEAD(&s
->vtd_as_with_notifiers
, vtd_as
, next
);
2419 } else if (new == IOMMU_NOTIFIER_NONE
) {
2420 QLIST_REMOVE(vtd_as
, next
);
2424 static int vtd_post_load(void *opaque
, int version_id
)
2426 IntelIOMMUState
*iommu
= opaque
;
2429 * Memory regions are dynamically turned on/off depending on
2430 * context entry configurations from the guest. After migration,
2431 * we need to make sure the memory regions are still correct.
2433 vtd_switch_address_space_all(iommu
);
2438 static const VMStateDescription vtd_vmstate
= {
2439 .name
= "iommu-intel",
2441 .minimum_version_id
= 1,
2442 .priority
= MIG_PRI_IOMMU
,
2443 .post_load
= vtd_post_load
,
2444 .fields
= (VMStateField
[]) {
2445 VMSTATE_UINT64(root
, IntelIOMMUState
),
2446 VMSTATE_UINT64(intr_root
, IntelIOMMUState
),
2447 VMSTATE_UINT64(iq
, IntelIOMMUState
),
2448 VMSTATE_UINT32(intr_size
, IntelIOMMUState
),
2449 VMSTATE_UINT16(iq_head
, IntelIOMMUState
),
2450 VMSTATE_UINT16(iq_tail
, IntelIOMMUState
),
2451 VMSTATE_UINT16(iq_size
, IntelIOMMUState
),
2452 VMSTATE_UINT16(next_frcd_reg
, IntelIOMMUState
),
2453 VMSTATE_UINT8_ARRAY(csr
, IntelIOMMUState
, DMAR_REG_SIZE
),
2454 VMSTATE_UINT8(iq_last_desc_type
, IntelIOMMUState
),
2455 VMSTATE_BOOL(root_extended
, IntelIOMMUState
),
2456 VMSTATE_BOOL(dmar_enabled
, IntelIOMMUState
),
2457 VMSTATE_BOOL(qi_enabled
, IntelIOMMUState
),
2458 VMSTATE_BOOL(intr_enabled
, IntelIOMMUState
),
2459 VMSTATE_BOOL(intr_eime
, IntelIOMMUState
),
2460 VMSTATE_END_OF_LIST()
2464 static const MemoryRegionOps vtd_mem_ops
= {
2465 .read
= vtd_mem_read
,
2466 .write
= vtd_mem_write
,
2467 .endianness
= DEVICE_LITTLE_ENDIAN
,
2469 .min_access_size
= 4,
2470 .max_access_size
= 8,
2473 .min_access_size
= 4,
2474 .max_access_size
= 8,
2478 static Property vtd_properties
[] = {
2479 DEFINE_PROP_UINT32("version", IntelIOMMUState
, version
, 0),
2480 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState
, intr_eim
,
2482 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState
, buggy_eim
, false),
2483 DEFINE_PROP_UINT8("x-aw-bits", IntelIOMMUState
, aw_bits
,
2484 VTD_HOST_ADDRESS_WIDTH
),
2485 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState
, caching_mode
, FALSE
),
2486 DEFINE_PROP_END_OF_LIST(),
2489 /* Read IRTE entry with specific index */
2490 static int vtd_irte_get(IntelIOMMUState
*iommu
, uint16_t index
,
2491 VTD_IR_TableEntry
*entry
, uint16_t sid
)
2493 static const uint16_t vtd_svt_mask
[VTD_SQ_MAX
] = \
2494 {0xffff, 0xfffb, 0xfff9, 0xfff8};
2495 dma_addr_t addr
= 0x00;
2496 uint16_t mask
, source_id
;
2497 uint8_t bus
, bus_max
, bus_min
;
2499 addr
= iommu
->intr_root
+ index
* sizeof(*entry
);
2500 if (dma_memory_read(&address_space_memory
, addr
, entry
,
2502 trace_vtd_err("Memory read failed for IRTE.");
2503 return -VTD_FR_IR_ROOT_INVAL
;
2506 trace_vtd_ir_irte_get(index
, le64_to_cpu(entry
->data
[1]),
2507 le64_to_cpu(entry
->data
[0]));
2509 if (!entry
->irte
.present
) {
2510 trace_vtd_err_irte(index
, le64_to_cpu(entry
->data
[1]),
2511 le64_to_cpu(entry
->data
[0]));
2512 return -VTD_FR_IR_ENTRY_P
;
2515 if (entry
->irte
.__reserved_0
|| entry
->irte
.__reserved_1
||
2516 entry
->irte
.__reserved_2
) {
2517 trace_vtd_err_irte(index
, le64_to_cpu(entry
->data
[1]),
2518 le64_to_cpu(entry
->data
[0]));
2519 return -VTD_FR_IR_IRTE_RSVD
;
2522 if (sid
!= X86_IOMMU_SID_INVALID
) {
2523 /* Validate IRTE SID */
2524 source_id
= le32_to_cpu(entry
->irte
.source_id
);
2525 switch (entry
->irte
.sid_vtype
) {
2530 mask
= vtd_svt_mask
[entry
->irte
.sid_q
];
2531 if ((source_id
& mask
) != (sid
& mask
)) {
2532 trace_vtd_err_irte_sid(index
, sid
, source_id
);
2533 return -VTD_FR_IR_SID_ERR
;
2538 bus_max
= source_id
>> 8;
2539 bus_min
= source_id
& 0xff;
2541 if (bus
> bus_max
|| bus
< bus_min
) {
2542 trace_vtd_err_irte_sid_bus(index
, bus
, bus_min
, bus_max
);
2543 return -VTD_FR_IR_SID_ERR
;
2548 trace_vtd_err_irte_svt(index
, entry
->irte
.sid_vtype
);
2549 /* Take this as verification failure. */
2550 return -VTD_FR_IR_SID_ERR
;
2558 /* Fetch IRQ information of specific IR index */
2559 static int vtd_remap_irq_get(IntelIOMMUState
*iommu
, uint16_t index
,
2560 VTDIrq
*irq
, uint16_t sid
)
2562 VTD_IR_TableEntry irte
= {};
2565 ret
= vtd_irte_get(iommu
, index
, &irte
, sid
);
2570 irq
->trigger_mode
= irte
.irte
.trigger_mode
;
2571 irq
->vector
= irte
.irte
.vector
;
2572 irq
->delivery_mode
= irte
.irte
.delivery_mode
;
2573 irq
->dest
= le32_to_cpu(irte
.irte
.dest_id
);
2574 if (!iommu
->intr_eime
) {
2575 #define VTD_IR_APIC_DEST_MASK (0xff00ULL)
2576 #define VTD_IR_APIC_DEST_SHIFT (8)
2577 irq
->dest
= (irq
->dest
& VTD_IR_APIC_DEST_MASK
) >>
2578 VTD_IR_APIC_DEST_SHIFT
;
2580 irq
->dest_mode
= irte
.irte
.dest_mode
;
2581 irq
->redir_hint
= irte
.irte
.redir_hint
;
2583 trace_vtd_ir_remap(index
, irq
->trigger_mode
, irq
->vector
,
2584 irq
->delivery_mode
, irq
->dest
, irq
->dest_mode
);
2589 /* Generate one MSI message from VTDIrq info */
2590 static void vtd_generate_msi_message(VTDIrq
*irq
, MSIMessage
*msg_out
)
2592 VTD_MSIMessage msg
= {};
2594 /* Generate address bits */
2595 msg
.dest_mode
= irq
->dest_mode
;
2596 msg
.redir_hint
= irq
->redir_hint
;
2597 msg
.dest
= irq
->dest
;
2598 msg
.__addr_hi
= irq
->dest
& 0xffffff00;
2599 msg
.__addr_head
= cpu_to_le32(0xfee);
2600 /* Keep this from original MSI address bits */
2601 msg
.__not_used
= irq
->msi_addr_last_bits
;
2603 /* Generate data bits */
2604 msg
.vector
= irq
->vector
;
2605 msg
.delivery_mode
= irq
->delivery_mode
;
2607 msg
.trigger_mode
= irq
->trigger_mode
;
2609 msg_out
->address
= msg
.msi_addr
;
2610 msg_out
->data
= msg
.msi_data
;
2613 /* Interrupt remapping for MSI/MSI-X entry */
2614 static int vtd_interrupt_remap_msi(IntelIOMMUState
*iommu
,
2616 MSIMessage
*translated
,
2620 VTD_IR_MSIAddress addr
;
2624 assert(origin
&& translated
);
2626 trace_vtd_ir_remap_msi_req(origin
->address
, origin
->data
);
2628 if (!iommu
|| !iommu
->intr_enabled
) {
2629 memcpy(translated
, origin
, sizeof(*origin
));
2633 if (origin
->address
& VTD_MSI_ADDR_HI_MASK
) {
2634 trace_vtd_err("MSI address high 32 bits non-zero when "
2635 "Interrupt Remapping enabled.");
2636 return -VTD_FR_IR_REQ_RSVD
;
2639 addr
.data
= origin
->address
& VTD_MSI_ADDR_LO_MASK
;
2640 if (addr
.addr
.__head
!= 0xfee) {
2641 trace_vtd_err("MSI addr low 32 bit invalid.");
2642 return -VTD_FR_IR_REQ_RSVD
;
2645 /* This is compatible mode. */
2646 if (addr
.addr
.int_mode
!= VTD_IR_INT_FORMAT_REMAP
) {
2647 memcpy(translated
, origin
, sizeof(*origin
));
2651 index
= addr
.addr
.index_h
<< 15 | le16_to_cpu(addr
.addr
.index_l
);
2653 #define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
2654 #define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
2656 if (addr
.addr
.sub_valid
) {
2657 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */
2658 index
+= origin
->data
& VTD_IR_MSI_DATA_SUBHANDLE
;
2661 ret
= vtd_remap_irq_get(iommu
, index
, &irq
, sid
);
2666 if (addr
.addr
.sub_valid
) {
2667 trace_vtd_ir_remap_type("MSI");
2668 if (origin
->data
& VTD_IR_MSI_DATA_RESERVED
) {
2669 trace_vtd_err_ir_msi_invalid(sid
, origin
->address
, origin
->data
);
2670 return -VTD_FR_IR_REQ_RSVD
;
2673 uint8_t vector
= origin
->data
& 0xff;
2674 uint8_t trigger_mode
= (origin
->data
>> MSI_DATA_TRIGGER_SHIFT
) & 0x1;
2676 trace_vtd_ir_remap_type("IOAPIC");
2677 /* IOAPIC entry vector should be aligned with IRTE vector
2678 * (see vt-d spec 5.1.5.1). */
2679 if (vector
!= irq
.vector
) {
2680 trace_vtd_warn_ir_vector(sid
, index
, vector
, irq
.vector
);
2683 /* The Trigger Mode field must match the Trigger Mode in the IRTE.
2684 * (see vt-d spec 5.1.5.1). */
2685 if (trigger_mode
!= irq
.trigger_mode
) {
2686 trace_vtd_warn_ir_trigger(sid
, index
, trigger_mode
,
2692 * We'd better keep the last two bits, assuming that guest OS
2693 * might modify it. Keep it does not hurt after all.
2695 irq
.msi_addr_last_bits
= addr
.addr
.__not_care
;
2697 /* Translate VTDIrq to MSI message */
2698 vtd_generate_msi_message(&irq
, translated
);
2701 trace_vtd_ir_remap_msi(origin
->address
, origin
->data
,
2702 translated
->address
, translated
->data
);
2706 static int vtd_int_remap(X86IOMMUState
*iommu
, MSIMessage
*src
,
2707 MSIMessage
*dst
, uint16_t sid
)
2709 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu
),
2713 static MemTxResult
vtd_mem_ir_read(void *opaque
, hwaddr addr
,
2714 uint64_t *data
, unsigned size
,
2720 static MemTxResult
vtd_mem_ir_write(void *opaque
, hwaddr addr
,
2721 uint64_t value
, unsigned size
,
2725 MSIMessage from
= {}, to
= {};
2726 uint16_t sid
= X86_IOMMU_SID_INVALID
;
2728 from
.address
= (uint64_t) addr
+ VTD_INTERRUPT_ADDR_FIRST
;
2729 from
.data
= (uint32_t) value
;
2731 if (!attrs
.unspecified
) {
2732 /* We have explicit Source ID */
2733 sid
= attrs
.requester_id
;
2736 ret
= vtd_interrupt_remap_msi(opaque
, &from
, &to
, sid
);
2738 /* TODO: report error */
2739 /* Drop this interrupt */
2743 apic_get_class()->send_msi(&to
);
2748 static const MemoryRegionOps vtd_mem_ir_ops
= {
2749 .read_with_attrs
= vtd_mem_ir_read
,
2750 .write_with_attrs
= vtd_mem_ir_write
,
2751 .endianness
= DEVICE_LITTLE_ENDIAN
,
2753 .min_access_size
= 4,
2754 .max_access_size
= 4,
2757 .min_access_size
= 4,
2758 .max_access_size
= 4,
2762 VTDAddressSpace
*vtd_find_add_as(IntelIOMMUState
*s
, PCIBus
*bus
, int devfn
)
2764 uintptr_t key
= (uintptr_t)bus
;
2765 VTDBus
*vtd_bus
= g_hash_table_lookup(s
->vtd_as_by_busptr
, &key
);
2766 VTDAddressSpace
*vtd_dev_as
;
2770 uintptr_t *new_key
= g_malloc(sizeof(*new_key
));
2771 *new_key
= (uintptr_t)bus
;
2772 /* No corresponding free() */
2773 vtd_bus
= g_malloc0(sizeof(VTDBus
) + sizeof(VTDAddressSpace
*) * \
2776 g_hash_table_insert(s
->vtd_as_by_busptr
, new_key
, vtd_bus
);
2779 vtd_dev_as
= vtd_bus
->dev_as
[devfn
];
2782 snprintf(name
, sizeof(name
), "intel_iommu_devfn_%d", devfn
);
2783 vtd_bus
->dev_as
[devfn
] = vtd_dev_as
= g_malloc0(sizeof(VTDAddressSpace
));
2785 vtd_dev_as
->bus
= bus
;
2786 vtd_dev_as
->devfn
= (uint8_t)devfn
;
2787 vtd_dev_as
->iommu_state
= s
;
2788 vtd_dev_as
->context_cache_entry
.context_cache_gen
= 0;
2791 * Memory region relationships looks like (Address range shows
2792 * only lower 32 bits to make it short in length...):
2794 * |-----------------+-------------------+----------|
2795 * | Name | Address range | Priority |
2796 * |-----------------+-------------------+----------+
2797 * | vtd_root | 00000000-ffffffff | 0 |
2798 * | intel_iommu | 00000000-ffffffff | 1 |
2799 * | vtd_sys_alias | 00000000-ffffffff | 1 |
2800 * | intel_iommu_ir | fee00000-feefffff | 64 |
2801 * |-----------------+-------------------+----------|
2803 * We enable/disable DMAR by switching enablement for
2804 * vtd_sys_alias and intel_iommu regions. IR region is always
2807 memory_region_init_iommu(&vtd_dev_as
->iommu
, sizeof(vtd_dev_as
->iommu
),
2808 TYPE_INTEL_IOMMU_MEMORY_REGION
, OBJECT(s
),
2811 memory_region_init_alias(&vtd_dev_as
->sys_alias
, OBJECT(s
),
2812 "vtd_sys_alias", get_system_memory(),
2813 0, memory_region_size(get_system_memory()));
2814 memory_region_init_io(&vtd_dev_as
->iommu_ir
, OBJECT(s
),
2815 &vtd_mem_ir_ops
, s
, "intel_iommu_ir",
2816 VTD_INTERRUPT_ADDR_SIZE
);
2817 memory_region_init(&vtd_dev_as
->root
, OBJECT(s
),
2818 "vtd_root", UINT64_MAX
);
2819 memory_region_add_subregion_overlap(&vtd_dev_as
->root
,
2820 VTD_INTERRUPT_ADDR_FIRST
,
2821 &vtd_dev_as
->iommu_ir
, 64);
2822 address_space_init(&vtd_dev_as
->as
, &vtd_dev_as
->root
, name
);
2823 memory_region_add_subregion_overlap(&vtd_dev_as
->root
, 0,
2824 &vtd_dev_as
->sys_alias
, 1);
2825 memory_region_add_subregion_overlap(&vtd_dev_as
->root
, 0,
2826 MEMORY_REGION(&vtd_dev_as
->iommu
),
2828 vtd_switch_address_space(vtd_dev_as
);
2833 /* Unmap the whole range in the notifier's scope. */
2834 static void vtd_address_space_unmap(VTDAddressSpace
*as
, IOMMUNotifier
*n
)
2836 IOMMUTLBEntry entry
;
2838 hwaddr start
= n
->start
;
2839 hwaddr end
= n
->end
;
2840 IntelIOMMUState
*s
= as
->iommu_state
;
2843 * Note: all the codes in this function has a assumption that IOVA
2844 * bits are no more than VTD_MGAW bits (which is restricted by
2845 * VT-d spec), otherwise we need to consider overflow of 64 bits.
2848 if (end
> VTD_ADDRESS_SIZE(s
->aw_bits
)) {
2850 * Don't need to unmap regions that is bigger than the whole
2851 * VT-d supported address space size
2853 end
= VTD_ADDRESS_SIZE(s
->aw_bits
);
2856 assert(start
<= end
);
2859 if (ctpop64(size
) != 1) {
2861 * This size cannot format a correct mask. Let's enlarge it to
2862 * suite the minimum available mask.
2864 int n
= 64 - clz64(size
);
2865 if (n
> s
->aw_bits
) {
2866 /* should not happen, but in case it happens, limit it */
2872 entry
.target_as
= &address_space_memory
;
2873 /* Adjust iova for the size */
2874 entry
.iova
= n
->start
& ~(size
- 1);
2875 /* This field is meaningless for unmap */
2876 entry
.translated_addr
= 0;
2877 entry
.perm
= IOMMU_NONE
;
2878 entry
.addr_mask
= size
- 1;
2880 trace_vtd_as_unmap_whole(pci_bus_num(as
->bus
),
2881 VTD_PCI_SLOT(as
->devfn
),
2882 VTD_PCI_FUNC(as
->devfn
),
2885 memory_region_notify_one(n
, &entry
);
2888 static void vtd_address_space_unmap_all(IntelIOMMUState
*s
)
2890 VTDAddressSpace
*vtd_as
;
2893 QLIST_FOREACH(vtd_as
, &s
->vtd_as_with_notifiers
, next
) {
2894 IOMMU_NOTIFIER_FOREACH(n
, &vtd_as
->iommu
) {
2895 vtd_address_space_unmap(vtd_as
, n
);
2900 static int vtd_replay_hook(IOMMUTLBEntry
*entry
, void *private)
2902 memory_region_notify_one((IOMMUNotifier
*)private, entry
);
2906 static void vtd_iommu_replay(IOMMUMemoryRegion
*iommu_mr
, IOMMUNotifier
*n
)
2908 VTDAddressSpace
*vtd_as
= container_of(iommu_mr
, VTDAddressSpace
, iommu
);
2909 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
2910 uint8_t bus_n
= pci_bus_num(vtd_as
->bus
);
2914 * The replay can be triggered by either a invalidation or a newly
2915 * created entry. No matter what, we release existing mappings
2916 * (it means flushing caches for UNMAP-only registers).
2918 vtd_address_space_unmap(vtd_as
, n
);
2920 if (vtd_dev_to_context_entry(s
, bus_n
, vtd_as
->devfn
, &ce
) == 0) {
2921 trace_vtd_replay_ce_valid(bus_n
, PCI_SLOT(vtd_as
->devfn
),
2922 PCI_FUNC(vtd_as
->devfn
),
2923 VTD_CONTEXT_ENTRY_DID(ce
.hi
),
2925 if (vtd_as_has_map_notifier(vtd_as
)) {
2926 /* This is required only for MAP typed notifiers */
2927 vtd_page_walk(&ce
, 0, ~0ULL, vtd_replay_hook
, (void *)n
, false,
2931 trace_vtd_replay_ce_invalid(bus_n
, PCI_SLOT(vtd_as
->devfn
),
2932 PCI_FUNC(vtd_as
->devfn
));
2938 /* Do the initialization. It will also be called when reset, so pay
2939 * attention when adding new initialization stuff.
2941 static void vtd_init(IntelIOMMUState
*s
)
2943 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
2945 memset(s
->csr
, 0, DMAR_REG_SIZE
);
2946 memset(s
->wmask
, 0, DMAR_REG_SIZE
);
2947 memset(s
->w1cmask
, 0, DMAR_REG_SIZE
);
2948 memset(s
->womask
, 0, DMAR_REG_SIZE
);
2951 s
->root_extended
= false;
2952 s
->dmar_enabled
= false;
2957 s
->qi_enabled
= false;
2958 s
->iq_last_desc_type
= VTD_INV_DESC_NONE
;
2959 s
->next_frcd_reg
= 0;
2960 s
->cap
= VTD_CAP_FRO
| VTD_CAP_NFR
| VTD_CAP_ND
|
2961 VTD_CAP_MAMV
| VTD_CAP_PSI
| VTD_CAP_SLLPS
|
2962 VTD_CAP_SAGAW_39bit
| VTD_CAP_MGAW(s
->aw_bits
);
2963 if (s
->aw_bits
== VTD_HOST_AW_48BIT
) {
2964 s
->cap
|= VTD_CAP_SAGAW_48bit
;
2966 s
->ecap
= VTD_ECAP_QI
| VTD_ECAP_IRO
;
2969 * Rsvd field masks for spte
2971 vtd_paging_entry_rsvd_field
[0] = ~0ULL;
2972 vtd_paging_entry_rsvd_field
[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s
->aw_bits
);
2973 vtd_paging_entry_rsvd_field
[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s
->aw_bits
);
2974 vtd_paging_entry_rsvd_field
[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s
->aw_bits
);
2975 vtd_paging_entry_rsvd_field
[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s
->aw_bits
);
2976 vtd_paging_entry_rsvd_field
[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s
->aw_bits
);
2977 vtd_paging_entry_rsvd_field
[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s
->aw_bits
);
2978 vtd_paging_entry_rsvd_field
[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s
->aw_bits
);
2979 vtd_paging_entry_rsvd_field
[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s
->aw_bits
);
2981 if (x86_iommu
->intr_supported
) {
2982 s
->ecap
|= VTD_ECAP_IR
| VTD_ECAP_MHMV
;
2983 if (s
->intr_eim
== ON_OFF_AUTO_ON
) {
2984 s
->ecap
|= VTD_ECAP_EIM
;
2986 assert(s
->intr_eim
!= ON_OFF_AUTO_AUTO
);
2989 if (x86_iommu
->dt_supported
) {
2990 s
->ecap
|= VTD_ECAP_DT
;
2993 if (x86_iommu
->pt_supported
) {
2994 s
->ecap
|= VTD_ECAP_PT
;
2997 if (s
->caching_mode
) {
2998 s
->cap
|= VTD_CAP_CM
;
3002 vtd_reset_context_cache_locked(s
);
3003 vtd_reset_iotlb_locked(s
);
3004 vtd_iommu_unlock(s
);
3006 /* Define registers with default values and bit semantics */
3007 vtd_define_long(s
, DMAR_VER_REG
, 0x10UL
, 0, 0);
3008 vtd_define_quad(s
, DMAR_CAP_REG
, s
->cap
, 0, 0);
3009 vtd_define_quad(s
, DMAR_ECAP_REG
, s
->ecap
, 0, 0);
3010 vtd_define_long(s
, DMAR_GCMD_REG
, 0, 0xff800000UL
, 0);
3011 vtd_define_long_wo(s
, DMAR_GCMD_REG
, 0xff800000UL
);
3012 vtd_define_long(s
, DMAR_GSTS_REG
, 0, 0, 0);
3013 vtd_define_quad(s
, DMAR_RTADDR_REG
, 0, 0xfffffffffffff000ULL
, 0);
3014 vtd_define_quad(s
, DMAR_CCMD_REG
, 0, 0xe0000003ffffffffULL
, 0);
3015 vtd_define_quad_wo(s
, DMAR_CCMD_REG
, 0x3ffff0000ULL
);
3017 /* Advanced Fault Logging not supported */
3018 vtd_define_long(s
, DMAR_FSTS_REG
, 0, 0, 0x11UL
);
3019 vtd_define_long(s
, DMAR_FECTL_REG
, 0x80000000UL
, 0x80000000UL
, 0);
3020 vtd_define_long(s
, DMAR_FEDATA_REG
, 0, 0x0000ffffUL
, 0);
3021 vtd_define_long(s
, DMAR_FEADDR_REG
, 0, 0xfffffffcUL
, 0);
3023 /* Treated as RsvdZ when EIM in ECAP_REG is not supported
3024 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0);
3026 vtd_define_long(s
, DMAR_FEUADDR_REG
, 0, 0, 0);
3028 /* Treated as RO for implementations that PLMR and PHMR fields reported
3029 * as Clear in the CAP_REG.
3030 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0);
3032 vtd_define_long(s
, DMAR_PMEN_REG
, 0, 0, 0);
3034 vtd_define_quad(s
, DMAR_IQH_REG
, 0, 0, 0);
3035 vtd_define_quad(s
, DMAR_IQT_REG
, 0, 0x7fff0ULL
, 0);
3036 vtd_define_quad(s
, DMAR_IQA_REG
, 0, 0xfffffffffffff007ULL
, 0);
3037 vtd_define_long(s
, DMAR_ICS_REG
, 0, 0, 0x1UL
);
3038 vtd_define_long(s
, DMAR_IECTL_REG
, 0x80000000UL
, 0x80000000UL
, 0);
3039 vtd_define_long(s
, DMAR_IEDATA_REG
, 0, 0xffffffffUL
, 0);
3040 vtd_define_long(s
, DMAR_IEADDR_REG
, 0, 0xfffffffcUL
, 0);
3041 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */
3042 vtd_define_long(s
, DMAR_IEUADDR_REG
, 0, 0, 0);
3044 /* IOTLB registers */
3045 vtd_define_quad(s
, DMAR_IOTLB_REG
, 0, 0Xb003ffff00000000ULL
, 0);
3046 vtd_define_quad(s
, DMAR_IVA_REG
, 0, 0xfffffffffffff07fULL
, 0);
3047 vtd_define_quad_wo(s
, DMAR_IVA_REG
, 0xfffffffffffff07fULL
);
3049 /* Fault Recording Registers, 128-bit */
3050 vtd_define_quad(s
, DMAR_FRCD_REG_0_0
, 0, 0, 0);
3051 vtd_define_quad(s
, DMAR_FRCD_REG_0_2
, 0, 0, 0x8000000000000000ULL
);
3054 * Interrupt remapping registers.
3056 vtd_define_quad(s
, DMAR_IRTA_REG
, 0, 0xfffffffffffff80fULL
, 0);
3059 /* Should not reset address_spaces when reset because devices will still use
3060 * the address space they got at first (won't ask the bus again).
3062 static void vtd_reset(DeviceState
*dev
)
3064 IntelIOMMUState
*s
= INTEL_IOMMU_DEVICE(dev
);
3069 * When device reset, throw away all mappings and external caches
3071 vtd_address_space_unmap_all(s
);
3074 static AddressSpace
*vtd_host_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
3076 IntelIOMMUState
*s
= opaque
;
3077 VTDAddressSpace
*vtd_as
;
3079 assert(0 <= devfn
&& devfn
< PCI_DEVFN_MAX
);
3081 vtd_as
= vtd_find_add_as(s
, bus
, devfn
);
3085 static bool vtd_decide_config(IntelIOMMUState
*s
, Error
**errp
)
3087 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
3089 /* Currently Intel IOMMU IR only support "kernel-irqchip={off|split}" */
3090 if (x86_iommu
->intr_supported
&& kvm_irqchip_in_kernel() &&
3091 !kvm_irqchip_is_split()) {
3092 error_setg(errp
, "Intel Interrupt Remapping cannot work with "
3093 "kernel-irqchip=on, please use 'split|off'.");
3096 if (s
->intr_eim
== ON_OFF_AUTO_ON
&& !x86_iommu
->intr_supported
) {
3097 error_setg(errp
, "eim=on cannot be selected without intremap=on");
3101 if (s
->intr_eim
== ON_OFF_AUTO_AUTO
) {
3102 s
->intr_eim
= (kvm_irqchip_in_kernel() || s
->buggy_eim
)
3103 && x86_iommu
->intr_supported
?
3104 ON_OFF_AUTO_ON
: ON_OFF_AUTO_OFF
;
3106 if (s
->intr_eim
== ON_OFF_AUTO_ON
&& !s
->buggy_eim
) {
3107 if (!kvm_irqchip_in_kernel()) {
3108 error_setg(errp
, "eim=on requires accel=kvm,kernel-irqchip=split");
3111 if (!kvm_enable_x2apic()) {
3112 error_setg(errp
, "eim=on requires support on the KVM side"
3113 "(X2APIC_API, first shipped in v4.7)");
3118 /* Currently only address widths supported are 39 and 48 bits */
3119 if ((s
->aw_bits
!= VTD_HOST_AW_39BIT
) &&
3120 (s
->aw_bits
!= VTD_HOST_AW_48BIT
)) {
3121 error_setg(errp
, "Supported values for x-aw-bits are: %d, %d",
3122 VTD_HOST_AW_39BIT
, VTD_HOST_AW_48BIT
);
3129 static void vtd_realize(DeviceState
*dev
, Error
**errp
)
3131 MachineState
*ms
= MACHINE(qdev_get_machine());
3132 PCMachineState
*pcms
= PC_MACHINE(ms
);
3133 PCIBus
*bus
= pcms
->bus
;
3134 IntelIOMMUState
*s
= INTEL_IOMMU_DEVICE(dev
);
3135 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(dev
);
3137 x86_iommu
->type
= TYPE_INTEL
;
3139 if (!vtd_decide_config(s
, errp
)) {
3143 QLIST_INIT(&s
->vtd_as_with_notifiers
);
3144 qemu_mutex_init(&s
->iommu_lock
);
3145 memset(s
->vtd_as_by_bus_num
, 0, sizeof(s
->vtd_as_by_bus_num
));
3146 memory_region_init_io(&s
->csrmem
, OBJECT(s
), &vtd_mem_ops
, s
,
3147 "intel_iommu", DMAR_REG_SIZE
);
3148 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->csrmem
);
3149 /* No corresponding destroy */
3150 s
->iotlb
= g_hash_table_new_full(vtd_uint64_hash
, vtd_uint64_equal
,
3152 s
->vtd_as_by_busptr
= g_hash_table_new_full(vtd_uint64_hash
, vtd_uint64_equal
,
3155 sysbus_mmio_map(SYS_BUS_DEVICE(s
), 0, Q35_HOST_BRIDGE_IOMMU_ADDR
);
3156 pci_setup_iommu(bus
, vtd_host_dma_iommu
, dev
);
3157 /* Pseudo address space under root PCI bus. */
3158 pcms
->ioapic_as
= vtd_host_dma_iommu(bus
, s
, Q35_PSEUDO_DEVFN_IOAPIC
);
3161 static void vtd_class_init(ObjectClass
*klass
, void *data
)
3163 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3164 X86IOMMUClass
*x86_class
= X86_IOMMU_CLASS(klass
);
3166 dc
->reset
= vtd_reset
;
3167 dc
->vmsd
= &vtd_vmstate
;
3168 dc
->props
= vtd_properties
;
3169 dc
->hotpluggable
= false;
3170 x86_class
->realize
= vtd_realize
;
3171 x86_class
->int_remap
= vtd_int_remap
;
3172 /* Supported by the pc-q35-* machine types */
3173 dc
->user_creatable
= true;
3176 static const TypeInfo vtd_info
= {
3177 .name
= TYPE_INTEL_IOMMU_DEVICE
,
3178 .parent
= TYPE_X86_IOMMU_DEVICE
,
3179 .instance_size
= sizeof(IntelIOMMUState
),
3180 .class_init
= vtd_class_init
,
3183 static void vtd_iommu_memory_region_class_init(ObjectClass
*klass
,
3186 IOMMUMemoryRegionClass
*imrc
= IOMMU_MEMORY_REGION_CLASS(klass
);
3188 imrc
->translate
= vtd_iommu_translate
;
3189 imrc
->notify_flag_changed
= vtd_iommu_notify_flag_changed
;
3190 imrc
->replay
= vtd_iommu_replay
;
3193 static const TypeInfo vtd_iommu_memory_region_info
= {
3194 .parent
= TYPE_IOMMU_MEMORY_REGION
,
3195 .name
= TYPE_INTEL_IOMMU_MEMORY_REGION
,
3196 .class_init
= vtd_iommu_memory_region_class_init
,
3199 static void vtd_register_types(void)
3201 type_register_static(&vtd_info
);
3202 type_register_static(&vtd_iommu_memory_region_info
);
3205 type_init(vtd_register_types
)