hw/arm/armsse.c: Correct modelling of SSE-300 internal SRAMs
[qemu/ar7.git] / target / i386 / cpu.h
blobe6836393f71baee7599cfb3f0395e17d0f0f803f
1 /*
2 * i386 virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef I386_CPU_H
21 #define I386_CPU_H
23 #include "sysemu/tcg.h"
24 #include "cpu-qom.h"
25 #include "kvm/hyperv-proto.h"
26 #include "exec/cpu-defs.h"
27 #include "qapi/qapi-types-common.h"
29 /* The x86 has a strong memory model with some store-after-load re-ordering */
30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
32 #define KVM_HAVE_MCE_INJECTION 1
34 /* support for self modifying code even if the modified instruction is
35 close to the modifying instruction */
36 #define TARGET_HAS_PRECISE_SMC
38 #ifdef TARGET_X86_64
39 #define I386_ELF_MACHINE EM_X86_64
40 #define ELF_MACHINE_UNAME "x86_64"
41 #else
42 #define I386_ELF_MACHINE EM_386
43 #define ELF_MACHINE_UNAME "i686"
44 #endif
46 enum {
47 R_EAX = 0,
48 R_ECX = 1,
49 R_EDX = 2,
50 R_EBX = 3,
51 R_ESP = 4,
52 R_EBP = 5,
53 R_ESI = 6,
54 R_EDI = 7,
55 R_R8 = 8,
56 R_R9 = 9,
57 R_R10 = 10,
58 R_R11 = 11,
59 R_R12 = 12,
60 R_R13 = 13,
61 R_R14 = 14,
62 R_R15 = 15,
64 R_AL = 0,
65 R_CL = 1,
66 R_DL = 2,
67 R_BL = 3,
68 R_AH = 4,
69 R_CH = 5,
70 R_DH = 6,
71 R_BH = 7,
74 typedef enum X86Seg {
75 R_ES = 0,
76 R_CS = 1,
77 R_SS = 2,
78 R_DS = 3,
79 R_FS = 4,
80 R_GS = 5,
81 R_LDTR = 6,
82 R_TR = 7,
83 } X86Seg;
85 /* segment descriptor fields */
86 #define DESC_G_SHIFT 23
87 #define DESC_G_MASK (1 << DESC_G_SHIFT)
88 #define DESC_B_SHIFT 22
89 #define DESC_B_MASK (1 << DESC_B_SHIFT)
90 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
91 #define DESC_L_MASK (1 << DESC_L_SHIFT)
92 #define DESC_AVL_SHIFT 20
93 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
94 #define DESC_P_SHIFT 15
95 #define DESC_P_MASK (1 << DESC_P_SHIFT)
96 #define DESC_DPL_SHIFT 13
97 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
98 #define DESC_S_SHIFT 12
99 #define DESC_S_MASK (1 << DESC_S_SHIFT)
100 #define DESC_TYPE_SHIFT 8
101 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
102 #define DESC_A_MASK (1 << 8)
104 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
105 #define DESC_C_MASK (1 << 10) /* code: conforming */
106 #define DESC_R_MASK (1 << 9) /* code: readable */
108 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
109 #define DESC_W_MASK (1 << 9) /* data: writable */
111 #define DESC_TSS_BUSY_MASK (1 << 9)
113 /* eflags masks */
114 #define CC_C 0x0001
115 #define CC_P 0x0004
116 #define CC_A 0x0010
117 #define CC_Z 0x0040
118 #define CC_S 0x0080
119 #define CC_O 0x0800
121 #define TF_SHIFT 8
122 #define IOPL_SHIFT 12
123 #define VM_SHIFT 17
125 #define TF_MASK 0x00000100
126 #define IF_MASK 0x00000200
127 #define DF_MASK 0x00000400
128 #define IOPL_MASK 0x00003000
129 #define NT_MASK 0x00004000
130 #define RF_MASK 0x00010000
131 #define VM_MASK 0x00020000
132 #define AC_MASK 0x00040000
133 #define VIF_MASK 0x00080000
134 #define VIP_MASK 0x00100000
135 #define ID_MASK 0x00200000
137 /* hidden flags - used internally by qemu to represent additional cpu
138 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
139 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
140 positions to ease oring with eflags. */
141 /* current cpl */
142 #define HF_CPL_SHIFT 0
143 /* true if hardware interrupts must be disabled for next instruction */
144 #define HF_INHIBIT_IRQ_SHIFT 3
145 /* 16 or 32 segments */
146 #define HF_CS32_SHIFT 4
147 #define HF_SS32_SHIFT 5
148 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
149 #define HF_ADDSEG_SHIFT 6
150 /* copy of CR0.PE (protected mode) */
151 #define HF_PE_SHIFT 7
152 #define HF_TF_SHIFT 8 /* must be same as eflags */
153 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
154 #define HF_EM_SHIFT 10
155 #define HF_TS_SHIFT 11
156 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
157 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
158 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
159 #define HF_RF_SHIFT 16 /* must be same as eflags */
160 #define HF_VM_SHIFT 17 /* must be same as eflags */
161 #define HF_AC_SHIFT 18 /* must be same as eflags */
162 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
163 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
164 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */
165 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
166 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */
167 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */
168 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
169 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */
171 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
172 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
173 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
174 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
175 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
176 #define HF_PE_MASK (1 << HF_PE_SHIFT)
177 #define HF_TF_MASK (1 << HF_TF_SHIFT)
178 #define HF_MP_MASK (1 << HF_MP_SHIFT)
179 #define HF_EM_MASK (1 << HF_EM_SHIFT)
180 #define HF_TS_MASK (1 << HF_TS_SHIFT)
181 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
182 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
183 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
184 #define HF_RF_MASK (1 << HF_RF_SHIFT)
185 #define HF_VM_MASK (1 << HF_VM_SHIFT)
186 #define HF_AC_MASK (1 << HF_AC_SHIFT)
187 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
188 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
189 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
190 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
191 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
192 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
193 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
194 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
196 /* hflags2 */
198 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
199 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
200 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
201 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
202 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
203 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */
204 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */
205 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */
207 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
208 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
209 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
210 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
211 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
212 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
213 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
214 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)
216 #define CR0_PE_SHIFT 0
217 #define CR0_MP_SHIFT 1
219 #define CR0_PE_MASK (1U << 0)
220 #define CR0_MP_MASK (1U << 1)
221 #define CR0_EM_MASK (1U << 2)
222 #define CR0_TS_MASK (1U << 3)
223 #define CR0_ET_MASK (1U << 4)
224 #define CR0_NE_MASK (1U << 5)
225 #define CR0_WP_MASK (1U << 16)
226 #define CR0_AM_MASK (1U << 18)
227 #define CR0_PG_MASK (1U << 31)
229 #define CR4_VME_MASK (1U << 0)
230 #define CR4_PVI_MASK (1U << 1)
231 #define CR4_TSD_MASK (1U << 2)
232 #define CR4_DE_MASK (1U << 3)
233 #define CR4_PSE_MASK (1U << 4)
234 #define CR4_PAE_MASK (1U << 5)
235 #define CR4_MCE_MASK (1U << 6)
236 #define CR4_PGE_MASK (1U << 7)
237 #define CR4_PCE_MASK (1U << 8)
238 #define CR4_OSFXSR_SHIFT 9
239 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
240 #define CR4_OSXMMEXCPT_MASK (1U << 10)
241 #define CR4_LA57_MASK (1U << 12)
242 #define CR4_VMXE_MASK (1U << 13)
243 #define CR4_SMXE_MASK (1U << 14)
244 #define CR4_FSGSBASE_MASK (1U << 16)
245 #define CR4_PCIDE_MASK (1U << 17)
246 #define CR4_OSXSAVE_MASK (1U << 18)
247 #define CR4_SMEP_MASK (1U << 20)
248 #define CR4_SMAP_MASK (1U << 21)
249 #define CR4_PKE_MASK (1U << 22)
250 #define CR4_PKS_MASK (1U << 24)
252 #define DR6_BD (1 << 13)
253 #define DR6_BS (1 << 14)
254 #define DR6_BT (1 << 15)
255 #define DR6_FIXED_1 0xffff0ff0
257 #define DR7_GD (1 << 13)
258 #define DR7_TYPE_SHIFT 16
259 #define DR7_LEN_SHIFT 18
260 #define DR7_FIXED_1 0x00000400
261 #define DR7_GLOBAL_BP_MASK 0xaa
262 #define DR7_LOCAL_BP_MASK 0x55
263 #define DR7_MAX_BP 4
264 #define DR7_TYPE_BP_INST 0x0
265 #define DR7_TYPE_DATA_WR 0x1
266 #define DR7_TYPE_IO_RW 0x2
267 #define DR7_TYPE_DATA_RW 0x3
269 #define PG_PRESENT_BIT 0
270 #define PG_RW_BIT 1
271 #define PG_USER_BIT 2
272 #define PG_PWT_BIT 3
273 #define PG_PCD_BIT 4
274 #define PG_ACCESSED_BIT 5
275 #define PG_DIRTY_BIT 6
276 #define PG_PSE_BIT 7
277 #define PG_GLOBAL_BIT 8
278 #define PG_PSE_PAT_BIT 12
279 #define PG_PKRU_BIT 59
280 #define PG_NX_BIT 63
282 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
283 #define PG_RW_MASK (1 << PG_RW_BIT)
284 #define PG_USER_MASK (1 << PG_USER_BIT)
285 #define PG_PWT_MASK (1 << PG_PWT_BIT)
286 #define PG_PCD_MASK (1 << PG_PCD_BIT)
287 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
288 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
289 #define PG_PSE_MASK (1 << PG_PSE_BIT)
290 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
291 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
292 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
293 #define PG_HI_USER_MASK 0x7ff0000000000000LL
294 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
295 #define PG_NX_MASK (1ULL << PG_NX_BIT)
297 #define PG_ERROR_W_BIT 1
299 #define PG_ERROR_P_MASK 0x01
300 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
301 #define PG_ERROR_U_MASK 0x04
302 #define PG_ERROR_RSVD_MASK 0x08
303 #define PG_ERROR_I_D_MASK 0x10
304 #define PG_ERROR_PK_MASK 0x20
306 #define PG_MODE_PAE (1 << 0)
307 #define PG_MODE_LMA (1 << 1)
308 #define PG_MODE_NXE (1 << 2)
309 #define PG_MODE_PSE (1 << 3)
310 #define PG_MODE_LA57 (1 << 4)
311 #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)
313 /* Bits of CR4 that do not affect the NPT page format. */
314 #define PG_MODE_WP (1 << 16)
315 #define PG_MODE_PKE (1 << 17)
316 #define PG_MODE_PKS (1 << 18)
317 #define PG_MODE_SMEP (1 << 19)
319 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
320 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
321 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */
323 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
324 #define MCE_BANKS_DEF 10
326 #define MCG_CAP_BANKS_MASK 0xff
328 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
329 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
330 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
331 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */
333 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
335 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
336 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
337 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
338 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
339 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
340 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
341 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
342 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
343 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
345 /* MISC register defines */
346 #define MCM_ADDR_SEGOFF 0 /* segment offset */
347 #define MCM_ADDR_LINEAR 1 /* linear address */
348 #define MCM_ADDR_PHYS 2 /* physical address */
349 #define MCM_ADDR_MEM 3 /* memory address */
350 #define MCM_ADDR_GENERIC 7 /* generic */
352 #define MSR_IA32_TSC 0x10
353 #define MSR_IA32_APICBASE 0x1b
354 #define MSR_IA32_APICBASE_BSP (1<<8)
355 #define MSR_IA32_APICBASE_ENABLE (1<<11)
356 #define MSR_IA32_APICBASE_EXTD (1 << 10)
357 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
358 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
359 #define MSR_TSC_ADJUST 0x0000003b
360 #define MSR_IA32_SPEC_CTRL 0x48
361 #define MSR_VIRT_SSBD 0xc001011f
362 #define MSR_IA32_PRED_CMD 0x49
363 #define MSR_IA32_UCODE_REV 0x8b
364 #define MSR_IA32_CORE_CAPABILITY 0xcf
366 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
367 #define ARCH_CAP_TSX_CTRL_MSR (1<<7)
369 #define MSR_IA32_PERF_CAPABILITIES 0x345
371 #define MSR_IA32_TSX_CTRL 0x122
372 #define MSR_IA32_TSCDEADLINE 0x6e0
373 #define MSR_IA32_PKRS 0x6e1
375 #define FEATURE_CONTROL_LOCKED (1<<0)
376 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
377 #define FEATURE_CONTROL_LMCE (1<<20)
379 #define MSR_P6_PERFCTR0 0xc1
381 #define MSR_IA32_SMBASE 0x9e
382 #define MSR_SMI_COUNT 0x34
383 #define MSR_CORE_THREAD_COUNT 0x35
384 #define MSR_MTRRcap 0xfe
385 #define MSR_MTRRcap_VCNT 8
386 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
387 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
389 #define MSR_IA32_SYSENTER_CS 0x174
390 #define MSR_IA32_SYSENTER_ESP 0x175
391 #define MSR_IA32_SYSENTER_EIP 0x176
393 #define MSR_MCG_CAP 0x179
394 #define MSR_MCG_STATUS 0x17a
395 #define MSR_MCG_CTL 0x17b
396 #define MSR_MCG_EXT_CTL 0x4d0
398 #define MSR_P6_EVNTSEL0 0x186
400 #define MSR_IA32_PERF_STATUS 0x198
402 #define MSR_IA32_MISC_ENABLE 0x1a0
403 /* Indicates good rep/movs microcode on some processors: */
404 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
405 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
407 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
408 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
410 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
412 #define MSR_MTRRfix64K_00000 0x250
413 #define MSR_MTRRfix16K_80000 0x258
414 #define MSR_MTRRfix16K_A0000 0x259
415 #define MSR_MTRRfix4K_C0000 0x268
416 #define MSR_MTRRfix4K_C8000 0x269
417 #define MSR_MTRRfix4K_D0000 0x26a
418 #define MSR_MTRRfix4K_D8000 0x26b
419 #define MSR_MTRRfix4K_E0000 0x26c
420 #define MSR_MTRRfix4K_E8000 0x26d
421 #define MSR_MTRRfix4K_F0000 0x26e
422 #define MSR_MTRRfix4K_F8000 0x26f
424 #define MSR_PAT 0x277
426 #define MSR_MTRRdefType 0x2ff
428 #define MSR_CORE_PERF_FIXED_CTR0 0x309
429 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
430 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
431 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
432 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
433 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
434 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
436 #define MSR_MC0_CTL 0x400
437 #define MSR_MC0_STATUS 0x401
438 #define MSR_MC0_ADDR 0x402
439 #define MSR_MC0_MISC 0x403
441 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560
442 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561
443 #define MSR_IA32_RTIT_CTL 0x570
444 #define MSR_IA32_RTIT_STATUS 0x571
445 #define MSR_IA32_RTIT_CR3_MATCH 0x572
446 #define MSR_IA32_RTIT_ADDR0_A 0x580
447 #define MSR_IA32_RTIT_ADDR0_B 0x581
448 #define MSR_IA32_RTIT_ADDR1_A 0x582
449 #define MSR_IA32_RTIT_ADDR1_B 0x583
450 #define MSR_IA32_RTIT_ADDR2_A 0x584
451 #define MSR_IA32_RTIT_ADDR2_B 0x585
452 #define MSR_IA32_RTIT_ADDR3_A 0x586
453 #define MSR_IA32_RTIT_ADDR3_B 0x587
454 #define MAX_RTIT_ADDRS 8
456 #define MSR_EFER 0xc0000080
458 #define MSR_EFER_SCE (1 << 0)
459 #define MSR_EFER_LME (1 << 8)
460 #define MSR_EFER_LMA (1 << 10)
461 #define MSR_EFER_NXE (1 << 11)
462 #define MSR_EFER_SVME (1 << 12)
463 #define MSR_EFER_FFXSR (1 << 14)
465 #define MSR_STAR 0xc0000081
466 #define MSR_LSTAR 0xc0000082
467 #define MSR_CSTAR 0xc0000083
468 #define MSR_FMASK 0xc0000084
469 #define MSR_FSBASE 0xc0000100
470 #define MSR_GSBASE 0xc0000101
471 #define MSR_KERNELGSBASE 0xc0000102
472 #define MSR_TSC_AUX 0xc0000103
474 #define MSR_VM_HSAVE_PA 0xc0010117
476 #define MSR_IA32_BNDCFGS 0x00000d90
477 #define MSR_IA32_XSS 0x00000da0
478 #define MSR_IA32_UMWAIT_CONTROL 0xe1
480 #define MSR_IA32_VMX_BASIC 0x00000480
481 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
482 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
483 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
484 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
485 #define MSR_IA32_VMX_MISC 0x00000485
486 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
487 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
488 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
489 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
490 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
491 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
492 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
493 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
494 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
495 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
496 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
497 #define MSR_IA32_VMX_VMFUNC 0x00000491
499 #define XSTATE_FP_BIT 0
500 #define XSTATE_SSE_BIT 1
501 #define XSTATE_YMM_BIT 2
502 #define XSTATE_BNDREGS_BIT 3
503 #define XSTATE_BNDCSR_BIT 4
504 #define XSTATE_OPMASK_BIT 5
505 #define XSTATE_ZMM_Hi256_BIT 6
506 #define XSTATE_Hi16_ZMM_BIT 7
507 #define XSTATE_PKRU_BIT 9
509 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
510 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
511 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
512 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
513 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
514 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
515 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
516 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
517 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
519 /* CPUID feature words */
520 typedef enum FeatureWord {
521 FEAT_1_EDX, /* CPUID[1].EDX */
522 FEAT_1_ECX, /* CPUID[1].ECX */
523 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
524 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */
525 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */
526 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */
527 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
528 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
529 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
530 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
531 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
532 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
533 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */
534 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */
535 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */
536 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */
537 FEAT_HV_RECOMM_EAX, /* CPUID[4000_0004].EAX */
538 FEAT_HV_NESTED_EAX, /* CPUID[4000_000A].EAX */
539 FEAT_SVM, /* CPUID[8000_000A].EDX */
540 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
541 FEAT_6_EAX, /* CPUID[6].EAX */
542 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
543 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
544 FEAT_ARCH_CAPABILITIES,
545 FEAT_CORE_CAPABILITY,
546 FEAT_PERF_CAPABILITIES,
547 FEAT_VMX_PROCBASED_CTLS,
548 FEAT_VMX_SECONDARY_CTLS,
549 FEAT_VMX_PINBASED_CTLS,
550 FEAT_VMX_EXIT_CTLS,
551 FEAT_VMX_ENTRY_CTLS,
552 FEAT_VMX_MISC,
553 FEAT_VMX_EPT_VPID_CAPS,
554 FEAT_VMX_BASIC,
555 FEAT_VMX_VMFUNC,
556 FEAT_14_0_ECX,
557 FEATURE_WORDS,
558 } FeatureWord;
560 typedef uint64_t FeatureWordArray[FEATURE_WORDS];
562 /* cpuid_features bits */
563 #define CPUID_FP87 (1U << 0)
564 #define CPUID_VME (1U << 1)
565 #define CPUID_DE (1U << 2)
566 #define CPUID_PSE (1U << 3)
567 #define CPUID_TSC (1U << 4)
568 #define CPUID_MSR (1U << 5)
569 #define CPUID_PAE (1U << 6)
570 #define CPUID_MCE (1U << 7)
571 #define CPUID_CX8 (1U << 8)
572 #define CPUID_APIC (1U << 9)
573 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
574 #define CPUID_MTRR (1U << 12)
575 #define CPUID_PGE (1U << 13)
576 #define CPUID_MCA (1U << 14)
577 #define CPUID_CMOV (1U << 15)
578 #define CPUID_PAT (1U << 16)
579 #define CPUID_PSE36 (1U << 17)
580 #define CPUID_PN (1U << 18)
581 #define CPUID_CLFLUSH (1U << 19)
582 #define CPUID_DTS (1U << 21)
583 #define CPUID_ACPI (1U << 22)
584 #define CPUID_MMX (1U << 23)
585 #define CPUID_FXSR (1U << 24)
586 #define CPUID_SSE (1U << 25)
587 #define CPUID_SSE2 (1U << 26)
588 #define CPUID_SS (1U << 27)
589 #define CPUID_HT (1U << 28)
590 #define CPUID_TM (1U << 29)
591 #define CPUID_IA64 (1U << 30)
592 #define CPUID_PBE (1U << 31)
594 #define CPUID_EXT_SSE3 (1U << 0)
595 #define CPUID_EXT_PCLMULQDQ (1U << 1)
596 #define CPUID_EXT_DTES64 (1U << 2)
597 #define CPUID_EXT_MONITOR (1U << 3)
598 #define CPUID_EXT_DSCPL (1U << 4)
599 #define CPUID_EXT_VMX (1U << 5)
600 #define CPUID_EXT_SMX (1U << 6)
601 #define CPUID_EXT_EST (1U << 7)
602 #define CPUID_EXT_TM2 (1U << 8)
603 #define CPUID_EXT_SSSE3 (1U << 9)
604 #define CPUID_EXT_CID (1U << 10)
605 #define CPUID_EXT_FMA (1U << 12)
606 #define CPUID_EXT_CX16 (1U << 13)
607 #define CPUID_EXT_XTPR (1U << 14)
608 #define CPUID_EXT_PDCM (1U << 15)
609 #define CPUID_EXT_PCID (1U << 17)
610 #define CPUID_EXT_DCA (1U << 18)
611 #define CPUID_EXT_SSE41 (1U << 19)
612 #define CPUID_EXT_SSE42 (1U << 20)
613 #define CPUID_EXT_X2APIC (1U << 21)
614 #define CPUID_EXT_MOVBE (1U << 22)
615 #define CPUID_EXT_POPCNT (1U << 23)
616 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
617 #define CPUID_EXT_AES (1U << 25)
618 #define CPUID_EXT_XSAVE (1U << 26)
619 #define CPUID_EXT_OSXSAVE (1U << 27)
620 #define CPUID_EXT_AVX (1U << 28)
621 #define CPUID_EXT_F16C (1U << 29)
622 #define CPUID_EXT_RDRAND (1U << 30)
623 #define CPUID_EXT_HYPERVISOR (1U << 31)
625 #define CPUID_EXT2_FPU (1U << 0)
626 #define CPUID_EXT2_VME (1U << 1)
627 #define CPUID_EXT2_DE (1U << 2)
628 #define CPUID_EXT2_PSE (1U << 3)
629 #define CPUID_EXT2_TSC (1U << 4)
630 #define CPUID_EXT2_MSR (1U << 5)
631 #define CPUID_EXT2_PAE (1U << 6)
632 #define CPUID_EXT2_MCE (1U << 7)
633 #define CPUID_EXT2_CX8 (1U << 8)
634 #define CPUID_EXT2_APIC (1U << 9)
635 #define CPUID_EXT2_SYSCALL (1U << 11)
636 #define CPUID_EXT2_MTRR (1U << 12)
637 #define CPUID_EXT2_PGE (1U << 13)
638 #define CPUID_EXT2_MCA (1U << 14)
639 #define CPUID_EXT2_CMOV (1U << 15)
640 #define CPUID_EXT2_PAT (1U << 16)
641 #define CPUID_EXT2_PSE36 (1U << 17)
642 #define CPUID_EXT2_MP (1U << 19)
643 #define CPUID_EXT2_NX (1U << 20)
644 #define CPUID_EXT2_MMXEXT (1U << 22)
645 #define CPUID_EXT2_MMX (1U << 23)
646 #define CPUID_EXT2_FXSR (1U << 24)
647 #define CPUID_EXT2_FFXSR (1U << 25)
648 #define CPUID_EXT2_PDPE1GB (1U << 26)
649 #define CPUID_EXT2_RDTSCP (1U << 27)
650 #define CPUID_EXT2_LM (1U << 29)
651 #define CPUID_EXT2_3DNOWEXT (1U << 30)
652 #define CPUID_EXT2_3DNOW (1U << 31)
654 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
655 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
656 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
657 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
658 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
659 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
660 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
661 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
662 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
663 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
665 #define CPUID_EXT3_LAHF_LM (1U << 0)
666 #define CPUID_EXT3_CMP_LEG (1U << 1)
667 #define CPUID_EXT3_SVM (1U << 2)
668 #define CPUID_EXT3_EXTAPIC (1U << 3)
669 #define CPUID_EXT3_CR8LEG (1U << 4)
670 #define CPUID_EXT3_ABM (1U << 5)
671 #define CPUID_EXT3_SSE4A (1U << 6)
672 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
673 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
674 #define CPUID_EXT3_OSVW (1U << 9)
675 #define CPUID_EXT3_IBS (1U << 10)
676 #define CPUID_EXT3_XOP (1U << 11)
677 #define CPUID_EXT3_SKINIT (1U << 12)
678 #define CPUID_EXT3_WDT (1U << 13)
679 #define CPUID_EXT3_LWP (1U << 15)
680 #define CPUID_EXT3_FMA4 (1U << 16)
681 #define CPUID_EXT3_TCE (1U << 17)
682 #define CPUID_EXT3_NODEID (1U << 19)
683 #define CPUID_EXT3_TBM (1U << 21)
684 #define CPUID_EXT3_TOPOEXT (1U << 22)
685 #define CPUID_EXT3_PERFCORE (1U << 23)
686 #define CPUID_EXT3_PERFNB (1U << 24)
688 #define CPUID_SVM_NPT (1U << 0)
689 #define CPUID_SVM_LBRV (1U << 1)
690 #define CPUID_SVM_SVMLOCK (1U << 2)
691 #define CPUID_SVM_NRIPSAVE (1U << 3)
692 #define CPUID_SVM_TSCSCALE (1U << 4)
693 #define CPUID_SVM_VMCBCLEAN (1U << 5)
694 #define CPUID_SVM_FLUSHASID (1U << 6)
695 #define CPUID_SVM_DECODEASSIST (1U << 7)
696 #define CPUID_SVM_PAUSEFILTER (1U << 10)
697 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
698 #define CPUID_SVM_AVIC (1U << 13)
699 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
700 #define CPUID_SVM_VGIF (1U << 16)
701 #define CPUID_SVM_SVME_ADDR_CHK (1U << 28)
703 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
704 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
705 /* 1st Group of Advanced Bit Manipulation Extensions */
706 #define CPUID_7_0_EBX_BMI1 (1U << 3)
707 /* Hardware Lock Elision */
708 #define CPUID_7_0_EBX_HLE (1U << 4)
709 /* Intel Advanced Vector Extensions 2 */
710 #define CPUID_7_0_EBX_AVX2 (1U << 5)
711 /* Supervisor-mode Execution Prevention */
712 #define CPUID_7_0_EBX_SMEP (1U << 7)
713 /* 2nd Group of Advanced Bit Manipulation Extensions */
714 #define CPUID_7_0_EBX_BMI2 (1U << 8)
715 /* Enhanced REP MOVSB/STOSB */
716 #define CPUID_7_0_EBX_ERMS (1U << 9)
717 /* Invalidate Process-Context Identifier */
718 #define CPUID_7_0_EBX_INVPCID (1U << 10)
719 /* Restricted Transactional Memory */
720 #define CPUID_7_0_EBX_RTM (1U << 11)
721 /* Memory Protection Extension */
722 #define CPUID_7_0_EBX_MPX (1U << 14)
723 /* AVX-512 Foundation */
724 #define CPUID_7_0_EBX_AVX512F (1U << 16)
725 /* AVX-512 Doubleword & Quadword Instruction */
726 #define CPUID_7_0_EBX_AVX512DQ (1U << 17)
727 /* Read Random SEED */
728 #define CPUID_7_0_EBX_RDSEED (1U << 18)
729 /* ADCX and ADOX instructions */
730 #define CPUID_7_0_EBX_ADX (1U << 19)
731 /* Supervisor Mode Access Prevention */
732 #define CPUID_7_0_EBX_SMAP (1U << 20)
733 /* AVX-512 Integer Fused Multiply Add */
734 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
735 /* Persistent Commit */
736 #define CPUID_7_0_EBX_PCOMMIT (1U << 22)
737 /* Flush a Cache Line Optimized */
738 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
739 /* Cache Line Write Back */
740 #define CPUID_7_0_EBX_CLWB (1U << 24)
741 /* Intel Processor Trace */
742 #define CPUID_7_0_EBX_INTEL_PT (1U << 25)
743 /* AVX-512 Prefetch */
744 #define CPUID_7_0_EBX_AVX512PF (1U << 26)
745 /* AVX-512 Exponential and Reciprocal */
746 #define CPUID_7_0_EBX_AVX512ER (1U << 27)
747 /* AVX-512 Conflict Detection */
748 #define CPUID_7_0_EBX_AVX512CD (1U << 28)
749 /* SHA1/SHA256 Instruction Extensions */
750 #define CPUID_7_0_EBX_SHA_NI (1U << 29)
751 /* AVX-512 Byte and Word Instructions */
752 #define CPUID_7_0_EBX_AVX512BW (1U << 30)
753 /* AVX-512 Vector Length Extensions */
754 #define CPUID_7_0_EBX_AVX512VL (1U << 31)
756 /* AVX-512 Vector Byte Manipulation Instruction */
757 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
758 /* User-Mode Instruction Prevention */
759 #define CPUID_7_0_ECX_UMIP (1U << 2)
760 /* Protection Keys for User-mode Pages */
761 #define CPUID_7_0_ECX_PKU (1U << 3)
762 /* OS Enable Protection Keys */
763 #define CPUID_7_0_ECX_OSPKE (1U << 4)
764 /* UMONITOR/UMWAIT/TPAUSE Instructions */
765 #define CPUID_7_0_ECX_WAITPKG (1U << 5)
766 /* Additional AVX-512 Vector Byte Manipulation Instruction */
767 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
768 /* Galois Field New Instructions */
769 #define CPUID_7_0_ECX_GFNI (1U << 8)
770 /* Vector AES Instructions */
771 #define CPUID_7_0_ECX_VAES (1U << 9)
772 /* Carry-Less Multiplication Quadword */
773 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
774 /* Vector Neural Network Instructions */
775 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
776 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
777 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
778 /* POPCNT for vectors of DW/QW */
779 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
780 /* 5-level Page Tables */
781 #define CPUID_7_0_ECX_LA57 (1U << 16)
782 /* Read Processor ID */
783 #define CPUID_7_0_ECX_RDPID (1U << 22)
784 /* Bus Lock Debug Exception */
785 #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24)
786 /* Cache Line Demote Instruction */
787 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
788 /* Move Doubleword as Direct Store Instruction */
789 #define CPUID_7_0_ECX_MOVDIRI (1U << 27)
790 /* Move 64 Bytes as Direct Store Instruction */
791 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
792 /* Protection Keys for Supervisor-mode Pages */
793 #define CPUID_7_0_ECX_PKS (1U << 31)
795 /* AVX512 Neural Network Instructions */
796 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
797 /* AVX512 Multiply Accumulation Single Precision */
798 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
799 /* Fast Short Rep Mov */
800 #define CPUID_7_0_EDX_FSRM (1U << 4)
801 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */
802 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
803 /* SERIALIZE instruction */
804 #define CPUID_7_0_EDX_SERIALIZE (1U << 14)
805 /* TSX Suspend Load Address Tracking instruction */
806 #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
807 /* AVX512_FP16 instruction */
808 #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
809 /* Speculation Control */
810 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
811 /* Single Thread Indirect Branch Predictors */
812 #define CPUID_7_0_EDX_STIBP (1U << 27)
813 /* Arch Capabilities */
814 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
815 /* Core Capability */
816 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
817 /* Speculative Store Bypass Disable */
818 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
820 /* AVX512 BFloat16 Instruction */
821 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
823 /* Packets which contain IP payload have LIP values */
824 #define CPUID_14_0_ECX_LIP (1U << 31)
826 /* CLZERO instruction */
827 #define CPUID_8000_0008_EBX_CLZERO (1U << 0)
828 /* Always save/restore FP error pointers */
829 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
830 /* Write back and do not invalidate cache */
831 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
832 /* Indirect Branch Prediction Barrier */
833 #define CPUID_8000_0008_EBX_IBPB (1U << 12)
834 /* Indirect Branch Restricted Speculation */
835 #define CPUID_8000_0008_EBX_IBRS (1U << 14)
836 /* Single Thread Indirect Branch Predictors */
837 #define CPUID_8000_0008_EBX_STIBP (1U << 15)
838 /* Speculative Store Bypass Disable */
839 #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24)
841 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
842 #define CPUID_XSAVE_XSAVEC (1U << 1)
843 #define CPUID_XSAVE_XGETBV1 (1U << 2)
844 #define CPUID_XSAVE_XSAVES (1U << 3)
846 #define CPUID_6_EAX_ARAT (1U << 2)
848 /* CPUID[0x80000007].EDX flags: */
849 #define CPUID_APM_INVTSC (1U << 8)
851 #define CPUID_VENDOR_SZ 12
853 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
854 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
855 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
856 #define CPUID_VENDOR_INTEL "GenuineIntel"
858 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
859 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
860 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
861 #define CPUID_VENDOR_AMD "AuthenticAMD"
863 #define CPUID_VENDOR_VIA "CentaurHauls"
865 #define CPUID_VENDOR_HYGON "HygonGenuine"
867 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
868 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
869 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
870 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
871 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
872 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
874 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
875 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
877 /* CPUID[0xB].ECX level types */
878 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
879 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
880 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
881 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
883 /* MSR Feature Bits */
884 #define MSR_ARCH_CAP_RDCL_NO (1U << 0)
885 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
886 #define MSR_ARCH_CAP_RSBA (1U << 2)
887 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
888 #define MSR_ARCH_CAP_SSB_NO (1U << 4)
889 #define MSR_ARCH_CAP_MDS_NO (1U << 5)
890 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
891 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
892 #define MSR_ARCH_CAP_TAA_NO (1U << 8)
894 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
896 /* VMX MSR features */
897 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
898 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
899 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
900 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
901 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
902 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
904 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
905 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
906 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6)
907 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7)
908 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8)
909 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
910 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29)
911 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30)
913 #define MSR_VMX_EPT_EXECONLY (1ULL << 0)
914 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6)
915 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7)
916 #define MSR_VMX_EPT_UC (1ULL << 8)
917 #define MSR_VMX_EPT_WB (1ULL << 14)
918 #define MSR_VMX_EPT_2MB (1ULL << 16)
919 #define MSR_VMX_EPT_1GB (1ULL << 17)
920 #define MSR_VMX_EPT_INVEPT (1ULL << 20)
921 #define MSR_VMX_EPT_AD_BITS (1ULL << 21)
922 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22)
923 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25)
924 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26)
925 #define MSR_VMX_EPT_INVVPID (1ULL << 32)
926 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
927 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
928 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42)
929 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
931 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
934 /* VMX controls */
935 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
936 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
937 #define VMX_CPU_BASED_HLT_EXITING 0x00000080
938 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
939 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
940 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
941 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
942 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
943 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
944 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
945 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
946 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000
947 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
948 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
949 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
950 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
951 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
952 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
953 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
954 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
955 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
957 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
958 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
959 #define VMX_SECONDARY_EXEC_DESC 0x00000004
960 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
961 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
962 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
963 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
964 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
965 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
966 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
967 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
968 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
969 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
970 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
971 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
972 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
973 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
974 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
975 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000
977 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
978 #define VMX_PIN_BASED_NMI_EXITING 0x00000008
979 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
980 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
981 #define VMX_PIN_BASED_POSTED_INTR 0x00000080
983 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
984 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
985 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
986 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
987 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
988 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
989 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
990 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
991 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
992 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
993 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
994 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
995 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000
997 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
998 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200
999 #define VMX_VM_ENTRY_SMM 0x00000400
1000 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
1001 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
1002 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
1003 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
1004 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
1005 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
1006 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
1007 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000
1009 /* Supported Hyper-V Enlightenments */
1010 #define HYPERV_FEAT_RELAXED 0
1011 #define HYPERV_FEAT_VAPIC 1
1012 #define HYPERV_FEAT_TIME 2
1013 #define HYPERV_FEAT_CRASH 3
1014 #define HYPERV_FEAT_RESET 4
1015 #define HYPERV_FEAT_VPINDEX 5
1016 #define HYPERV_FEAT_RUNTIME 6
1017 #define HYPERV_FEAT_SYNIC 7
1018 #define HYPERV_FEAT_STIMER 8
1019 #define HYPERV_FEAT_FREQUENCIES 9
1020 #define HYPERV_FEAT_REENLIGHTENMENT 10
1021 #define HYPERV_FEAT_TLBFLUSH 11
1022 #define HYPERV_FEAT_EVMCS 12
1023 #define HYPERV_FEAT_IPI 13
1024 #define HYPERV_FEAT_STIMER_DIRECT 14
1026 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
1027 #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
1028 #endif
1030 #define EXCP00_DIVZ 0
1031 #define EXCP01_DB 1
1032 #define EXCP02_NMI 2
1033 #define EXCP03_INT3 3
1034 #define EXCP04_INTO 4
1035 #define EXCP05_BOUND 5
1036 #define EXCP06_ILLOP 6
1037 #define EXCP07_PREX 7
1038 #define EXCP08_DBLE 8
1039 #define EXCP09_XERR 9
1040 #define EXCP0A_TSS 10
1041 #define EXCP0B_NOSEG 11
1042 #define EXCP0C_STACK 12
1043 #define EXCP0D_GPF 13
1044 #define EXCP0E_PAGE 14
1045 #define EXCP10_COPR 16
1046 #define EXCP11_ALGN 17
1047 #define EXCP12_MCHK 18
1049 #define EXCP_VMEXIT 0x100 /* only for system emulation */
1050 #define EXCP_SYSCALL 0x101 /* only for user emulation */
1051 #define EXCP_VSYSCALL 0x102 /* only for user emulation */
1053 /* i386-specific interrupt pending bits. */
1054 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
1055 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
1056 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
1057 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
1058 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
1059 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
1060 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
1062 /* Use a clearer name for this. */
1063 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
1065 /* Instead of computing the condition codes after each x86 instruction,
1066 * QEMU just stores one operand (called CC_SRC), the result
1067 * (called CC_DST) and the type of operation (called CC_OP). When the
1068 * condition codes are needed, the condition codes can be calculated
1069 * using this information. Condition codes are not generated if they
1070 * are only needed for conditional branches.
1072 typedef enum {
1073 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
1074 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
1076 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
1077 CC_OP_MULW,
1078 CC_OP_MULL,
1079 CC_OP_MULQ,
1081 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1082 CC_OP_ADDW,
1083 CC_OP_ADDL,
1084 CC_OP_ADDQ,
1086 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1087 CC_OP_ADCW,
1088 CC_OP_ADCL,
1089 CC_OP_ADCQ,
1091 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1092 CC_OP_SUBW,
1093 CC_OP_SUBL,
1094 CC_OP_SUBQ,
1096 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1097 CC_OP_SBBW,
1098 CC_OP_SBBL,
1099 CC_OP_SBBQ,
1101 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
1102 CC_OP_LOGICW,
1103 CC_OP_LOGICL,
1104 CC_OP_LOGICQ,
1106 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
1107 CC_OP_INCW,
1108 CC_OP_INCL,
1109 CC_OP_INCQ,
1111 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
1112 CC_OP_DECW,
1113 CC_OP_DECL,
1114 CC_OP_DECQ,
1116 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
1117 CC_OP_SHLW,
1118 CC_OP_SHLL,
1119 CC_OP_SHLQ,
1121 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
1122 CC_OP_SARW,
1123 CC_OP_SARL,
1124 CC_OP_SARQ,
1126 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
1127 CC_OP_BMILGW,
1128 CC_OP_BMILGL,
1129 CC_OP_BMILGQ,
1131 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */
1132 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */
1133 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
1135 CC_OP_CLR, /* Z set, all other flags clear. */
1136 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */
1138 CC_OP_NB,
1139 } CCOp;
1141 typedef struct SegmentCache {
1142 uint32_t selector;
1143 target_ulong base;
1144 uint32_t limit;
1145 uint32_t flags;
1146 } SegmentCache;
1148 #define MMREG_UNION(n, bits) \
1149 union n { \
1150 uint8_t _b_##n[(bits)/8]; \
1151 uint16_t _w_##n[(bits)/16]; \
1152 uint32_t _l_##n[(bits)/32]; \
1153 uint64_t _q_##n[(bits)/64]; \
1154 float32 _s_##n[(bits)/32]; \
1155 float64 _d_##n[(bits)/64]; \
1158 typedef union {
1159 uint8_t _b[16];
1160 uint16_t _w[8];
1161 uint32_t _l[4];
1162 uint64_t _q[2];
1163 } XMMReg;
1165 typedef union {
1166 uint8_t _b[32];
1167 uint16_t _w[16];
1168 uint32_t _l[8];
1169 uint64_t _q[4];
1170 } YMMReg;
1172 typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
1173 typedef MMREG_UNION(MMXReg, 64) MMXReg;
1175 typedef struct BNDReg {
1176 uint64_t lb;
1177 uint64_t ub;
1178 } BNDReg;
1180 typedef struct BNDCSReg {
1181 uint64_t cfgu;
1182 uint64_t sts;
1183 } BNDCSReg;
1185 #define BNDCFG_ENABLE 1ULL
1186 #define BNDCFG_BNDPRESERVE 2ULL
1187 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
1189 #ifdef HOST_WORDS_BIGENDIAN
1190 #define ZMM_B(n) _b_ZMMReg[63 - (n)]
1191 #define ZMM_W(n) _w_ZMMReg[31 - (n)]
1192 #define ZMM_L(n) _l_ZMMReg[15 - (n)]
1193 #define ZMM_S(n) _s_ZMMReg[15 - (n)]
1194 #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1195 #define ZMM_D(n) _d_ZMMReg[7 - (n)]
1197 #define MMX_B(n) _b_MMXReg[7 - (n)]
1198 #define MMX_W(n) _w_MMXReg[3 - (n)]
1199 #define MMX_L(n) _l_MMXReg[1 - (n)]
1200 #define MMX_S(n) _s_MMXReg[1 - (n)]
1201 #else
1202 #define ZMM_B(n) _b_ZMMReg[n]
1203 #define ZMM_W(n) _w_ZMMReg[n]
1204 #define ZMM_L(n) _l_ZMMReg[n]
1205 #define ZMM_S(n) _s_ZMMReg[n]
1206 #define ZMM_Q(n) _q_ZMMReg[n]
1207 #define ZMM_D(n) _d_ZMMReg[n]
1209 #define MMX_B(n) _b_MMXReg[n]
1210 #define MMX_W(n) _w_MMXReg[n]
1211 #define MMX_L(n) _l_MMXReg[n]
1212 #define MMX_S(n) _s_MMXReg[n]
1213 #endif
1214 #define MMX_Q(n) _q_MMXReg[n]
1216 typedef union {
1217 floatx80 d __attribute__((aligned(16)));
1218 MMXReg mmx;
1219 } FPReg;
1221 typedef struct {
1222 uint64_t base;
1223 uint64_t mask;
1224 } MTRRVar;
1226 #define CPU_NB_REGS64 16
1227 #define CPU_NB_REGS32 8
1229 #ifdef TARGET_X86_64
1230 #define CPU_NB_REGS CPU_NB_REGS64
1231 #else
1232 #define CPU_NB_REGS CPU_NB_REGS32
1233 #endif
1235 #define MAX_FIXED_COUNTERS 3
1236 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1238 #define TARGET_INSN_START_EXTRA_WORDS 1
1240 #define NB_OPMASK_REGS 8
1242 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
1243 * that APIC ID hasn't been set yet
1245 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
1247 typedef union X86LegacyXSaveArea {
1248 struct {
1249 uint16_t fcw;
1250 uint16_t fsw;
1251 uint8_t ftw;
1252 uint8_t reserved;
1253 uint16_t fpop;
1254 uint64_t fpip;
1255 uint64_t fpdp;
1256 uint32_t mxcsr;
1257 uint32_t mxcsr_mask;
1258 FPReg fpregs[8];
1259 uint8_t xmm_regs[16][16];
1261 uint8_t data[512];
1262 } X86LegacyXSaveArea;
1264 typedef struct X86XSaveHeader {
1265 uint64_t xstate_bv;
1266 uint64_t xcomp_bv;
1267 uint64_t reserve0;
1268 uint8_t reserved[40];
1269 } X86XSaveHeader;
1271 /* Ext. save area 2: AVX State */
1272 typedef struct XSaveAVX {
1273 uint8_t ymmh[16][16];
1274 } XSaveAVX;
1276 /* Ext. save area 3: BNDREG */
1277 typedef struct XSaveBNDREG {
1278 BNDReg bnd_regs[4];
1279 } XSaveBNDREG;
1281 /* Ext. save area 4: BNDCSR */
1282 typedef union XSaveBNDCSR {
1283 BNDCSReg bndcsr;
1284 uint8_t data[64];
1285 } XSaveBNDCSR;
1287 /* Ext. save area 5: Opmask */
1288 typedef struct XSaveOpmask {
1289 uint64_t opmask_regs[NB_OPMASK_REGS];
1290 } XSaveOpmask;
1292 /* Ext. save area 6: ZMM_Hi256 */
1293 typedef struct XSaveZMM_Hi256 {
1294 uint8_t zmm_hi256[16][32];
1295 } XSaveZMM_Hi256;
1297 /* Ext. save area 7: Hi16_ZMM */
1298 typedef struct XSaveHi16_ZMM {
1299 uint8_t hi16_zmm[16][64];
1300 } XSaveHi16_ZMM;
1302 /* Ext. save area 9: PKRU state */
1303 typedef struct XSavePKRU {
1304 uint32_t pkru;
1305 uint32_t padding;
1306 } XSavePKRU;
1308 typedef struct X86XSaveArea {
1309 X86LegacyXSaveArea legacy;
1310 X86XSaveHeader header;
1312 /* Extended save areas: */
1314 /* AVX State: */
1315 XSaveAVX avx_state;
1316 uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
1317 /* MPX State: */
1318 XSaveBNDREG bndreg_state;
1319 XSaveBNDCSR bndcsr_state;
1320 /* AVX-512 State: */
1321 XSaveOpmask opmask_state;
1322 XSaveZMM_Hi256 zmm_hi256_state;
1323 XSaveHi16_ZMM hi16_zmm_state;
1324 /* PKRU State: */
1325 XSavePKRU pkru_state;
1326 } X86XSaveArea;
1328 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
1329 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1330 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
1331 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1332 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
1333 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1334 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
1335 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1336 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
1337 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1338 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
1339 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1340 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
1341 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1343 typedef enum TPRAccess {
1344 TPR_ACCESS_READ,
1345 TPR_ACCESS_WRITE,
1346 } TPRAccess;
1348 /* Cache information data structures: */
1350 enum CacheType {
1351 DATA_CACHE,
1352 INSTRUCTION_CACHE,
1353 UNIFIED_CACHE
1356 typedef struct CPUCacheInfo {
1357 enum CacheType type;
1358 uint8_t level;
1359 /* Size in bytes */
1360 uint32_t size;
1361 /* Line size, in bytes */
1362 uint16_t line_size;
1364 * Associativity.
1365 * Note: representation of fully-associative caches is not implemented
1367 uint8_t associativity;
1368 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1369 uint8_t partitions;
1370 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1371 uint32_t sets;
1373 * Lines per tag.
1374 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1375 * (Is this synonym to @partitions?)
1377 uint8_t lines_per_tag;
1379 /* Self-initializing cache */
1380 bool self_init;
1382 * WBINVD/INVD is not guaranteed to act upon lower level caches of
1383 * non-originating threads sharing this cache.
1384 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1386 bool no_invd_sharing;
1388 * Cache is inclusive of lower cache levels.
1389 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1391 bool inclusive;
1393 * A complex function is used to index the cache, potentially using all
1394 * address bits. CPUID[4].EDX[bit 2].
1396 bool complex_indexing;
1397 } CPUCacheInfo;
1400 typedef struct CPUCaches {
1401 CPUCacheInfo *l1d_cache;
1402 CPUCacheInfo *l1i_cache;
1403 CPUCacheInfo *l2_cache;
1404 CPUCacheInfo *l3_cache;
1405 } CPUCaches;
1407 typedef struct HVFX86LazyFlags {
1408 target_ulong result;
1409 target_ulong auxbits;
1410 } HVFX86LazyFlags;
1412 typedef struct CPUX86State {
1413 /* standard registers */
1414 target_ulong regs[CPU_NB_REGS];
1415 target_ulong eip;
1416 target_ulong eflags; /* eflags register. During CPU emulation, CC
1417 flags and DF are set to zero because they are
1418 stored elsewhere */
1420 /* emulator internal eflags handling */
1421 target_ulong cc_dst;
1422 target_ulong cc_src;
1423 target_ulong cc_src2;
1424 uint32_t cc_op;
1425 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1426 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
1427 are known at translation time. */
1428 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
1430 /* segments */
1431 SegmentCache segs[6]; /* selector values */
1432 SegmentCache ldt;
1433 SegmentCache tr;
1434 SegmentCache gdt; /* only base and limit are used */
1435 SegmentCache idt; /* only base and limit are used */
1437 target_ulong cr[5]; /* NOTE: cr1 is unused */
1438 int32_t a20_mask;
1440 BNDReg bnd_regs[4];
1441 BNDCSReg bndcs_regs;
1442 uint64_t msr_bndcfgs;
1443 uint64_t efer;
1445 /* Beginning of state preserved by INIT (dummy marker). */
1446 struct {} start_init_save;
1448 /* FPU state */
1449 unsigned int fpstt; /* top of stack index */
1450 uint16_t fpus;
1451 uint16_t fpuc;
1452 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
1453 FPReg fpregs[8];
1454 /* KVM-only so far */
1455 uint16_t fpop;
1456 uint64_t fpip;
1457 uint64_t fpdp;
1459 /* emulator internal variables */
1460 float_status fp_status;
1461 floatx80 ft0;
1463 float_status mmx_status; /* for 3DNow! float ops */
1464 float_status sse_status;
1465 uint32_t mxcsr;
1466 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
1467 ZMMReg xmm_t0;
1468 MMXReg mmx_t0;
1470 XMMReg ymmh_regs[CPU_NB_REGS];
1472 uint64_t opmask_regs[NB_OPMASK_REGS];
1473 YMMReg zmmh_regs[CPU_NB_REGS];
1474 ZMMReg hi16_zmm_regs[CPU_NB_REGS];
1476 /* sysenter registers */
1477 uint32_t sysenter_cs;
1478 target_ulong sysenter_esp;
1479 target_ulong sysenter_eip;
1480 uint64_t star;
1482 uint64_t vm_hsave;
1484 #ifdef TARGET_X86_64
1485 target_ulong lstar;
1486 target_ulong cstar;
1487 target_ulong fmask;
1488 target_ulong kernelgsbase;
1489 #endif
1491 uint64_t tsc;
1492 uint64_t tsc_adjust;
1493 uint64_t tsc_deadline;
1494 uint64_t tsc_aux;
1496 uint64_t xcr0;
1498 uint64_t mcg_status;
1499 uint64_t msr_ia32_misc_enable;
1500 uint64_t msr_ia32_feature_control;
1502 uint64_t msr_fixed_ctr_ctrl;
1503 uint64_t msr_global_ctrl;
1504 uint64_t msr_global_status;
1505 uint64_t msr_global_ovf_ctrl;
1506 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1507 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1508 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1510 uint64_t pat;
1511 uint32_t smbase;
1512 uint64_t msr_smi_count;
1514 uint32_t pkru;
1515 uint32_t pkrs;
1516 uint32_t tsx_ctrl;
1518 uint64_t spec_ctrl;
1519 uint64_t virt_ssbd;
1521 /* End of state preserved by INIT (dummy marker). */
1522 struct {} end_init_save;
1524 uint64_t system_time_msr;
1525 uint64_t wall_clock_msr;
1526 uint64_t steal_time_msr;
1527 uint64_t async_pf_en_msr;
1528 uint64_t async_pf_int_msr;
1529 uint64_t pv_eoi_en_msr;
1530 uint64_t poll_control_msr;
1532 /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1533 uint64_t msr_hv_hypercall;
1534 uint64_t msr_hv_guest_os_id;
1535 uint64_t msr_hv_tsc;
1537 /* Per-VCPU HV MSRs */
1538 uint64_t msr_hv_vapic;
1539 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1540 uint64_t msr_hv_runtime;
1541 uint64_t msr_hv_synic_control;
1542 uint64_t msr_hv_synic_evt_page;
1543 uint64_t msr_hv_synic_msg_page;
1544 uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1545 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1546 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1547 uint64_t msr_hv_reenlightenment_control;
1548 uint64_t msr_hv_tsc_emulation_control;
1549 uint64_t msr_hv_tsc_emulation_status;
1551 uint64_t msr_rtit_ctrl;
1552 uint64_t msr_rtit_status;
1553 uint64_t msr_rtit_output_base;
1554 uint64_t msr_rtit_output_mask;
1555 uint64_t msr_rtit_cr3_match;
1556 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1558 /* exception/interrupt handling */
1559 int error_code;
1560 int exception_is_int;
1561 target_ulong exception_next_eip;
1562 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
1563 union {
1564 struct CPUBreakpoint *cpu_breakpoint[4];
1565 struct CPUWatchpoint *cpu_watchpoint[4];
1566 }; /* break/watchpoints for dr[0..3] */
1567 int old_exception; /* exception in flight */
1569 uint64_t vm_vmcb;
1570 uint64_t tsc_offset;
1571 uint64_t intercept;
1572 uint16_t intercept_cr_read;
1573 uint16_t intercept_cr_write;
1574 uint16_t intercept_dr_read;
1575 uint16_t intercept_dr_write;
1576 uint32_t intercept_exceptions;
1577 uint64_t nested_cr3;
1578 uint32_t nested_pg_mode;
1579 uint8_t v_tpr;
1581 /* KVM states, automatically cleared on reset */
1582 uint8_t nmi_injected;
1583 uint8_t nmi_pending;
1585 uintptr_t retaddr;
1587 /* Fields up to this point are cleared by a CPU reset */
1588 struct {} end_reset_fields;
1590 /* Fields after this point are preserved across CPU reset. */
1592 /* processor features (e.g. for CPUID insn) */
1593 /* Minimum cpuid leaf 7 value */
1594 uint32_t cpuid_level_func7;
1595 /* Actual cpuid leaf 7 value */
1596 uint32_t cpuid_min_level_func7;
1597 /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1598 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1599 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1600 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1601 /* Actual level/xlevel/xlevel2 value: */
1602 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1603 uint32_t cpuid_vendor1;
1604 uint32_t cpuid_vendor2;
1605 uint32_t cpuid_vendor3;
1606 uint32_t cpuid_version;
1607 FeatureWordArray features;
1608 /* Features that were explicitly enabled/disabled */
1609 FeatureWordArray user_features;
1610 uint32_t cpuid_model[12];
1611 /* Cache information for CPUID. When legacy-cache=on, the cache data
1612 * on each CPUID leaf will be different, because we keep compatibility
1613 * with old QEMU versions.
1615 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1617 /* MTRRs */
1618 uint64_t mtrr_fixed[11];
1619 uint64_t mtrr_deftype;
1620 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1622 /* For KVM */
1623 uint32_t mp_state;
1624 int32_t exception_nr;
1625 int32_t interrupt_injected;
1626 uint8_t soft_interrupt;
1627 uint8_t exception_pending;
1628 uint8_t exception_injected;
1629 uint8_t has_error_code;
1630 uint8_t exception_has_payload;
1631 uint64_t exception_payload;
1632 uint32_t ins_len;
1633 uint32_t sipi_vector;
1634 bool tsc_valid;
1635 int64_t tsc_khz;
1636 int64_t user_tsc_khz; /* for sanity check only */
1637 uint64_t apic_bus_freq;
1638 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1639 void *xsave_buf;
1640 #endif
1641 #if defined(CONFIG_KVM)
1642 struct kvm_nested_state *nested_state;
1643 #endif
1644 #if defined(CONFIG_HVF)
1645 HVFX86LazyFlags hvf_lflags;
1646 void *hvf_mmio_buf;
1647 #endif
1649 uint64_t mcg_cap;
1650 uint64_t mcg_ctl;
1651 uint64_t mcg_ext_ctl;
1652 uint64_t mce_banks[MCE_BANKS_DEF*4];
1653 uint64_t xstate_bv;
1655 /* vmstate */
1656 uint16_t fpus_vmstate;
1657 uint16_t fptag_vmstate;
1658 uint16_t fpregs_format_vmstate;
1660 uint64_t xss;
1661 uint32_t umwait;
1663 TPRAccess tpr_access_type;
1665 unsigned nr_dies;
1666 } CPUX86State;
1668 struct kvm_msrs;
1671 * X86CPU:
1672 * @env: #CPUX86State
1673 * @migratable: If set, only migratable flags will be accepted when "enforce"
1674 * mode is used, and only migratable flags will be included in the "host"
1675 * CPU model.
1677 * An x86 CPU.
1679 struct X86CPU {
1680 /*< private >*/
1681 CPUState parent_obj;
1682 /*< public >*/
1684 CPUNegativeOffsetState neg;
1685 CPUX86State env;
1686 VMChangeStateEntry *vmsentry;
1688 uint64_t ucode_rev;
1690 uint32_t hyperv_spinlock_attempts;
1691 char *hyperv_vendor;
1692 bool hyperv_synic_kvm_only;
1693 uint64_t hyperv_features;
1694 bool hyperv_passthrough;
1695 OnOffAuto hyperv_no_nonarch_cs;
1696 uint32_t hyperv_vendor_id[3];
1697 uint32_t hyperv_interface_id[4];
1698 uint32_t hyperv_version_id[4];
1699 uint32_t hyperv_limits[3];
1701 bool check_cpuid;
1702 bool enforce_cpuid;
1704 * Force features to be enabled even if the host doesn't support them.
1705 * This is dangerous and should be done only for testing CPUID
1706 * compatibility.
1708 bool force_features;
1709 bool expose_kvm;
1710 bool expose_tcg;
1711 bool migratable;
1712 bool migrate_smi_count;
1713 bool max_features; /* Enable all supported features automatically */
1714 uint32_t apic_id;
1716 /* Enables publishing of TSC increment and Local APIC bus frequencies to
1717 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
1718 bool vmware_cpuid_freq;
1720 /* if true the CPUID code directly forward host cache leaves to the guest */
1721 bool cache_info_passthrough;
1723 /* if true the CPUID code directly forwards
1724 * host monitor/mwait leaves to the guest */
1725 struct {
1726 uint32_t eax;
1727 uint32_t ebx;
1728 uint32_t ecx;
1729 uint32_t edx;
1730 } mwait;
1732 /* Features that were filtered out because of missing host capabilities */
1733 FeatureWordArray filtered_features;
1735 /* Enable PMU CPUID bits. This can't be enabled by default yet because
1736 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
1737 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
1738 * capabilities) directly to the guest.
1740 bool enable_pmu;
1742 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
1743 * disabled by default to avoid breaking migration between QEMU with
1744 * different LMCE configurations.
1746 bool enable_lmce;
1748 /* Compatibility bits for old machine types.
1749 * If true present virtual l3 cache for VM, the vcpus in the same virtual
1750 * socket share an virtual l3 cache.
1752 bool enable_l3_cache;
1754 /* Compatibility bits for old machine types.
1755 * If true present the old cache topology information
1757 bool legacy_cache;
1759 /* Compatibility bits for old machine types: */
1760 bool enable_cpuid_0xb;
1762 /* Enable auto level-increase for all CPUID leaves */
1763 bool full_cpuid_auto_level;
1765 /* Enable auto level-increase for Intel Processor Trace leave */
1766 bool intel_pt_auto_level;
1768 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
1769 bool fill_mtrr_mask;
1771 /* if true override the phys_bits value with a value read from the host */
1772 bool host_phys_bits;
1774 /* if set, limit maximum value for phys_bits when host_phys_bits is true */
1775 uint8_t host_phys_bits_limit;
1777 /* Stop SMI delivery for migration compatibility with old machines */
1778 bool kvm_no_smi_migration;
1780 /* Number of physical address bits supported */
1781 uint32_t phys_bits;
1783 /* in order to simplify APIC support, we leave this pointer to the
1784 user */
1785 struct DeviceState *apic_state;
1786 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1787 Notifier machine_done;
1789 struct kvm_msrs *kvm_msr_buf;
1791 int32_t node_id; /* NUMA node this CPU belongs to */
1792 int32_t socket_id;
1793 int32_t die_id;
1794 int32_t core_id;
1795 int32_t thread_id;
1797 int32_t hv_max_vps;
1801 #ifndef CONFIG_USER_ONLY
1802 extern const VMStateDescription vmstate_x86_cpu;
1803 #endif
1805 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
1807 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1808 int cpuid, void *opaque);
1809 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1810 int cpuid, void *opaque);
1811 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1812 void *opaque);
1813 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1814 void *opaque);
1816 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1817 Error **errp);
1819 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
1821 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1822 MemTxAttrs *attrs);
1824 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1825 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1827 void x86_cpu_list(void);
1828 int cpu_x86_support_mca_broadcast(CPUX86State *env);
1830 int cpu_get_pic_interrupt(CPUX86State *s);
1831 /* MSDOS compatibility mode FPU exception support */
1832 void x86_register_ferr_irq(qemu_irq irq);
1833 void fpu_check_raise_ferr_irq(CPUX86State *s);
1834 void cpu_set_ignne(void);
1835 void cpu_clear_ignne(void);
1837 /* mpx_helper.c */
1838 void cpu_sync_bndcs_hflags(CPUX86State *env);
1840 /* this function must always be used to load data in the segment
1841 cache: it synchronizes the hflags with the segment cache values */
1842 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1843 X86Seg seg_reg, unsigned int selector,
1844 target_ulong base,
1845 unsigned int limit,
1846 unsigned int flags)
1848 SegmentCache *sc;
1849 unsigned int new_hflags;
1851 sc = &env->segs[seg_reg];
1852 sc->selector = selector;
1853 sc->base = base;
1854 sc->limit = limit;
1855 sc->flags = flags;
1857 /* update the hidden flags */
1859 if (seg_reg == R_CS) {
1860 #ifdef TARGET_X86_64
1861 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1862 /* long mode */
1863 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1864 env->hflags &= ~(HF_ADDSEG_MASK);
1865 } else
1866 #endif
1868 /* legacy / compatibility case */
1869 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1870 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1871 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1872 new_hflags;
1875 if (seg_reg == R_SS) {
1876 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1877 #if HF_CPL_MASK != 3
1878 #error HF_CPL_MASK is hardcoded
1879 #endif
1880 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1881 /* Possibly switch between BNDCFGS and BNDCFGU */
1882 cpu_sync_bndcs_hflags(env);
1884 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1885 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1886 if (env->hflags & HF_CS64_MASK) {
1887 /* zero base assumed for DS, ES and SS in long mode */
1888 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1889 (env->eflags & VM_MASK) ||
1890 !(env->hflags & HF_CS32_MASK)) {
1891 /* XXX: try to avoid this test. The problem comes from the
1892 fact that is real mode or vm86 mode we only modify the
1893 'base' and 'selector' fields of the segment cache to go
1894 faster. A solution may be to force addseg to one in
1895 translate-i386.c. */
1896 new_hflags |= HF_ADDSEG_MASK;
1897 } else {
1898 new_hflags |= ((env->segs[R_DS].base |
1899 env->segs[R_ES].base |
1900 env->segs[R_SS].base) != 0) <<
1901 HF_ADDSEG_SHIFT;
1903 env->hflags = (env->hflags &
1904 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1908 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1909 uint8_t sipi_vector)
1911 CPUState *cs = CPU(cpu);
1912 CPUX86State *env = &cpu->env;
1914 env->eip = 0;
1915 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1916 sipi_vector << 12,
1917 env->segs[R_CS].limit,
1918 env->segs[R_CS].flags);
1919 cs->halted = 0;
1922 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1923 target_ulong *base, unsigned int *limit,
1924 unsigned int *flags);
1926 /* op_helper.c */
1927 /* used for debug or cpu save/restore */
1929 /* cpu-exec.c */
1930 /* the following helpers are only usable in user mode simulation as
1931 they can trigger unexpected exceptions */
1932 void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector);
1933 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1934 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1935 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
1936 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
1938 /* you can call this signal handler from your SIGBUS and SIGSEGV
1939 signal handlers to inform the virtual CPU of exceptions. non zero
1940 is returned if the signal was handled by the virtual CPU. */
1941 int cpu_x86_signal_handler(int host_signum, void *pinfo,
1942 void *puc);
1944 /* cpu.c */
1945 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
1946 uint32_t vendor2, uint32_t vendor3);
1947 typedef struct PropValue {
1948 const char *prop, *value;
1949 } PropValue;
1950 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props);
1952 /* cpu.c other functions (cpuid) */
1953 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1954 uint32_t *eax, uint32_t *ebx,
1955 uint32_t *ecx, uint32_t *edx);
1956 void cpu_clear_apic_feature(CPUX86State *env);
1957 void host_cpuid(uint32_t function, uint32_t count,
1958 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1960 /* helper.c */
1961 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1963 #ifndef CONFIG_USER_ONLY
1964 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
1966 return !!attrs.secure;
1969 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
1971 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
1975 * load efer and update the corresponding hflags. XXX: do consistency
1976 * checks with cpuid bits?
1978 void cpu_load_efer(CPUX86State *env, uint64_t val);
1979 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1980 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1981 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1982 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1983 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1984 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1985 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1986 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1987 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1988 #endif
1990 /* will be suppressed */
1991 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1992 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1993 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1994 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1996 /* hw/pc.c */
1997 uint64_t cpu_get_tsc(CPUX86State *env);
1999 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
2000 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
2001 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
2003 #ifdef TARGET_X86_64
2004 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
2005 #else
2006 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
2007 #endif
2009 #define cpu_signal_handler cpu_x86_signal_handler
2010 #define cpu_list x86_cpu_list
2012 /* MMU modes definitions */
2013 #define MMU_KSMAP_IDX 0
2014 #define MMU_USER_IDX 1
2015 #define MMU_KNOSMAP_IDX 2
2016 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
2018 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
2019 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
2020 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
2023 static inline int cpu_mmu_index_kernel(CPUX86State *env)
2025 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
2026 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
2027 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
2030 #define CC_DST (env->cc_dst)
2031 #define CC_SRC (env->cc_src)
2032 #define CC_SRC2 (env->cc_src2)
2033 #define CC_OP (env->cc_op)
2035 typedef CPUX86State CPUArchState;
2036 typedef X86CPU ArchCPU;
2038 #include "exec/cpu-all.h"
2039 #include "svm.h"
2041 #if !defined(CONFIG_USER_ONLY)
2042 #include "hw/i386/apic.h"
2043 #endif
2045 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
2046 target_ulong *cs_base, uint32_t *flags)
2048 *cs_base = env->segs[R_CS].base;
2049 *pc = *cs_base + env->eip;
2050 *flags = env->hflags |
2051 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
2054 void do_cpu_init(X86CPU *cpu);
2055 void do_cpu_sipi(X86CPU *cpu);
2057 #define MCE_INJECT_BROADCAST 1
2058 #define MCE_INJECT_UNCOND_AO 2
2060 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
2061 uint64_t status, uint64_t mcg_status, uint64_t addr,
2062 uint64_t misc, int flags);
2064 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
2066 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
2068 uint32_t eflags = env->eflags;
2069 if (tcg_enabled()) {
2070 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
2072 return eflags;
2075 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
2077 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
2080 static inline int32_t x86_get_a20_mask(CPUX86State *env)
2082 if (env->hflags & HF_SMM_MASK) {
2083 return -1;
2084 } else {
2085 return env->a20_mask;
2089 static inline bool cpu_has_vmx(CPUX86State *env)
2091 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
2094 static inline bool cpu_has_svm(CPUX86State *env)
2096 return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM;
2100 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set.
2101 * Since it was set, CR4.VMXE must remain set as long as vCPU is in
2102 * VMX operation. This is because CR4.VMXE is one of the bits set
2103 * in MSR_IA32_VMX_CR4_FIXED1.
2105 * There is one exception to above statement when vCPU enters SMM mode.
2106 * When a vCPU enters SMM mode, it temporarily exit VMX operation and
2107 * may also reset CR4.VMXE during execution in SMM mode.
2108 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation
2109 * and CR4.VMXE is restored to it's original value of being set.
2111 * Therefore, when vCPU is not in SMM mode, we can infer whether
2112 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot
2113 * know for certain.
2115 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
2117 return cpu_has_vmx(env) &&
2118 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK));
2121 /* excp_helper.c */
2122 int get_pg_mode(CPUX86State *env);
2124 /* fpu_helper.c */
2125 void update_fp_status(CPUX86State *env);
2126 void update_mxcsr_status(CPUX86State *env);
2127 void update_mxcsr_from_sse_status(CPUX86State *env);
2129 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
2131 env->mxcsr = mxcsr;
2132 if (tcg_enabled()) {
2133 update_mxcsr_status(env);
2137 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
2139 env->fpuc = fpuc;
2140 if (tcg_enabled()) {
2141 update_fp_status(env);
2145 /* mem_helper.c */
2146 void helper_lock_init(void);
2148 /* svm_helper.c */
2149 #ifdef CONFIG_USER_ONLY
2150 static inline void
2151 cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2152 uint64_t param, uintptr_t retaddr)
2153 { /* no-op */ }
2154 #else
2155 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2156 uint64_t param, uintptr_t retaddr);
2157 #endif
2159 /* apic.c */
2160 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
2161 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
2162 TPRAccess access);
2164 /* Special values for X86CPUVersion: */
2166 /* Resolve to latest CPU version */
2167 #define CPU_VERSION_LATEST -1
2170 * Resolve to version defined by current machine type.
2171 * See x86_cpu_set_default_version()
2173 #define CPU_VERSION_AUTO -2
2175 /* Don't resolve to any versioned CPU models, like old QEMU versions */
2176 #define CPU_VERSION_LEGACY 0
2178 typedef int X86CPUVersion;
2181 * Set default CPU model version for CPU models having
2182 * version == CPU_VERSION_AUTO.
2184 void x86_cpu_set_default_version(X86CPUVersion version);
2186 #define APIC_DEFAULT_ADDRESS 0xfee00000
2187 #define APIC_SPACE_SIZE 0x100000
2189 /* cpu-dump.c */
2190 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
2192 /* cpu.c */
2193 bool cpu_is_bsp(X86CPU *cpu);
2195 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf);
2196 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf);
2197 void x86_update_hflags(CPUX86State* env);
2199 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat)
2201 return !!(cpu->hyperv_features & BIT(feat));
2204 #if defined(TARGET_X86_64) && \
2205 defined(CONFIG_USER_ONLY) && \
2206 defined(CONFIG_LINUX)
2207 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20)
2208 #endif
2210 #endif /* I386_CPU_H */