| commit | 4eb1770988397354ed95dec2bd63c09348ebf707 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 10 May 2021 19:08:41 +0000 (10 20:08 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 25 May 2021 15:01:43 +0000 (25 16:01 +0100) | ||
| tree | 88667f3b61b8f6f70681537dab7a7a7f2f16ee57 | treesnapshot (tar.gz zip) |
| parent | 902b28ae4eba6df303cba57016945426865a6d59 | commitdiff |
hw/arm/armsse.c: Correct modelling of SSE-300 internal SRAMs
The SSE-300 was not correctly modelling its internal SRAMs:
* the SRAM address width default is 18
* the SRAM is mapped at 0x2100_0000, not 0x2000_0000 like
the SSE-200 and IoTKit
The default address width is no longer guest-visible since
our only SSE-300 board sets it explicitly to a non-default
value, but following the hardware's default will help for
any future boards we need to model.
Reported-by: Devaraj Ranganna <devaraj.ranganna@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210510190844.17799-4-peter.maydell@linaro.org
The SSE-300 was not correctly modelling its internal SRAMs:
* the SRAM address width default is 18
* the SRAM is mapped at 0x2100_0000, not 0x2000_0000 like
the SSE-200 and IoTKit
The default address width is no longer guest-visible since
our only SSE-300 board sets it explicitly to a non-default
value, but following the hardware's default will help for
any future boards we need to model.
Reported-by: Devaraj Ranganna <devaraj.ranganna@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210510190844.17799-4-peter.maydell@linaro.org
| hw/arm/armsse.c | diffblobblamehistory |