hw/arm/xlnx-zynqmp.c

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "hw/arm/xlnx-zynqmp.h"
  19 #include "hw/intc/arm_gic_common.h"
  20 #include "exec/address-spaces.h"
  21
  22 #define GIC_NUM_SPI_INTR 160
  23
  24 #define ARM_PHYS_TIMER_PPI  30
  25 #define ARM_VIRT_TIMER_PPI  27
  26
  27 #define GIC_BASE_ADDR       0xf9000000
  28 #define GIC_DIST_ADDR       0xf9010000
  29 #define GIC_CPU_ADDR        0xf9020000
  30
  31 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  32     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  33 };
  34
  35 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  36     57, 59, 61, 63,
  37 };
  38
  39 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  40     0xFF000000, 0xFF010000,
  41 };
  42
  43 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  44     21, 22,
  45 };
  46
  47 typedef struct XlnxZynqMPGICRegion {
  48     int region_index;
  49     uint32_t address;
  50 } XlnxZynqMPGICRegion;
  51
  52 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
  53     { .region_index = 0, .address = GIC_DIST_ADDR, },
  54     { .region_index = 1, .address = GIC_CPU_ADDR,  },
  55 };
  56
  57 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
  58 {
  59     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
  60 }
  61
  62 static void xlnx_zynqmp_init(Object *obj)
  63 {
  64     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
  65     int i;
  66
  67     for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
  68         object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
  69                           "cortex-a53-" TYPE_ARM_CPU);
  70         object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
  71                                   &error_abort);
  72     }
  73
  74     object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
  75     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
  76
  77     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
  78         object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
  79         qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
  80     }
  81
  82     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
  83         object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
  84         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
  85     }
  86 }
  87
  88 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
  89 {
  90     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
  91     MemoryRegion *system_memory = get_system_memory();
  92     uint8_t i;
  93     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
  94     Error *err = NULL;
  95
  96     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
  97     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
  98     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_CPUS);
  99     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
 100     if (err) {
 101         error_propagate((errp), (err));
 102         return;
 103     }
 104     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
 105     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
 106         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
 107         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
 108         MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
 109         uint32_t addr = r->address;
 110         int j;
 111
 112         sysbus_mmio_map(gic, r->region_index, addr);
 113
 114         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
 115             MemoryRegion *alias = &s->gic_mr[i][j];
 116
 117             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
 118             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
 119                                      0, XLNX_ZYNQMP_GIC_REGION_SIZE);
 120             memory_region_add_subregion(system_memory, addr, alias);
 121         }
 122     }
 123
 124     for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
 125         qemu_irq irq;
 126
 127         object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
 128                                 "psci-conduit", &error_abort);
 129         if (i > 0) {
 130             /* Secondary CPUs start in PSCI powered-down state */
 131             object_property_set_bool(OBJECT(&s->cpu[i]), true,
 132                                      "start-powered-off", &error_abort);
 133         }
 134
 135         object_property_set_int(OBJECT(&s->cpu[i]), GIC_BASE_ADDR,
 136                                 "reset-cbar", &err);
 137         if (err) {
 138             error_propagate((errp), (err));
 139             return;
 140         }
 141
 142         object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
 143         if (err) {
 144             error_propagate((errp), (err));
 145             return;
 146         }
 147
 148         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
 149                            qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
 150         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 151                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
 152         qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq);
 153         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 154                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
 155         qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq);
 156     }
 157
 158     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
 159         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 160     }
 161
 162     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 163         NICInfo *nd = &nd_table[i];
 164
 165         if (nd->used) {
 166             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 167             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
 168         }
 169         object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
 170         if (err) {
 171             error_propagate((errp), (err));
 172             return;
 173         }
 174         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
 175         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
 176                            gic_spi[gem_intr[i]]);
 177     }
 178
 179     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 180         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 181         if (err) {
 182             error_propagate((errp), (err));
 183             return;
 184         }
 185         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
 186         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 187                            gic_spi[uart_intr[i]]);
 188     }
 189 }
 190
 191 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 192 {
 193     DeviceClass *dc = DEVICE_CLASS(oc);
 194
 195     dc->realize = xlnx_zynqmp_realize;
 196 }
 197
 198 static const TypeInfo xlnx_zynqmp_type_info = {
 199     .name = TYPE_XLNX_ZYNQMP,
 200     .parent = TYPE_DEVICE,
 201     .instance_size = sizeof(XlnxZynqMPState),
 202     .instance_init = xlnx_zynqmp_init,
 203     .class_init = xlnx_zynqmp_class_init,
 204 };
 205
 206 static void xlnx_zynqmp_register_types(void)
 207 {
 208     type_register_static(&xlnx_zynqmp_type_info);
 209 }
 210
 211 type_init(xlnx_zynqmp_register_types)