hw/intc/apic_common.c

   1 /*
   2  *  APIC support - common bits of emulated and KVM kernel model
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  19  */
  20 #include "qemu/osdep.h"
  21 #include "qemu/error-report.h"
  22 #include "qapi/error.h"
  23 #include "qemu-common.h"
  24 #include "cpu.h"
  25 #include "qapi/visitor.h"
  26 #include "hw/i386/apic.h"
  27 #include "hw/i386/apic_internal.h"
  28 #include "trace.h"
  29 #include "sysemu/kvm.h"
  30 #include "hw/qdev.h"
  31 #include "hw/sysbus.h"
  32
  33 static int apic_irq_delivered;
  34 bool apic_report_tpr_access;
  35
  36 void cpu_set_apic_base(DeviceState *dev, uint64_t val)
  37 {
  38     trace_cpu_set_apic_base(val);
  39
  40     if (dev) {
  41         APICCommonState *s = APIC_COMMON(dev);
  42         APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  43         info->set_base(s, val);
  44     }
  45 }
  46
  47 uint64_t cpu_get_apic_base(DeviceState *dev)
  48 {
  49     if (dev) {
  50         APICCommonState *s = APIC_COMMON(dev);
  51         trace_cpu_get_apic_base((uint64_t)s->apicbase);
  52         return s->apicbase;
  53     } else {
  54         trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
  55         return MSR_IA32_APICBASE_BSP;
  56     }
  57 }
  58
  59 void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
  60 {
  61     APICCommonState *s;
  62     APICCommonClass *info;
  63
  64     if (!dev) {
  65         return;
  66     }
  67
  68     s = APIC_COMMON(dev);
  69     info = APIC_COMMON_GET_CLASS(s);
  70
  71     info->set_tpr(s, val);
  72 }
  73
  74 uint8_t cpu_get_apic_tpr(DeviceState *dev)
  75 {
  76     APICCommonState *s;
  77     APICCommonClass *info;
  78
  79     if (!dev) {
  80         return 0;
  81     }
  82
  83     s = APIC_COMMON(dev);
  84     info = APIC_COMMON_GET_CLASS(s);
  85
  86     return info->get_tpr(s);
  87 }
  88
  89 void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
  90 {
  91     APICCommonState *s = APIC_COMMON(dev);
  92     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  93
  94     apic_report_tpr_access = enable;
  95     if (info->enable_tpr_reporting) {
  96         info->enable_tpr_reporting(s, enable);
  97     }
  98 }
  99
 100 void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
 101 {
 102     APICCommonState *s = APIC_COMMON(dev);
 103     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 104
 105     s->vapic_paddr = paddr;
 106     info->vapic_base_update(s);
 107 }
 108
 109 void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
 110                                    TPRAccess access)
 111 {
 112     APICCommonState *s = APIC_COMMON(dev);
 113
 114     vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
 115 }
 116
 117 void apic_report_irq_delivered(int delivered)
 118 {
 119     apic_irq_delivered += delivered;
 120
 121     trace_apic_report_irq_delivered(apic_irq_delivered);
 122 }
 123
 124 void apic_reset_irq_delivered(void)
 125 {
 126     /* Copy this into a local variable to encourage gcc to emit a plain
 127      * register for a sys/sdt.h marker.  For details on this workaround, see:
 128      * https://sourceware.org/bugzilla/show_bug.cgi?id=13296
 129      */
 130     volatile int a_i_d = apic_irq_delivered;
 131     trace_apic_reset_irq_delivered(a_i_d);
 132
 133     apic_irq_delivered = 0;
 134 }
 135
 136 int apic_get_irq_delivered(void)
 137 {
 138     trace_apic_get_irq_delivered(apic_irq_delivered);
 139
 140     return apic_irq_delivered;
 141 }
 142
 143 void apic_deliver_nmi(DeviceState *dev)
 144 {
 145     APICCommonState *s = APIC_COMMON(dev);
 146     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 147
 148     info->external_nmi(s);
 149 }
 150
 151 bool apic_next_timer(APICCommonState *s, int64_t current_time)
 152 {
 153     int64_t d;
 154
 155     /* We need to store the timer state separately to support APIC
 156      * implementations that maintain a non-QEMU timer, e.g. inside the
 157      * host kernel. This open-coded state allows us to migrate between
 158      * both models. */
 159     s->timer_expiry = -1;
 160
 161     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
 162         return false;
 163     }
 164
 165     d = (current_time - s->initial_count_load_time) >> s->count_shift;
 166
 167     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 168         if (!s->initial_count) {
 169             return false;
 170         }
 171         d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
 172             ((uint64_t)s->initial_count + 1);
 173     } else {
 174         if (d >= s->initial_count) {
 175             return false;
 176         }
 177         d = (uint64_t)s->initial_count + 1;
 178     }
 179     s->next_time = s->initial_count_load_time + (d << s->count_shift);
 180     s->timer_expiry = s->next_time;
 181     return true;
 182 }
 183
 184 void apic_init_reset(DeviceState *dev)
 185 {
 186     APICCommonState *s;
 187     APICCommonClass *info;
 188     int i;
 189
 190     if (!dev) {
 191         return;
 192     }
 193     s = APIC_COMMON(dev);
 194     s->tpr = 0;
 195     s->spurious_vec = 0xff;
 196     s->log_dest = 0;
 197     s->dest_mode = 0xf;
 198     memset(s->isr, 0, sizeof(s->isr));
 199     memset(s->tmr, 0, sizeof(s->tmr));
 200     memset(s->irr, 0, sizeof(s->irr));
 201     for (i = 0; i < APIC_LVT_NB; i++) {
 202         s->lvt[i] = APIC_LVT_MASKED;
 203     }
 204     s->esr = 0;
 205     memset(s->icr, 0, sizeof(s->icr));
 206     s->divide_conf = 0;
 207     s->count_shift = 0;
 208     s->initial_count = 0;
 209     s->initial_count_load_time = 0;
 210     s->next_time = 0;
 211     s->wait_for_sipi = !cpu_is_bsp(s->cpu);
 212
 213     if (s->timer) {
 214         timer_del(s->timer);
 215     }
 216     s->timer_expiry = -1;
 217
 218     info = APIC_COMMON_GET_CLASS(s);
 219     if (info->reset) {
 220         info->reset(s);
 221     }
 222 }
 223
 224 void apic_designate_bsp(DeviceState *dev, bool bsp)
 225 {
 226     if (dev == NULL) {
 227         return;
 228     }
 229
 230     APICCommonState *s = APIC_COMMON(dev);
 231     if (bsp) {
 232         s->apicbase |= MSR_IA32_APICBASE_BSP;
 233     } else {
 234         s->apicbase &= ~MSR_IA32_APICBASE_BSP;
 235     }
 236 }
 237
 238 static void apic_reset_common(DeviceState *dev)
 239 {
 240     APICCommonState *s = APIC_COMMON(dev);
 241     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 242     uint32_t bsp;
 243
 244     bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
 245     s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
 246     s->id = s->initial_apic_id;
 247
 248     s->vapic_paddr = 0;
 249     info->vapic_base_update(s);
 250
 251     apic_init_reset(dev);
 252 }
 253
 254 /* This function is only used for old state version 1 and 2 */
 255 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 256 {
 257     APICCommonState *s = opaque;
 258     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 259     int i;
 260
 261     if (version_id > 2) {
 262         return -EINVAL;
 263     }
 264
 265     /* XXX: what if the base changes? (registered memory regions) */
 266     qemu_get_be32s(f, &s->apicbase);
 267     qemu_get_8s(f, &s->id);
 268     qemu_get_8s(f, &s->arb_id);
 269     qemu_get_8s(f, &s->tpr);
 270     qemu_get_be32s(f, &s->spurious_vec);
 271     qemu_get_8s(f, &s->log_dest);
 272     qemu_get_8s(f, &s->dest_mode);
 273     for (i = 0; i < 8; i++) {
 274         qemu_get_be32s(f, &s->isr[i]);
 275         qemu_get_be32s(f, &s->tmr[i]);
 276         qemu_get_be32s(f, &s->irr[i]);
 277     }
 278     for (i = 0; i < APIC_LVT_NB; i++) {
 279         qemu_get_be32s(f, &s->lvt[i]);
 280     }
 281     qemu_get_be32s(f, &s->esr);
 282     qemu_get_be32s(f, &s->icr[0]);
 283     qemu_get_be32s(f, &s->icr[1]);
 284     qemu_get_be32s(f, &s->divide_conf);
 285     s->count_shift = qemu_get_be32(f);
 286     qemu_get_be32s(f, &s->initial_count);
 287     s->initial_count_load_time = qemu_get_be64(f);
 288     s->next_time = qemu_get_be64(f);
 289
 290     if (version_id >= 2) {
 291         s->timer_expiry = qemu_get_be64(f);
 292     }
 293
 294     if (info->post_load) {
 295         info->post_load(s);
 296     }
 297     return 0;
 298 }
 299
 300 static const VMStateDescription vmstate_apic_common;
 301
 302 static void apic_common_realize(DeviceState *dev, Error **errp)
 303 {
 304     APICCommonState *s = APIC_COMMON(dev);
 305     APICCommonClass *info;
 306     static DeviceState *vapic;
 307     int instance_id = s->id;
 308
 309     info = APIC_COMMON_GET_CLASS(s);
 310     info->realize(dev, errp);
 311
 312     /* Note: We need at least 1M to map the VAPIC option ROM */
 313     if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
 314         ram_size >= 1024 * 1024) {
 315         vapic = sysbus_create_simple("kvmvapic", -1, NULL);
 316     }
 317     s->vapic = vapic;
 318     if (apic_report_tpr_access && info->enable_tpr_reporting) {
 319         info->enable_tpr_reporting(s, true);
 320     }
 321
 322     if (s->legacy_instance_id) {
 323         instance_id = -1;
 324     }
 325     vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common,
 326                                    s, -1, 0);
 327 }
 328
 329 static void apic_common_unrealize(DeviceState *dev, Error **errp)
 330 {
 331     APICCommonState *s = APIC_COMMON(dev);
 332     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 333
 334     vmstate_unregister(NULL, &vmstate_apic_common, s);
 335     info->unrealize(dev, errp);
 336
 337     if (apic_report_tpr_access && info->enable_tpr_reporting) {
 338         info->enable_tpr_reporting(s, false);
 339     }
 340 }
 341
 342 static int apic_pre_load(void *opaque)
 343 {
 344     APICCommonState *s = APIC_COMMON(opaque);
 345
 346     /* The default is !cpu_is_bsp(s->cpu), but the common value is 0
 347      * so that's what apic_common_sipi_needed checks for.  Reset to
 348      * the value that is assumed when the apic_sipi subsection is
 349      * absent.
 350      */
 351     s->wait_for_sipi = 0;
 352     return 0;
 353 }
 354
 355 static void apic_dispatch_pre_save(void *opaque)
 356 {
 357     APICCommonState *s = APIC_COMMON(opaque);
 358     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 359
 360     if (info->pre_save) {
 361         info->pre_save(s);
 362     }
 363 }
 364
 365 static int apic_dispatch_post_load(void *opaque, int version_id)
 366 {
 367     APICCommonState *s = APIC_COMMON(opaque);
 368     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 369
 370     if (info->post_load) {
 371         info->post_load(s);
 372     }
 373     return 0;
 374 }
 375
 376 static bool apic_common_sipi_needed(void *opaque)
 377 {
 378     APICCommonState *s = APIC_COMMON(opaque);
 379     return s->wait_for_sipi != 0;
 380 }
 381
 382 static const VMStateDescription vmstate_apic_common_sipi = {
 383     .name = "apic_sipi",
 384     .version_id = 1,
 385     .minimum_version_id = 1,
 386     .needed = apic_common_sipi_needed,
 387     .fields = (VMStateField[]) {
 388         VMSTATE_INT32(sipi_vector, APICCommonState),
 389         VMSTATE_INT32(wait_for_sipi, APICCommonState),
 390         VMSTATE_END_OF_LIST()
 391     }
 392 };
 393
 394 static const VMStateDescription vmstate_apic_common = {
 395     .name = "apic",
 396     .version_id = 3,
 397     .minimum_version_id = 3,
 398     .minimum_version_id_old = 1,
 399     .load_state_old = apic_load_old,
 400     .pre_load = apic_pre_load,
 401     .pre_save = apic_dispatch_pre_save,
 402     .post_load = apic_dispatch_post_load,
 403     .fields = (VMStateField[]) {
 404         VMSTATE_UINT32(apicbase, APICCommonState),
 405         VMSTATE_UINT8(id, APICCommonState),
 406         VMSTATE_UINT8(arb_id, APICCommonState),
 407         VMSTATE_UINT8(tpr, APICCommonState),
 408         VMSTATE_UINT32(spurious_vec, APICCommonState),
 409         VMSTATE_UINT8(log_dest, APICCommonState),
 410         VMSTATE_UINT8(dest_mode, APICCommonState),
 411         VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
 412         VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
 413         VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
 414         VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
 415         VMSTATE_UINT32(esr, APICCommonState),
 416         VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
 417         VMSTATE_UINT32(divide_conf, APICCommonState),
 418         VMSTATE_INT32(count_shift, APICCommonState),
 419         VMSTATE_UINT32(initial_count, APICCommonState),
 420         VMSTATE_INT64(initial_count_load_time, APICCommonState),
 421         VMSTATE_INT64(next_time, APICCommonState),
 422         VMSTATE_INT64(timer_expiry,
 423                       APICCommonState), /* open-coded timer state */
 424         VMSTATE_END_OF_LIST()
 425     },
 426     .subsections = (const VMStateDescription*[]) {
 427         &vmstate_apic_common_sipi,
 428         NULL
 429     }
 430 };
 431
 432 static Property apic_properties_common[] = {
 433     DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
 434     DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
 435                     true),
 436     DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id,
 437                      false),
 438     DEFINE_PROP_END_OF_LIST(),
 439 };
 440
 441 static void apic_common_get_id(Object *obj, Visitor *v, const char *name,
 442                                void *opaque, Error **errp)
 443 {
 444     APICCommonState *s = APIC_COMMON(obj);
 445     int64_t value;
 446
 447     value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id;
 448     visit_type_int(v, name, &value, errp);
 449 }
 450
 451 static void apic_common_set_id(Object *obj, Visitor *v, const char *name,
 452                                void *opaque, Error **errp)
 453 {
 454     APICCommonState *s = APIC_COMMON(obj);
 455     DeviceState *dev = DEVICE(obj);
 456     Error *local_err = NULL;
 457     int64_t value;
 458
 459     if (dev->realized) {
 460         qdev_prop_set_after_realize(dev, name, errp);
 461         return;
 462     }
 463
 464     visit_type_int(v, name, &value, &local_err);
 465     if (local_err) {
 466         error_propagate(errp, local_err);
 467         return;
 468     }
 469
 470     s->initial_apic_id = value;
 471     s->id = (uint8_t)value;
 472 }
 473
 474 static void apic_common_initfn(Object *obj)
 475 {
 476     APICCommonState *s = APIC_COMMON(obj);
 477
 478     s->id = s->initial_apic_id = -1;
 479     object_property_add(obj, "id", "int",
 480                         apic_common_get_id,
 481                         apic_common_set_id, NULL, NULL, NULL);
 482 }
 483
 484 static void apic_common_class_init(ObjectClass *klass, void *data)
 485 {
 486     DeviceClass *dc = DEVICE_CLASS(klass);
 487
 488     dc->reset = apic_reset_common;
 489     dc->props = apic_properties_common;
 490     dc->realize = apic_common_realize;
 491     dc->unrealize = apic_common_unrealize;
 492     /*
 493      * Reason: APIC and CPU need to be wired up by
 494      * x86_cpu_apic_create()
 495      */
 496     dc->cannot_instantiate_with_device_add_yet = true;
 497 }
 498
 499 static const TypeInfo apic_common_type = {
 500     .name = TYPE_APIC_COMMON,
 501     .parent = TYPE_DEVICE,
 502     .instance_size = sizeof(APICCommonState),
 503     .instance_init = apic_common_initfn,
 504     .class_size = sizeof(APICCommonClass),
 505     .class_init = apic_common_class_init,
 506     .abstract = true,
 507 };
 508
 509 static void apic_common_register_types(void)
 510 {
 511     type_register_static(&apic_common_type);
 512 }
 513
 514 type_init(apic_common_register_types)