2 * Xilinx Zynq MPSoC emulation
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 #include "hw/arm/xlnx-zynqmp.h"
19 #include "hw/intc/arm_gic_common.h"
20 #include "exec/address-spaces.h"
22 #define GIC_NUM_SPI_INTR 160
24 #define ARM_PHYS_TIMER_PPI 30
25 #define ARM_VIRT_TIMER_PPI 27
27 #define GIC_BASE_ADDR 0xf9000000
28 #define GIC_DIST_ADDR 0xf9010000
29 #define GIC_CPU_ADDR 0xf9020000
32 #define SATA_ADDR 0xFD0C0000
33 #define SATA_NUM_PORTS 2
35 static const uint64_t gem_addr
[XLNX_ZYNQMP_NUM_GEMS
] = {
36 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
39 static const int gem_intr
[XLNX_ZYNQMP_NUM_GEMS
] = {
43 static const uint64_t uart_addr
[XLNX_ZYNQMP_NUM_UARTS
] = {
44 0xFF000000, 0xFF010000,
47 static const int uart_intr
[XLNX_ZYNQMP_NUM_UARTS
] = {
51 typedef struct XlnxZynqMPGICRegion
{
54 } XlnxZynqMPGICRegion
;
56 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions
[] = {
57 { .region_index
= 0, .address
= GIC_DIST_ADDR
, },
58 { .region_index
= 1, .address
= GIC_CPU_ADDR
, },
61 static inline int arm_gic_ppi_index(int cpu_nr
, int ppi_index
)
63 return GIC_NUM_SPI_INTR
+ cpu_nr
* GIC_INTERNAL
+ ppi_index
;
66 static void xlnx_zynqmp_init(Object
*obj
)
68 XlnxZynqMPState
*s
= XLNX_ZYNQMP(obj
);
71 for (i
= 0; i
< XLNX_ZYNQMP_NUM_APU_CPUS
; i
++) {
72 object_initialize(&s
->apu_cpu
[i
], sizeof(s
->apu_cpu
[i
]),
73 "cortex-a53-" TYPE_ARM_CPU
);
74 object_property_add_child(obj
, "apu-cpu[*]", OBJECT(&s
->apu_cpu
[i
]),
78 for (i
= 0; i
< XLNX_ZYNQMP_NUM_RPU_CPUS
; i
++) {
79 object_initialize(&s
->rpu_cpu
[i
], sizeof(s
->rpu_cpu
[i
]),
80 "cortex-r5-" TYPE_ARM_CPU
);
81 object_property_add_child(obj
, "rpu-cpu[*]", OBJECT(&s
->rpu_cpu
[i
]),
85 object_initialize(&s
->gic
, sizeof(s
->gic
), TYPE_ARM_GIC
);
86 qdev_set_parent_bus(DEVICE(&s
->gic
), sysbus_get_default());
88 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
89 object_initialize(&s
->gem
[i
], sizeof(s
->gem
[i
]), TYPE_CADENCE_GEM
);
90 qdev_set_parent_bus(DEVICE(&s
->gem
[i
]), sysbus_get_default());
93 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
94 object_initialize(&s
->uart
[i
], sizeof(s
->uart
[i
]), TYPE_CADENCE_UART
);
95 qdev_set_parent_bus(DEVICE(&s
->uart
[i
]), sysbus_get_default());
98 object_initialize(&s
->sata
, sizeof(s
->sata
), TYPE_SYSBUS_AHCI
);
99 qdev_set_parent_bus(DEVICE(&s
->sata
), sysbus_get_default());
102 static void xlnx_zynqmp_realize(DeviceState
*dev
, Error
**errp
)
104 XlnxZynqMPState
*s
= XLNX_ZYNQMP(dev
);
105 MemoryRegion
*system_memory
= get_system_memory();
107 const char *boot_cpu
= s
->boot_cpu
? s
->boot_cpu
: "apu-cpu[0]";
108 qemu_irq gic_spi
[GIC_NUM_SPI_INTR
];
111 /* Create the four OCM banks */
112 for (i
= 0; i
< XLNX_ZYNQMP_NUM_OCM_BANKS
; i
++) {
113 char *ocm_name
= g_strdup_printf("zynqmp.ocm_ram_bank_%d", i
);
115 memory_region_init_ram(&s
->ocm_ram
[i
], NULL
, ocm_name
,
116 XLNX_ZYNQMP_OCM_RAM_SIZE
, &error_fatal
);
117 vmstate_register_ram_global(&s
->ocm_ram
[i
]);
118 memory_region_add_subregion(get_system_memory(),
119 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS
+
120 i
* XLNX_ZYNQMP_OCM_RAM_SIZE
,
126 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-irq", GIC_NUM_SPI_INTR
+ 32);
127 qdev_prop_set_uint32(DEVICE(&s
->gic
), "revision", 2);
128 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS
);
129 object_property_set_bool(OBJECT(&s
->gic
), true, "realized", &err
);
131 error_propagate(errp
, err
);
134 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions
) == XLNX_ZYNQMP_GIC_REGIONS
);
135 for (i
= 0; i
< XLNX_ZYNQMP_GIC_REGIONS
; i
++) {
136 SysBusDevice
*gic
= SYS_BUS_DEVICE(&s
->gic
);
137 const XlnxZynqMPGICRegion
*r
= &xlnx_zynqmp_gic_regions
[i
];
138 MemoryRegion
*mr
= sysbus_mmio_get_region(gic
, r
->region_index
);
139 uint32_t addr
= r
->address
;
142 sysbus_mmio_map(gic
, r
->region_index
, addr
);
144 for (j
= 0; j
< XLNX_ZYNQMP_GIC_ALIASES
; j
++) {
145 MemoryRegion
*alias
= &s
->gic_mr
[i
][j
];
147 addr
+= XLNX_ZYNQMP_GIC_REGION_SIZE
;
148 memory_region_init_alias(alias
, OBJECT(s
), "zynqmp-gic-alias", mr
,
149 0, XLNX_ZYNQMP_GIC_REGION_SIZE
);
150 memory_region_add_subregion(system_memory
, addr
, alias
);
154 for (i
= 0; i
< XLNX_ZYNQMP_NUM_APU_CPUS
; i
++) {
158 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), QEMU_PSCI_CONDUIT_SMC
,
159 "psci-conduit", &error_abort
);
161 name
= object_get_canonical_path_component(OBJECT(&s
->apu_cpu
[i
]));
162 if (strcmp(name
, boot_cpu
)) {
163 /* Secondary CPUs start in PSCI powered-down state */
164 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), true,
165 "start-powered-off", &error_abort
);
167 s
->boot_cpu_ptr
= &s
->apu_cpu
[i
];
171 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), GIC_BASE_ADDR
,
172 "reset-cbar", &error_abort
);
173 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), true, "realized",
176 error_propagate(errp
, err
);
180 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
,
181 qdev_get_gpio_in(DEVICE(&s
->apu_cpu
[i
]),
183 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
184 arm_gic_ppi_index(i
, ARM_PHYS_TIMER_PPI
));
185 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), 0, irq
);
186 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
187 arm_gic_ppi_index(i
, ARM_VIRT_TIMER_PPI
));
188 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), 1, irq
);
191 for (i
= 0; i
< XLNX_ZYNQMP_NUM_RPU_CPUS
; i
++) {
194 name
= object_get_canonical_path_component(OBJECT(&s
->rpu_cpu
[i
]));
195 if (strcmp(name
, boot_cpu
)) {
196 /* Secondary CPUs start in PSCI powered-down state */
197 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true,
198 "start-powered-off", &error_abort
);
200 s
->boot_cpu_ptr
= &s
->rpu_cpu
[i
];
204 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true, "reset-hivecs",
206 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true, "realized",
209 error_propagate(errp
, err
);
214 if (!s
->boot_cpu_ptr
) {
215 error_setg(errp
, "ZynqMP Boot cpu %s not found\n", boot_cpu
);
219 for (i
= 0; i
< GIC_NUM_SPI_INTR
; i
++) {
220 gic_spi
[i
] = qdev_get_gpio_in(DEVICE(&s
->gic
), i
);
223 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
224 NICInfo
*nd
= &nd_table
[i
];
227 qemu_check_nic_model(nd
, TYPE_CADENCE_GEM
);
228 qdev_set_nic_properties(DEVICE(&s
->gem
[i
]), nd
);
230 object_property_set_bool(OBJECT(&s
->gem
[i
]), true, "realized", &err
);
232 error_propagate(errp
, err
);
235 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gem
[i
]), 0, gem_addr
[i
]);
236 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gem
[i
]), 0,
237 gic_spi
[gem_intr
[i
]]);
240 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
241 object_property_set_bool(OBJECT(&s
->uart
[i
]), true, "realized", &err
);
243 error_propagate(errp
, err
);
246 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, uart_addr
[i
]);
247 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
248 gic_spi
[uart_intr
[i
]]);
251 object_property_set_int(OBJECT(&s
->sata
), SATA_NUM_PORTS
, "num-ports",
253 object_property_set_bool(OBJECT(&s
->sata
), true, "realized", &err
);
255 error_propagate(errp
, err
);
259 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sata
), 0, SATA_ADDR
);
260 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sata
), 0, gic_spi
[SATA_INTR
]);
263 static Property xlnx_zynqmp_props
[] = {
264 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState
, boot_cpu
),
265 DEFINE_PROP_END_OF_LIST()
268 static void xlnx_zynqmp_class_init(ObjectClass
*oc
, void *data
)
270 DeviceClass
*dc
= DEVICE_CLASS(oc
);
272 dc
->props
= xlnx_zynqmp_props
;
273 dc
->realize
= xlnx_zynqmp_realize
;
276 * Reason: creates an ARM CPU, thus use after free(), see
277 * arm_cpu_class_init()
279 dc
->cannot_destroy_with_object_finalize_yet
= true;
282 static const TypeInfo xlnx_zynqmp_type_info
= {
283 .name
= TYPE_XLNX_ZYNQMP
,
284 .parent
= TYPE_DEVICE
,
285 .instance_size
= sizeof(XlnxZynqMPState
),
286 .instance_init
= xlnx_zynqmp_init
,
287 .class_init
= xlnx_zynqmp_class_init
,
290 static void xlnx_zynqmp_register_types(void)
292 type_register_static(&xlnx_zynqmp_type_info
);
295 type_init(xlnx_zynqmp_register_types
)