target/riscv/csr.c

   1 /*
   2  * RISC-V Control and Status Registers.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/log.h"
  22 #include "cpu.h"
  23 #include "qemu/main-loop.h"
  24 #include "exec/exec-all.h"
  25
  26 /* CSR function table */
  27 static riscv_csr_operations csr_ops[];
  28
  29 /* CSR function table constants */
  30 enum {
  31     CSR_TABLE_SIZE = 0x1000
  32 };
  33
  34 /* CSR function table public API */
  35 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
  36 {
  37     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
  38 }
  39
  40 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
  41 {
  42     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
  43 }
  44
  45 /* Predicates */
  46 static int fs(CPURISCVState *env, int csrno)
  47 {
  48 #if !defined(CONFIG_USER_ONLY)
  49     /* loose check condition for fcsr in vector extension */
  50     if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
  51         return 0;
  52     }
  53     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
  54         return -RISCV_EXCP_ILLEGAL_INST;
  55     }
  56 #endif
  57     return 0;
  58 }
  59
  60 static int vs(CPURISCVState *env, int csrno)
  61 {
  62     if (env->misa & RVV) {
  63         return 0;
  64     }
  65     return -1;
  66 }
  67
  68 static int ctr(CPURISCVState *env, int csrno)
  69 {
  70 #if !defined(CONFIG_USER_ONLY)
  71     CPUState *cs = env_cpu(env);
  72     RISCVCPU *cpu = RISCV_CPU(cs);
  73
  74     if (!cpu->cfg.ext_counters) {
  75         /* The Counters extensions is not enabled */
  76         return -RISCV_EXCP_ILLEGAL_INST;
  77     }
  78
  79     if (riscv_cpu_virt_enabled(env)) {
  80         switch (csrno) {
  81         case CSR_CYCLE:
  82             if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
  83                 get_field(env->mcounteren, HCOUNTEREN_CY)) {
  84                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  85             }
  86             break;
  87         case CSR_TIME:
  88             if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
  89                 get_field(env->mcounteren, HCOUNTEREN_TM)) {
  90                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  91             }
  92             break;
  93         case CSR_INSTRET:
  94             if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
  95                 get_field(env->mcounteren, HCOUNTEREN_IR)) {
  96                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  97             }
  98             break;
  99         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
 100             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
 101                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
 102                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 103             }
 104             break;
 105 #if defined(TARGET_RISCV32)
 106         case CSR_CYCLEH:
 107             if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
 108                 get_field(env->mcounteren, HCOUNTEREN_CY)) {
 109                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 110             }
 111             break;
 112         case CSR_TIMEH:
 113             if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
 114                 get_field(env->mcounteren, HCOUNTEREN_TM)) {
 115                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 116             }
 117             break;
 118         case CSR_INSTRETH:
 119             if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
 120                 get_field(env->mcounteren, HCOUNTEREN_IR)) {
 121                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 122             }
 123             break;
 124         case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
 125             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
 126                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
 127                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 128             }
 129             break;
 130 #endif
 131         }
 132     }
 133 #endif
 134     return 0;
 135 }
 136
 137 #if !defined(CONFIG_USER_ONLY)
 138 static int any(CPURISCVState *env, int csrno)
 139 {
 140     return 0;
 141 }
 142
 143 static int smode(CPURISCVState *env, int csrno)
 144 {
 145     return -!riscv_has_ext(env, RVS);
 146 }
 147
 148 static int hmode(CPURISCVState *env, int csrno)
 149 {
 150     if (riscv_has_ext(env, RVS) &&
 151         riscv_has_ext(env, RVH)) {
 152         /* Hypervisor extension is supported */
 153         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 154             env->priv == PRV_M) {
 155             return 0;
 156         } else {
 157             return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 158         }
 159     }
 160
 161     return -RISCV_EXCP_ILLEGAL_INST;
 162 }
 163
 164 static int pmp(CPURISCVState *env, int csrno)
 165 {
 166     return -!riscv_feature(env, RISCV_FEATURE_PMP);
 167 }
 168 #endif
 169
 170 /* User Floating-Point CSRs */
 171 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
 172 {
 173 #if !defined(CONFIG_USER_ONLY)
 174     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 175         return -RISCV_EXCP_ILLEGAL_INST;
 176     }
 177 #endif
 178     *val = riscv_cpu_get_fflags(env);
 179     return 0;
 180 }
 181
 182 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
 183 {
 184 #if !defined(CONFIG_USER_ONLY)
 185     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 186         return -RISCV_EXCP_ILLEGAL_INST;
 187     }
 188     env->mstatus |= MSTATUS_FS;
 189 #endif
 190     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
 191     return 0;
 192 }
 193
 194 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
 195 {
 196 #if !defined(CONFIG_USER_ONLY)
 197     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 198         return -RISCV_EXCP_ILLEGAL_INST;
 199     }
 200 #endif
 201     *val = env->frm;
 202     return 0;
 203 }
 204
 205 static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
 206 {
 207 #if !defined(CONFIG_USER_ONLY)
 208     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 209         return -RISCV_EXCP_ILLEGAL_INST;
 210     }
 211     env->mstatus |= MSTATUS_FS;
 212 #endif
 213     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
 214     return 0;
 215 }
 216
 217 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
 218 {
 219 #if !defined(CONFIG_USER_ONLY)
 220     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 221         return -RISCV_EXCP_ILLEGAL_INST;
 222     }
 223 #endif
 224     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
 225         | (env->frm << FSR_RD_SHIFT);
 226     if (vs(env, csrno) >= 0) {
 227         *val |= (env->vxrm << FSR_VXRM_SHIFT)
 228                 | (env->vxsat << FSR_VXSAT_SHIFT);
 229     }
 230     return 0;
 231 }
 232
 233 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
 234 {
 235 #if !defined(CONFIG_USER_ONLY)
 236     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 237         return -RISCV_EXCP_ILLEGAL_INST;
 238     }
 239     env->mstatus |= MSTATUS_FS;
 240 #endif
 241     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 242     if (vs(env, csrno) >= 0) {
 243         env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
 244         env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
 245     }
 246     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
 247     return 0;
 248 }
 249
 250 static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
 251 {
 252     *val = env->vtype;
 253     return 0;
 254 }
 255
 256 static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
 257 {
 258     *val = env->vl;
 259     return 0;
 260 }
 261
 262 static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
 263 {
 264     *val = env->vxrm;
 265     return 0;
 266 }
 267
 268 static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
 269 {
 270     env->vxrm = val;
 271     return 0;
 272 }
 273
 274 static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
 275 {
 276     *val = env->vxsat;
 277     return 0;
 278 }
 279
 280 static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
 281 {
 282     env->vxsat = val;
 283     return 0;
 284 }
 285
 286 static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
 287 {
 288     *val = env->vstart;
 289     return 0;
 290 }
 291
 292 static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
 293 {
 294     env->vstart = val;
 295     return 0;
 296 }
 297
 298 /* User Timers and Counters */
 299 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
 300 {
 301 #if !defined(CONFIG_USER_ONLY)
 302     if (icount_enabled()) {
 303         *val = icount_get();
 304     } else {
 305         *val = cpu_get_host_ticks();
 306     }
 307 #else
 308     *val = cpu_get_host_ticks();
 309 #endif
 310     return 0;
 311 }
 312
 313 #if defined(TARGET_RISCV32)
 314 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
 315 {
 316 #if !defined(CONFIG_USER_ONLY)
 317     if (icount_enabled()) {
 318         *val = icount_get() >> 32;
 319     } else {
 320         *val = cpu_get_host_ticks() >> 32;
 321     }
 322 #else
 323     *val = cpu_get_host_ticks() >> 32;
 324 #endif
 325     return 0;
 326 }
 327 #endif /* TARGET_RISCV32 */
 328
 329 #if defined(CONFIG_USER_ONLY)
 330 static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
 331 {
 332     *val = cpu_get_host_ticks();
 333     return 0;
 334 }
 335
 336 #if defined(TARGET_RISCV32)
 337 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
 338 {
 339     *val = cpu_get_host_ticks() >> 32;
 340     return 0;
 341 }
 342 #endif
 343
 344 #else /* CONFIG_USER_ONLY */
 345
 346 static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
 347 {
 348     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 349
 350     if (!env->rdtime_fn) {
 351         return -RISCV_EXCP_ILLEGAL_INST;
 352     }
 353
 354     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
 355     return 0;
 356 }
 357
 358 #if defined(TARGET_RISCV32)
 359 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
 360 {
 361     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 362
 363     if (!env->rdtime_fn) {
 364         return -RISCV_EXCP_ILLEGAL_INST;
 365     }
 366
 367     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
 368     return 0;
 369 }
 370 #endif
 371
 372 /* Machine constants */
 373
 374 #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
 375 #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
 376 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
 377
 378 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
 379                                            VS_MODE_INTERRUPTS;
 380 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
 381                                      VS_MODE_INTERRUPTS;
 382 static const target_ulong delegable_excps =
 383     (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) |
 384     (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) |
 385     (1ULL << (RISCV_EXCP_ILLEGAL_INST)) |
 386     (1ULL << (RISCV_EXCP_BREAKPOINT)) |
 387     (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) |
 388     (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) |
 389     (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) |
 390     (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) |
 391     (1ULL << (RISCV_EXCP_U_ECALL)) |
 392     (1ULL << (RISCV_EXCP_S_ECALL)) |
 393     (1ULL << (RISCV_EXCP_VS_ECALL)) |
 394     (1ULL << (RISCV_EXCP_M_ECALL)) |
 395     (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) |
 396     (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) |
 397     (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) |
 398     (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
 399     (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
 400     (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
 401     (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
 402 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
 403     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
 404     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
 405 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
 406 static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 407 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 408
 409 #if defined(TARGET_RISCV32)
 410 static const char valid_vm_1_10[16] = {
 411     [VM_1_10_MBARE] = 1,
 412     [VM_1_10_SV32] = 1
 413 };
 414 #elif defined(TARGET_RISCV64)
 415 static const char valid_vm_1_10[16] = {
 416     [VM_1_10_MBARE] = 1,
 417     [VM_1_10_SV39] = 1,
 418     [VM_1_10_SV48] = 1,
 419     [VM_1_10_SV57] = 1
 420 };
 421 #endif /* CONFIG_USER_ONLY */
 422
 423 /* Machine Information Registers */
 424 static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
 425 {
 426     return *val = 0;
 427 }
 428
 429 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val)
 430 {
 431     *val = env->mhartid;
 432     return 0;
 433 }
 434
 435 /* Machine Trap Setup */
 436 static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
 437 {
 438     *val = env->mstatus;
 439     return 0;
 440 }
 441
 442 static int validate_vm(CPURISCVState *env, target_ulong vm)
 443 {
 444     return valid_vm_1_10[vm & 0xf];
 445 }
 446
 447 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
 448 {
 449     uint64_t mstatus = env->mstatus;
 450     uint64_t mask = 0;
 451     int dirty;
 452
 453     /* flush tlb on mstatus fields that affect VM */
 454     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
 455             MSTATUS_MPRV | MSTATUS_SUM)) {
 456         tlb_flush(env_cpu(env));
 457     }
 458     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
 459         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
 460         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
 461         MSTATUS_TW;
 462 #if defined(TARGET_RISCV64)
 463     /*
 464      * RV32: MPV and GVA are not in mstatus. The current plan is to
 465      * add them to mstatush. For now, we just don't support it.
 466      */
 467     mask |= MSTATUS_MPV | MSTATUS_GVA;
 468 #endif
 469
 470     mstatus = (mstatus & ~mask) | (val & mask);
 471
 472     dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
 473             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
 474     mstatus = set_field(mstatus, MSTATUS_SD, dirty);
 475     env->mstatus = mstatus;
 476
 477     return 0;
 478 }
 479
 480 #ifdef TARGET_RISCV32
 481 static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
 482 {
 483     *val = env->mstatus >> 32;
 484     return 0;
 485 }
 486
 487 static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
 488 {
 489     uint64_t valh = (uint64_t)val << 32;
 490     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
 491
 492     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
 493         tlb_flush(env_cpu(env));
 494     }
 495
 496     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
 497
 498     return 0;
 499 }
 500 #endif
 501
 502 static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
 503 {
 504     *val = env->misa;
 505     return 0;
 506 }
 507
 508 static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
 509 {
 510     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
 511         /* drop write to misa */
 512         return 0;
 513     }
 514
 515     /* 'I' or 'E' must be present */
 516     if (!(val & (RVI | RVE))) {
 517         /* It is not, drop write to misa */
 518         return 0;
 519     }
 520
 521     /* 'E' excludes all other extensions */
 522     if (val & RVE) {
 523         /* when we support 'E' we can do "val = RVE;" however
 524          * for now we just drop writes if 'E' is present.
 525          */
 526         return 0;
 527     }
 528
 529     /* Mask extensions that are not supported by this hart */
 530     val &= env->misa_mask;
 531
 532     /* Mask extensions that are not supported by QEMU */
 533     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 534
 535     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
 536     if ((val & RVD) && !(val & RVF)) {
 537         val &= ~RVD;
 538     }
 539
 540     /* Suppress 'C' if next instruction is not aligned
 541      * TODO: this should check next_pc
 542      */
 543     if ((val & RVC) && (GETPC() & ~3) != 0) {
 544         val &= ~RVC;
 545     }
 546
 547     /* misa.MXL writes are not supported by QEMU */
 548     val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
 549
 550     /* flush translation cache */
 551     if (val != env->misa) {
 552         tb_flush(env_cpu(env));
 553     }
 554
 555     env->misa = val;
 556
 557     return 0;
 558 }
 559
 560 static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
 561 {
 562     *val = env->medeleg;
 563     return 0;
 564 }
 565
 566 static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val)
 567 {
 568     env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
 569     return 0;
 570 }
 571
 572 static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
 573 {
 574     *val = env->mideleg;
 575     return 0;
 576 }
 577
 578 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
 579 {
 580     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
 581     if (riscv_has_ext(env, RVH)) {
 582         env->mideleg |= VS_MODE_INTERRUPTS;
 583     }
 584     return 0;
 585 }
 586
 587 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)
 588 {
 589     *val = env->mie;
 590     return 0;
 591 }
 592
 593 static int write_mie(CPURISCVState *env, int csrno, target_ulong val)
 594 {
 595     env->mie = (env->mie & ~all_ints) | (val & all_ints);
 596     return 0;
 597 }
 598
 599 static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
 600 {
 601     *val = env->mtvec;
 602     return 0;
 603 }
 604
 605 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
 606 {
 607     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
 608     if ((val & 3) < 2) {
 609         env->mtvec = val;
 610     } else {
 611         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
 612     }
 613     return 0;
 614 }
 615
 616 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
 617 {
 618     *val = env->mcounteren;
 619     return 0;
 620 }
 621
 622 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
 623 {
 624     env->mcounteren = val;
 625     return 0;
 626 }
 627
 628 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 629 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
 630 {
 631     if (env->priv_ver < PRIV_VERSION_1_11_0) {
 632         return -RISCV_EXCP_ILLEGAL_INST;
 633     }
 634     *val = env->mcounteren;
 635     return 0;
 636 }
 637
 638 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 639 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
 640 {
 641     if (env->priv_ver < PRIV_VERSION_1_11_0) {
 642         return -RISCV_EXCP_ILLEGAL_INST;
 643     }
 644     env->mcounteren = val;
 645     return 0;
 646 }
 647
 648 /* Machine Trap Handling */
 649 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
 650 {
 651     *val = env->mscratch;
 652     return 0;
 653 }
 654
 655 static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val)
 656 {
 657     env->mscratch = val;
 658     return 0;
 659 }
 660
 661 static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val)
 662 {
 663     *val = env->mepc;
 664     return 0;
 665 }
 666
 667 static int write_mepc(CPURISCVState *env, int csrno, target_ulong val)
 668 {
 669     env->mepc = val;
 670     return 0;
 671 }
 672
 673 static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val)
 674 {
 675     *val = env->mcause;
 676     return 0;
 677 }
 678
 679 static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
 680 {
 681     env->mcause = val;
 682     return 0;
 683 }
 684
 685 static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
 686 {
 687     *val = env->mbadaddr;
 688     return 0;
 689 }
 690
 691 static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
 692 {
 693     env->mbadaddr = val;
 694     return 0;
 695 }
 696
 697 static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 698                    target_ulong new_value, target_ulong write_mask)
 699 {
 700     RISCVCPU *cpu = env_archcpu(env);
 701     /* Allow software control of delegable interrupts not claimed by hardware */
 702     target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
 703     uint32_t old_mip;
 704
 705     if (mask) {
 706         old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
 707     } else {
 708         old_mip = env->mip;
 709     }
 710
 711     if (ret_value) {
 712         *ret_value = old_mip;
 713     }
 714
 715     return 0;
 716 }
 717
 718 /* Supervisor Trap Setup */
 719 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
 720 {
 721     target_ulong mask = (sstatus_v1_10_mask);
 722     *val = env->mstatus & mask;
 723     return 0;
 724 }
 725
 726 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
 727 {
 728     target_ulong mask = (sstatus_v1_10_mask);
 729     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
 730     return write_mstatus(env, CSR_MSTATUS, newval);
 731 }
 732
 733 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
 734 {
 735     if (riscv_cpu_virt_enabled(env)) {
 736         /* Tell the guest the VS bits, shifted to the S bit locations */
 737         *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
 738     } else {
 739         *val = env->mie & env->mideleg;
 740     }
 741     return 0;
 742 }
 743
 744 static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
 745 {
 746     target_ulong newval;
 747
 748     if (riscv_cpu_virt_enabled(env)) {
 749         /* Shift the guests S bits to VS */
 750         newval = (env->mie & ~VS_MODE_INTERRUPTS) |
 751                  ((val << 1) & VS_MODE_INTERRUPTS);
 752     } else {
 753         newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
 754     }
 755
 756     return write_mie(env, CSR_MIE, newval);
 757 }
 758
 759 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
 760 {
 761     *val = env->stvec;
 762     return 0;
 763 }
 764
 765 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
 766 {
 767     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
 768     if ((val & 3) < 2) {
 769         env->stvec = val;
 770     } else {
 771         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
 772     }
 773     return 0;
 774 }
 775
 776 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
 777 {
 778     *val = env->scounteren;
 779     return 0;
 780 }
 781
 782 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
 783 {
 784     env->scounteren = val;
 785     return 0;
 786 }
 787
 788 /* Supervisor Trap Handling */
 789 static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val)
 790 {
 791     *val = env->sscratch;
 792     return 0;
 793 }
 794
 795 static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val)
 796 {
 797     env->sscratch = val;
 798     return 0;
 799 }
 800
 801 static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val)
 802 {
 803     *val = env->sepc;
 804     return 0;
 805 }
 806
 807 static int write_sepc(CPURISCVState *env, int csrno, target_ulong val)
 808 {
 809     env->sepc = val;
 810     return 0;
 811 }
 812
 813 static int read_scause(CPURISCVState *env, int csrno, target_ulong *val)
 814 {
 815     *val = env->scause;
 816     return 0;
 817 }
 818
 819 static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
 820 {
 821     env->scause = val;
 822     return 0;
 823 }
 824
 825 static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
 826 {
 827     *val = env->sbadaddr;
 828     return 0;
 829 }
 830
 831 static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
 832 {
 833     env->sbadaddr = val;
 834     return 0;
 835 }
 836
 837 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 838                    target_ulong new_value, target_ulong write_mask)
 839 {
 840     int ret;
 841
 842     if (riscv_cpu_virt_enabled(env)) {
 843         /* Shift the new values to line up with the VS bits */
 844         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
 845                       (write_mask & sip_writable_mask) << 1 & env->mideleg);
 846         ret &= vsip_writable_mask;
 847         ret >>= 1;
 848     } else {
 849         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
 850                       write_mask & env->mideleg & sip_writable_mask);
 851     }
 852
 853     *ret_value &= env->mideleg;
 854     return ret;
 855 }
 856
 857 /* Supervisor Protection and Translation */
 858 static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
 859 {
 860     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
 861         *val = 0;
 862         return 0;
 863     }
 864
 865     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
 866         return -RISCV_EXCP_ILLEGAL_INST;
 867     } else {
 868         *val = env->satp;
 869     }
 870
 871     return 0;
 872 }
 873
 874 static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
 875 {
 876     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
 877         return 0;
 878     }
 879     if (validate_vm(env, get_field(val, SATP_MODE)) &&
 880         ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
 881     {
 882         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
 883             return -RISCV_EXCP_ILLEGAL_INST;
 884         } else {
 885             if ((val ^ env->satp) & SATP_ASID) {
 886                 tlb_flush(env_cpu(env));
 887             }
 888             env->satp = val;
 889         }
 890     }
 891     return 0;
 892 }
 893
 894 /* Hypervisor Extensions */
 895 static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
 896 {
 897     *val = env->hstatus;
 898 #ifdef TARGET_RISCV64
 899     /* We only support 64-bit VSXL */
 900     *val = set_field(*val, HSTATUS_VSXL, 2);
 901 #endif
 902     /* We only support little endian */
 903     *val = set_field(*val, HSTATUS_VSBE, 0);
 904     return 0;
 905 }
 906
 907 static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
 908 {
 909     env->hstatus = val;
 910 #ifdef TARGET_RISCV64
 911     if (get_field(val, HSTATUS_VSXL) != 2) {
 912         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
 913     }
 914 #endif
 915     if (get_field(val, HSTATUS_VSBE) != 0) {
 916         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
 917     }
 918     return 0;
 919 }
 920
 921 static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
 922 {
 923     *val = env->hedeleg;
 924     return 0;
 925 }
 926
 927 static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
 928 {
 929     env->hedeleg = val;
 930     return 0;
 931 }
 932
 933 static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
 934 {
 935     *val = env->hideleg;
 936     return 0;
 937 }
 938
 939 static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
 940 {
 941     env->hideleg = val;
 942     return 0;
 943 }
 944
 945 static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 946                    target_ulong new_value, target_ulong write_mask)
 947 {
 948     int ret = rmw_mip(env, 0, ret_value, new_value,
 949                       write_mask & hip_writable_mask);
 950
 951     *ret_value &= hip_writable_mask;
 952
 953     return ret;
 954 }
 955
 956 static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 957                    target_ulong new_value, target_ulong write_mask)
 958 {
 959     int ret = rmw_mip(env, 0, ret_value, new_value,
 960                       write_mask & hip_writable_mask);
 961
 962     *ret_value &= hip_writable_mask;
 963
 964     return ret;
 965 }
 966
 967 static int read_hie(CPURISCVState *env, int csrno, target_ulong *val)
 968 {
 969     *val = env->mie & VS_MODE_INTERRUPTS;
 970     return 0;
 971 }
 972
 973 static int write_hie(CPURISCVState *env, int csrno, target_ulong val)
 974 {
 975     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
 976     return write_mie(env, CSR_MIE, newval);
 977 }
 978
 979 static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val)
 980 {
 981     *val = env->hcounteren;
 982     return 0;
 983 }
 984
 985 static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
 986 {
 987     env->hcounteren = val;
 988     return 0;
 989 }
 990
 991 static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
 992 {
 993     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
 994     return 0;
 995 }
 996
 997 static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
 998 {
 999     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1000     return 0;
1001 }
1002
1003 static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
1004 {
1005     *val = env->htval;
1006     return 0;
1007 }
1008
1009 static int write_htval(CPURISCVState *env, int csrno, target_ulong val)
1010 {
1011     env->htval = val;
1012     return 0;
1013 }
1014
1015 static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
1016 {
1017     *val = env->htinst;
1018     return 0;
1019 }
1020
1021 static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
1022 {
1023     return 0;
1024 }
1025
1026 static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
1027 {
1028     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1029     return 0;
1030 }
1031
1032 static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
1033 {
1034     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1035     return 0;
1036 }
1037
1038 static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
1039 {
1040     *val = env->hgatp;
1041     return 0;
1042 }
1043
1044 static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
1045 {
1046     env->hgatp = val;
1047     return 0;
1048 }
1049
1050 static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
1051 {
1052     if (!env->rdtime_fn) {
1053         return -RISCV_EXCP_ILLEGAL_INST;
1054     }
1055
1056 #if defined(TARGET_RISCV32)
1057     *val = env->htimedelta & 0xffffffff;
1058 #else
1059     *val = env->htimedelta;
1060 #endif
1061     return 0;
1062 }
1063
1064 static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
1065 {
1066     if (!env->rdtime_fn) {
1067         return -RISCV_EXCP_ILLEGAL_INST;
1068     }
1069
1070 #if defined(TARGET_RISCV32)
1071     env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1072 #else
1073     env->htimedelta = val;
1074 #endif
1075     return 0;
1076 }
1077
1078 #if defined(TARGET_RISCV32)
1079 static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
1080 {
1081     if (!env->rdtime_fn) {
1082         return -RISCV_EXCP_ILLEGAL_INST;
1083     }
1084
1085     *val = env->htimedelta >> 32;
1086     return 0;
1087 }
1088
1089 static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
1090 {
1091     if (!env->rdtime_fn) {
1092         return -RISCV_EXCP_ILLEGAL_INST;
1093     }
1094
1095     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1096     return 0;
1097 }
1098 #endif
1099
1100 /* Virtual CSR Registers */
1101 static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
1102 {
1103     *val = env->vsstatus;
1104     return 0;
1105 }
1106
1107 static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
1108 {
1109     uint64_t mask = (target_ulong)-1;
1110     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1111     return 0;
1112 }
1113
1114 static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
1115                     target_ulong new_value, target_ulong write_mask)
1116 {
1117     int ret = rmw_mip(env, 0, ret_value, new_value,
1118                       write_mask & env->mideleg & vsip_writable_mask);
1119     return ret;
1120 }
1121
1122 static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
1123 {
1124     *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
1125     return 0;
1126 }
1127
1128 static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
1129 {
1130     target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
1131     return write_mie(env, CSR_MIE, newval);
1132 }
1133
1134 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1135 {
1136     *val = env->vstvec;
1137     return 0;
1138 }
1139
1140 static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val)
1141 {
1142     env->vstvec = val;
1143     return 0;
1144 }
1145
1146 static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val)
1147 {
1148     *val = env->vsscratch;
1149     return 0;
1150 }
1151
1152 static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val)
1153 {
1154     env->vsscratch = val;
1155     return 0;
1156 }
1157
1158 static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val)
1159 {
1160     *val = env->vsepc;
1161     return 0;
1162 }
1163
1164 static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val)
1165 {
1166     env->vsepc = val;
1167     return 0;
1168 }
1169
1170 static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val)
1171 {
1172     *val = env->vscause;
1173     return 0;
1174 }
1175
1176 static int write_vscause(CPURISCVState *env, int csrno, target_ulong val)
1177 {
1178     env->vscause = val;
1179     return 0;
1180 }
1181
1182 static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val)
1183 {
1184     *val = env->vstval;
1185     return 0;
1186 }
1187
1188 static int write_vstval(CPURISCVState *env, int csrno, target_ulong val)
1189 {
1190     env->vstval = val;
1191     return 0;
1192 }
1193
1194 static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val)
1195 {
1196     *val = env->vsatp;
1197     return 0;
1198 }
1199
1200 static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val)
1201 {
1202     env->vsatp = val;
1203     return 0;
1204 }
1205
1206 static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
1207 {
1208     *val = env->mtval2;
1209     return 0;
1210 }
1211
1212 static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
1213 {
1214     env->mtval2 = val;
1215     return 0;
1216 }
1217
1218 static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
1219 {
1220     *val = env->mtinst;
1221     return 0;
1222 }
1223
1224 static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
1225 {
1226     env->mtinst = val;
1227     return 0;
1228 }
1229
1230 /* Physical Memory Protection */
1231 static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
1232 {
1233     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1234     return 0;
1235 }
1236
1237 static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val)
1238 {
1239     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1240     return 0;
1241 }
1242
1243 static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val)
1244 {
1245     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1246     return 0;
1247 }
1248
1249 static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
1250 {
1251     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1252     return 0;
1253 }
1254
1255 #endif
1256
1257 /*
1258  * riscv_csrrw - read and/or update control and status register
1259  *
1260  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
1261  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
1262  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
1263  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
1264  */
1265
1266 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
1267                 target_ulong new_value, target_ulong write_mask)
1268 {
1269     int ret;
1270     target_ulong old_value;
1271     RISCVCPU *cpu = env_archcpu(env);
1272
1273     /* check privileges and return -1 if check fails */
1274 #if !defined(CONFIG_USER_ONLY)
1275     int effective_priv = env->priv;
1276     int read_only = get_field(csrno, 0xC00) == 3;
1277
1278     if (riscv_has_ext(env, RVH) &&
1279         env->priv == PRV_S &&
1280         !riscv_cpu_virt_enabled(env)) {
1281         /*
1282          * We are in S mode without virtualisation, therefore we are in HS Mode.
1283          * Add 1 to the effective privledge level to allow us to access the
1284          * Hypervisor CSRs.
1285          */
1286         effective_priv++;
1287     }
1288
1289     if ((write_mask && read_only) ||
1290         (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
1291         return -RISCV_EXCP_ILLEGAL_INST;
1292     }
1293 #endif
1294
1295     /* ensure the CSR extension is enabled. */
1296     if (!cpu->cfg.ext_icsr) {
1297         return -RISCV_EXCP_ILLEGAL_INST;
1298     }
1299
1300     /* check predicate */
1301     if (!csr_ops[csrno].predicate) {
1302         return -RISCV_EXCP_ILLEGAL_INST;
1303     }
1304     ret = csr_ops[csrno].predicate(env, csrno);
1305     if (ret < 0) {
1306         return ret;
1307     }
1308
1309     /* execute combined read/write operation if it exists */
1310     if (csr_ops[csrno].op) {
1311         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1312     }
1313
1314     /* if no accessor exists then return failure */
1315     if (!csr_ops[csrno].read) {
1316         return -RISCV_EXCP_ILLEGAL_INST;
1317     }
1318
1319     /* read old value */
1320     ret = csr_ops[csrno].read(env, csrno, &old_value);
1321     if (ret < 0) {
1322         return ret;
1323     }
1324
1325     /* write value if writable and write mask set, otherwise drop writes */
1326     if (write_mask) {
1327         new_value = (old_value & ~write_mask) | (new_value & write_mask);
1328         if (csr_ops[csrno].write) {
1329             ret = csr_ops[csrno].write(env, csrno, new_value);
1330             if (ret < 0) {
1331                 return ret;
1332             }
1333         }
1334     }
1335
1336     /* return old value */
1337     if (ret_value) {
1338         *ret_value = old_value;
1339     }
1340
1341     return 0;
1342 }
1343
1344 /*
1345  * Debugger support.  If not in user mode, set env->debugger before the
1346  * riscv_csrrw call and clear it after the call.
1347  */
1348 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
1349                 target_ulong new_value, target_ulong write_mask)
1350 {
1351     int ret;
1352 #if !defined(CONFIG_USER_ONLY)
1353     env->debugger = true;
1354 #endif
1355     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
1356 #if !defined(CONFIG_USER_ONLY)
1357     env->debugger = false;
1358 #endif
1359     return ret;
1360 }
1361
1362 /* Control and Status Register function table */
1363 static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
1364     /* User Floating-Point CSRs */
1365     [CSR_FFLAGS] =              { fs,   read_fflags,      write_fflags      },
1366     [CSR_FRM] =                 { fs,   read_frm,         write_frm         },
1367     [CSR_FCSR] =                { fs,   read_fcsr,        write_fcsr        },
1368     /* Vector CSRs */
1369     [CSR_VSTART] =              { vs,   read_vstart,      write_vstart      },
1370     [CSR_VXSAT] =               { vs,   read_vxsat,       write_vxsat       },
1371     [CSR_VXRM] =                { vs,   read_vxrm,        write_vxrm        },
1372     [CSR_VL] =                  { vs,   read_vl                             },
1373     [CSR_VTYPE] =               { vs,   read_vtype                          },
1374     /* User Timers and Counters */
1375     [CSR_CYCLE] =               { ctr,  read_instret                        },
1376     [CSR_INSTRET] =             { ctr,  read_instret                        },
1377 #if defined(TARGET_RISCV32)
1378     [CSR_CYCLEH] =              { ctr,  read_instreth                       },
1379     [CSR_INSTRETH] =            { ctr,  read_instreth                       },
1380 #endif
1381
1382     /* In privileged mode, the monitor will have to emulate TIME CSRs only if
1383      * rdtime callback is not provided by machine/platform emulation */
1384     [CSR_TIME] =                { ctr,  read_time                           },
1385 #if defined(TARGET_RISCV32)
1386     [CSR_TIMEH] =               { ctr,  read_timeh                          },
1387 #endif
1388
1389 #if !defined(CONFIG_USER_ONLY)
1390     /* Machine Timers and Counters */
1391     [CSR_MCYCLE] =              { any,  read_instret                        },
1392     [CSR_MINSTRET] =            { any,  read_instret                        },
1393 #if defined(TARGET_RISCV32)
1394     [CSR_MCYCLEH] =             { any,  read_instreth                       },
1395     [CSR_MINSTRETH] =           { any,  read_instreth                       },
1396 #endif
1397
1398     /* Machine Information Registers */
1399     [CSR_MVENDORID] =           { any,  read_zero                           },
1400     [CSR_MARCHID] =             { any,  read_zero                           },
1401     [CSR_MIMPID] =              { any,  read_zero                           },
1402     [CSR_MHARTID] =             { any,  read_mhartid                        },
1403
1404     /* Machine Trap Setup */
1405     [CSR_MSTATUS] =             { any,  read_mstatus,     write_mstatus     },
1406     [CSR_MISA] =                { any,  read_misa,        write_misa        },
1407     [CSR_MIDELEG] =             { any,  read_mideleg,     write_mideleg     },
1408     [CSR_MEDELEG] =             { any,  read_medeleg,     write_medeleg     },
1409     [CSR_MIE] =                 { any,  read_mie,         write_mie         },
1410     [CSR_MTVEC] =               { any,  read_mtvec,       write_mtvec       },
1411     [CSR_MCOUNTEREN] =          { any,  read_mcounteren,  write_mcounteren  },
1412
1413 #if defined(TARGET_RISCV32)
1414     [CSR_MSTATUSH] =            { any,  read_mstatush,    write_mstatush    },
1415 #endif
1416
1417     [CSR_MSCOUNTEREN] =         { any,  read_mscounteren, write_mscounteren },
1418
1419     /* Machine Trap Handling */
1420     [CSR_MSCRATCH] =            { any,  read_mscratch,    write_mscratch    },
1421     [CSR_MEPC] =                { any,  read_mepc,        write_mepc        },
1422     [CSR_MCAUSE] =              { any,  read_mcause,      write_mcause      },
1423     [CSR_MBADADDR] =            { any,  read_mbadaddr,    write_mbadaddr    },
1424     [CSR_MIP] =                 { any,  NULL,     NULL,     rmw_mip         },
1425
1426     /* Supervisor Trap Setup */
1427     [CSR_SSTATUS] =             { smode, read_sstatus,     write_sstatus     },
1428     [CSR_SIE] =                 { smode, read_sie,         write_sie         },
1429     [CSR_STVEC] =               { smode, read_stvec,       write_stvec       },
1430     [CSR_SCOUNTEREN] =          { smode, read_scounteren,  write_scounteren  },
1431
1432     /* Supervisor Trap Handling */
1433     [CSR_SSCRATCH] =            { smode, read_sscratch,    write_sscratch    },
1434     [CSR_SEPC] =                { smode, read_sepc,        write_sepc        },
1435     [CSR_SCAUSE] =              { smode, read_scause,      write_scause      },
1436     [CSR_SBADADDR] =            { smode, read_sbadaddr,    write_sbadaddr    },
1437     [CSR_SIP] =                 { smode, NULL,     NULL,     rmw_sip         },
1438
1439     /* Supervisor Protection and Translation */
1440     [CSR_SATP] =                { smode, read_satp,        write_satp        },
1441
1442     [CSR_HSTATUS] =             { hmode,   read_hstatus,     write_hstatus    },
1443     [CSR_HEDELEG] =             { hmode,   read_hedeleg,     write_hedeleg    },
1444     [CSR_HIDELEG] =             { hmode,   read_hideleg,     write_hideleg    },
1445     [CSR_HVIP] =                { hmode,   NULL,     NULL,     rmw_hvip       },
1446     [CSR_HIP] =                 { hmode,   NULL,     NULL,     rmw_hip        },
1447     [CSR_HIE] =                 { hmode,   read_hie,         write_hie        },
1448     [CSR_HCOUNTEREN] =          { hmode,   read_hcounteren,  write_hcounteren },
1449     [CSR_HGEIE] =               { hmode,   read_hgeie,       write_hgeie      },
1450     [CSR_HTVAL] =               { hmode,   read_htval,       write_htval      },
1451     [CSR_HTINST] =              { hmode,   read_htinst,      write_htinst     },
1452     [CSR_HGEIP] =               { hmode,   read_hgeip,       write_hgeip      },
1453     [CSR_HGATP] =               { hmode,   read_hgatp,       write_hgatp      },
1454     [CSR_HTIMEDELTA] =          { hmode,   read_htimedelta,  write_htimedelta },
1455 #if defined(TARGET_RISCV32)
1456     [CSR_HTIMEDELTAH] =         { hmode,   read_htimedeltah, write_htimedeltah},
1457 #endif
1458
1459     [CSR_VSSTATUS] =            { hmode,   read_vsstatus,    write_vsstatus   },
1460     [CSR_VSIP] =                { hmode,   NULL,     NULL,     rmw_vsip       },
1461     [CSR_VSIE] =                { hmode,   read_vsie,        write_vsie       },
1462     [CSR_VSTVEC] =              { hmode,   read_vstvec,      write_vstvec     },
1463     [CSR_VSSCRATCH] =           { hmode,   read_vsscratch,   write_vsscratch  },
1464     [CSR_VSEPC] =               { hmode,   read_vsepc,       write_vsepc      },
1465     [CSR_VSCAUSE] =             { hmode,   read_vscause,     write_vscause    },
1466     [CSR_VSTVAL] =              { hmode,   read_vstval,      write_vstval     },
1467     [CSR_VSATP] =               { hmode,   read_vsatp,       write_vsatp      },
1468
1469     [CSR_MTVAL2] =              { hmode,   read_mtval2,      write_mtval2     },
1470     [CSR_MTINST] =              { hmode,   read_mtinst,      write_mtinst     },
1471
1472     /* Physical Memory Protection */
1473     [CSR_PMPCFG0  ... CSR_PMPCFG3]   = { pmp,   read_pmpcfg,  write_pmpcfg   },
1474     [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp,   read_pmpaddr, write_pmpaddr  },
1475
1476     /* Performance Counters */
1477     [CSR_HPMCOUNTER3   ... CSR_HPMCOUNTER31] =    { ctr,  read_zero          },
1478     [CSR_MHPMCOUNTER3  ... CSR_MHPMCOUNTER31] =   { any,  read_zero          },
1479     [CSR_MHPMEVENT3    ... CSR_MHPMEVENT31] =     { any,  read_zero          },
1480 #if defined(TARGET_RISCV32)
1481     [CSR_HPMCOUNTER3H  ... CSR_HPMCOUNTER31H] =   { ctr,  read_zero          },
1482     [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] =  { any,  read_zero          },
1483 #endif
1484 #endif /* !CONFIG_USER_ONLY */
1485 };