2 * RISC-V Control and Status Registers.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "qemu/timer.h"
24 #include "tcg/tcg-cpu.h"
26 #include "time_helper.h"
27 #include "exec/exec-all.h"
28 #include "exec/tb-flush.h"
29 #include "sysemu/cpu-timers.h"
30 #include "qemu/guest-random.h"
31 #include "qapi/error.h"
34 /* CSR function table public API */
35 void riscv_get_csr_ops(int csrno
, riscv_csr_operations
*ops
)
37 *ops
= csr_ops
[csrno
& (CSR_TABLE_SIZE
- 1)];
40 void riscv_set_csr_ops(int csrno
, riscv_csr_operations
*ops
)
42 csr_ops
[csrno
& (CSR_TABLE_SIZE
- 1)] = *ops
;
46 #if !defined(CONFIG_USER_ONLY)
47 RISCVException
smstateen_acc_ok(CPURISCVState
*env
, int index
, uint64_t bit
)
49 bool virt
= env
->virt_enabled
;
51 if (env
->priv
== PRV_M
|| !riscv_cpu_cfg(env
)->ext_smstateen
) {
52 return RISCV_EXCP_NONE
;
55 if (!(env
->mstateen
[index
] & bit
)) {
56 return RISCV_EXCP_ILLEGAL_INST
;
60 if (!(env
->hstateen
[index
] & bit
)) {
61 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
64 if (env
->priv
== PRV_U
&& !(env
->sstateen
[index
] & bit
)) {
65 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
69 if (env
->priv
== PRV_U
&& riscv_has_ext(env
, RVS
)) {
70 if (!(env
->sstateen
[index
] & bit
)) {
71 return RISCV_EXCP_ILLEGAL_INST
;
75 return RISCV_EXCP_NONE
;
79 static RISCVException
fs(CPURISCVState
*env
, int csrno
)
81 #if !defined(CONFIG_USER_ONLY)
82 if (!env
->debugger
&& !riscv_cpu_fp_enabled(env
) &&
83 !riscv_cpu_cfg(env
)->ext_zfinx
) {
84 return RISCV_EXCP_ILLEGAL_INST
;
87 if (!env
->debugger
&& !riscv_cpu_fp_enabled(env
)) {
88 return smstateen_acc_ok(env
, 0, SMSTATEEN0_FCSR
);
91 return RISCV_EXCP_NONE
;
94 static RISCVException
vs(CPURISCVState
*env
, int csrno
)
96 if (riscv_cpu_cfg(env
)->ext_zve32f
) {
97 #if !defined(CONFIG_USER_ONLY)
98 if (!env
->debugger
&& !riscv_cpu_vector_enabled(env
)) {
99 return RISCV_EXCP_ILLEGAL_INST
;
102 return RISCV_EXCP_NONE
;
104 return RISCV_EXCP_ILLEGAL_INST
;
107 static RISCVException
ctr(CPURISCVState
*env
, int csrno
)
109 #if !defined(CONFIG_USER_ONLY)
110 RISCVCPU
*cpu
= env_archcpu(env
);
112 target_ulong ctr_mask
;
113 int base_csrno
= CSR_CYCLE
;
114 bool rv32
= riscv_cpu_mxl(env
) == MXL_RV32
? true : false;
116 if (rv32
&& csrno
>= CSR_CYCLEH
) {
117 /* Offset for RV32 hpmcounternh counters */
120 ctr_index
= csrno
- base_csrno
;
121 ctr_mask
= BIT(ctr_index
);
123 if ((csrno
>= CSR_CYCLE
&& csrno
<= CSR_INSTRET
) ||
124 (csrno
>= CSR_CYCLEH
&& csrno
<= CSR_INSTRETH
)) {
125 if (!riscv_cpu_cfg(env
)->ext_zicntr
) {
126 return RISCV_EXCP_ILLEGAL_INST
;
129 goto skip_ext_pmu_check
;
132 if (!(cpu
->pmu_avail_ctrs
& ctr_mask
)) {
133 /* No counter is enabled in PMU or the counter is out of range */
134 return RISCV_EXCP_ILLEGAL_INST
;
140 return RISCV_EXCP_NONE
;
143 if (env
->priv
< PRV_M
&& !get_field(env
->mcounteren
, ctr_mask
)) {
144 return RISCV_EXCP_ILLEGAL_INST
;
147 if (env
->virt_enabled
) {
148 if (!get_field(env
->hcounteren
, ctr_mask
) ||
149 (env
->priv
== PRV_U
&& !get_field(env
->scounteren
, ctr_mask
))) {
150 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
154 if (riscv_has_ext(env
, RVS
) && env
->priv
== PRV_U
&&
155 !get_field(env
->scounteren
, ctr_mask
)) {
156 return RISCV_EXCP_ILLEGAL_INST
;
160 return RISCV_EXCP_NONE
;
163 static RISCVException
ctr32(CPURISCVState
*env
, int csrno
)
165 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
166 return RISCV_EXCP_ILLEGAL_INST
;
169 return ctr(env
, csrno
);
172 static RISCVException
zcmt(CPURISCVState
*env
, int csrno
)
174 if (!riscv_cpu_cfg(env
)->ext_zcmt
) {
175 return RISCV_EXCP_ILLEGAL_INST
;
178 #if !defined(CONFIG_USER_ONLY)
179 RISCVException ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_JVT
);
180 if (ret
!= RISCV_EXCP_NONE
) {
185 return RISCV_EXCP_NONE
;
188 #if !defined(CONFIG_USER_ONLY)
189 static RISCVException
mctr(CPURISCVState
*env
, int csrno
)
191 RISCVCPU
*cpu
= env_archcpu(env
);
192 uint32_t pmu_avail_ctrs
= cpu
->pmu_avail_ctrs
;
194 int base_csrno
= CSR_MHPMCOUNTER3
;
196 if ((riscv_cpu_mxl(env
) == MXL_RV32
) && csrno
>= CSR_MCYCLEH
) {
197 /* Offset for RV32 mhpmcounternh counters */
201 g_assert(csrno
>= CSR_MHPMCOUNTER3
&& csrno
<= CSR_MHPMCOUNTER31
);
203 ctr_index
= csrno
- base_csrno
;
204 if ((BIT(ctr_index
) & pmu_avail_ctrs
>> 3) == 0) {
205 /* The PMU is not enabled or counter is out of range */
206 return RISCV_EXCP_ILLEGAL_INST
;
209 return RISCV_EXCP_NONE
;
212 static RISCVException
mctr32(CPURISCVState
*env
, int csrno
)
214 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
215 return RISCV_EXCP_ILLEGAL_INST
;
218 return mctr(env
, csrno
);
221 static RISCVException
sscofpmf(CPURISCVState
*env
, int csrno
)
223 if (!riscv_cpu_cfg(env
)->ext_sscofpmf
) {
224 return RISCV_EXCP_ILLEGAL_INST
;
227 return RISCV_EXCP_NONE
;
230 static RISCVException
any(CPURISCVState
*env
, int csrno
)
232 return RISCV_EXCP_NONE
;
235 static RISCVException
any32(CPURISCVState
*env
, int csrno
)
237 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
238 return RISCV_EXCP_ILLEGAL_INST
;
241 return any(env
, csrno
);
245 static RISCVException
aia_any(CPURISCVState
*env
, int csrno
)
247 if (!riscv_cpu_cfg(env
)->ext_smaia
) {
248 return RISCV_EXCP_ILLEGAL_INST
;
251 return any(env
, csrno
);
254 static RISCVException
aia_any32(CPURISCVState
*env
, int csrno
)
256 if (!riscv_cpu_cfg(env
)->ext_smaia
) {
257 return RISCV_EXCP_ILLEGAL_INST
;
260 return any32(env
, csrno
);
263 static RISCVException
smode(CPURISCVState
*env
, int csrno
)
265 if (riscv_has_ext(env
, RVS
)) {
266 return RISCV_EXCP_NONE
;
269 return RISCV_EXCP_ILLEGAL_INST
;
272 static RISCVException
smode32(CPURISCVState
*env
, int csrno
)
274 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
275 return RISCV_EXCP_ILLEGAL_INST
;
278 return smode(env
, csrno
);
281 static RISCVException
aia_smode(CPURISCVState
*env
, int csrno
)
283 if (!riscv_cpu_cfg(env
)->ext_ssaia
) {
284 return RISCV_EXCP_ILLEGAL_INST
;
287 return smode(env
, csrno
);
290 static RISCVException
aia_smode32(CPURISCVState
*env
, int csrno
)
292 if (!riscv_cpu_cfg(env
)->ext_ssaia
) {
293 return RISCV_EXCP_ILLEGAL_INST
;
296 return smode32(env
, csrno
);
299 static RISCVException
hmode(CPURISCVState
*env
, int csrno
)
301 if (riscv_has_ext(env
, RVH
)) {
302 return RISCV_EXCP_NONE
;
305 return RISCV_EXCP_ILLEGAL_INST
;
308 static RISCVException
hmode32(CPURISCVState
*env
, int csrno
)
310 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
311 return RISCV_EXCP_ILLEGAL_INST
;
314 return hmode(env
, csrno
);
318 static RISCVException
umode(CPURISCVState
*env
, int csrno
)
320 if (riscv_has_ext(env
, RVU
)) {
321 return RISCV_EXCP_NONE
;
324 return RISCV_EXCP_ILLEGAL_INST
;
327 static RISCVException
umode32(CPURISCVState
*env
, int csrno
)
329 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
330 return RISCV_EXCP_ILLEGAL_INST
;
333 return umode(env
, csrno
);
336 static RISCVException
mstateen(CPURISCVState
*env
, int csrno
)
338 if (!riscv_cpu_cfg(env
)->ext_smstateen
) {
339 return RISCV_EXCP_ILLEGAL_INST
;
342 return any(env
, csrno
);
345 static RISCVException
hstateen_pred(CPURISCVState
*env
, int csrno
, int base
)
347 if (!riscv_cpu_cfg(env
)->ext_smstateen
) {
348 return RISCV_EXCP_ILLEGAL_INST
;
351 RISCVException ret
= hmode(env
, csrno
);
352 if (ret
!= RISCV_EXCP_NONE
) {
357 return RISCV_EXCP_NONE
;
360 if (env
->priv
< PRV_M
) {
361 if (!(env
->mstateen
[csrno
- base
] & SMSTATEEN_STATEEN
)) {
362 return RISCV_EXCP_ILLEGAL_INST
;
366 return RISCV_EXCP_NONE
;
369 static RISCVException
hstateen(CPURISCVState
*env
, int csrno
)
371 return hstateen_pred(env
, csrno
, CSR_HSTATEEN0
);
374 static RISCVException
hstateenh(CPURISCVState
*env
, int csrno
)
376 return hstateen_pred(env
, csrno
, CSR_HSTATEEN0H
);
379 static RISCVException
sstateen(CPURISCVState
*env
, int csrno
)
381 bool virt
= env
->virt_enabled
;
382 int index
= csrno
- CSR_SSTATEEN0
;
384 if (!riscv_cpu_cfg(env
)->ext_smstateen
) {
385 return RISCV_EXCP_ILLEGAL_INST
;
388 RISCVException ret
= smode(env
, csrno
);
389 if (ret
!= RISCV_EXCP_NONE
) {
394 return RISCV_EXCP_NONE
;
397 if (env
->priv
< PRV_M
) {
398 if (!(env
->mstateen
[index
] & SMSTATEEN_STATEEN
)) {
399 return RISCV_EXCP_ILLEGAL_INST
;
403 if (!(env
->hstateen
[index
] & SMSTATEEN_STATEEN
)) {
404 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
409 return RISCV_EXCP_NONE
;
412 static RISCVException
sstc(CPURISCVState
*env
, int csrno
)
414 bool hmode_check
= false;
416 if (!riscv_cpu_cfg(env
)->ext_sstc
|| !env
->rdtime_fn
) {
417 return RISCV_EXCP_ILLEGAL_INST
;
420 if ((csrno
== CSR_VSTIMECMP
) || (csrno
== CSR_VSTIMECMPH
)) {
424 RISCVException ret
= hmode_check
? hmode(env
, csrno
) : smode(env
, csrno
);
425 if (ret
!= RISCV_EXCP_NONE
) {
430 return RISCV_EXCP_NONE
;
433 if (env
->priv
== PRV_M
) {
434 return RISCV_EXCP_NONE
;
438 * No need of separate function for rv32 as menvcfg stores both menvcfg
441 if (!(get_field(env
->mcounteren
, COUNTEREN_TM
) &&
442 get_field(env
->menvcfg
, MENVCFG_STCE
))) {
443 return RISCV_EXCP_ILLEGAL_INST
;
446 if (env
->virt_enabled
) {
447 if (!(get_field(env
->hcounteren
, COUNTEREN_TM
) &&
448 get_field(env
->henvcfg
, HENVCFG_STCE
))) {
449 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
453 return RISCV_EXCP_NONE
;
456 static RISCVException
sstc_32(CPURISCVState
*env
, int csrno
)
458 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
459 return RISCV_EXCP_ILLEGAL_INST
;
462 return sstc(env
, csrno
);
465 static RISCVException
satp(CPURISCVState
*env
, int csrno
)
467 if (env
->priv
== PRV_S
&& !env
->virt_enabled
&&
468 get_field(env
->mstatus
, MSTATUS_TVM
)) {
469 return RISCV_EXCP_ILLEGAL_INST
;
471 if (env
->priv
== PRV_S
&& env
->virt_enabled
&&
472 get_field(env
->hstatus
, HSTATUS_VTVM
)) {
473 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
476 return smode(env
, csrno
);
479 static RISCVException
hgatp(CPURISCVState
*env
, int csrno
)
481 if (env
->priv
== PRV_S
&& !env
->virt_enabled
&&
482 get_field(env
->mstatus
, MSTATUS_TVM
)) {
483 return RISCV_EXCP_ILLEGAL_INST
;
486 return hmode(env
, csrno
);
489 /* Checks if PointerMasking registers could be accessed */
490 static RISCVException
pointer_masking(CPURISCVState
*env
, int csrno
)
492 /* Check if j-ext is present */
493 if (riscv_has_ext(env
, RVJ
)) {
494 return RISCV_EXCP_NONE
;
496 return RISCV_EXCP_ILLEGAL_INST
;
499 static RISCVException
aia_hmode(CPURISCVState
*env
, int csrno
)
501 if (!riscv_cpu_cfg(env
)->ext_ssaia
) {
502 return RISCV_EXCP_ILLEGAL_INST
;
505 return hmode(env
, csrno
);
508 static RISCVException
aia_hmode32(CPURISCVState
*env
, int csrno
)
510 if (!riscv_cpu_cfg(env
)->ext_ssaia
) {
511 return RISCV_EXCP_ILLEGAL_INST
;
514 return hmode32(env
, csrno
);
517 static RISCVException
pmp(CPURISCVState
*env
, int csrno
)
519 if (riscv_cpu_cfg(env
)->pmp
) {
520 if (csrno
<= CSR_PMPCFG3
) {
521 uint32_t reg_index
= csrno
- CSR_PMPCFG0
;
523 /* TODO: RV128 restriction check */
524 if ((reg_index
& 1) && (riscv_cpu_mxl(env
) == MXL_RV64
)) {
525 return RISCV_EXCP_ILLEGAL_INST
;
529 return RISCV_EXCP_NONE
;
532 return RISCV_EXCP_ILLEGAL_INST
;
535 static RISCVException
have_mseccfg(CPURISCVState
*env
, int csrno
)
537 if (riscv_cpu_cfg(env
)->ext_smepmp
) {
538 return RISCV_EXCP_NONE
;
540 if (riscv_cpu_cfg(env
)->ext_zkr
) {
541 return RISCV_EXCP_NONE
;
544 return RISCV_EXCP_ILLEGAL_INST
;
547 static RISCVException
debug(CPURISCVState
*env
, int csrno
)
549 if (riscv_cpu_cfg(env
)->debug
) {
550 return RISCV_EXCP_NONE
;
553 return RISCV_EXCP_ILLEGAL_INST
;
557 static RISCVException
seed(CPURISCVState
*env
, int csrno
)
559 if (!riscv_cpu_cfg(env
)->ext_zkr
) {
560 return RISCV_EXCP_ILLEGAL_INST
;
563 #if !defined(CONFIG_USER_ONLY)
565 return RISCV_EXCP_NONE
;
569 * With a CSR read-write instruction:
570 * 1) The seed CSR is always available in machine mode as normal.
571 * 2) Attempted access to seed from virtual modes VS and VU always raises
572 * an exception(virtual instruction exception only if mseccfg.sseed=1).
573 * 3) Without the corresponding access control bit set to 1, any attempted
574 * access to seed from U, S or HS modes will raise an illegal instruction
577 if (env
->priv
== PRV_M
) {
578 return RISCV_EXCP_NONE
;
579 } else if (env
->virt_enabled
) {
580 if (env
->mseccfg
& MSECCFG_SSEED
) {
581 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
583 return RISCV_EXCP_ILLEGAL_INST
;
586 if (env
->priv
== PRV_S
&& (env
->mseccfg
& MSECCFG_SSEED
)) {
587 return RISCV_EXCP_NONE
;
588 } else if (env
->priv
== PRV_U
&& (env
->mseccfg
& MSECCFG_USEED
)) {
589 return RISCV_EXCP_NONE
;
591 return RISCV_EXCP_ILLEGAL_INST
;
595 return RISCV_EXCP_NONE
;
599 /* User Floating-Point CSRs */
600 static RISCVException
read_fflags(CPURISCVState
*env
, int csrno
,
603 *val
= riscv_cpu_get_fflags(env
);
604 return RISCV_EXCP_NONE
;
607 static RISCVException
write_fflags(CPURISCVState
*env
, int csrno
,
610 #if !defined(CONFIG_USER_ONLY)
611 if (riscv_has_ext(env
, RVF
)) {
612 env
->mstatus
|= MSTATUS_FS
;
615 riscv_cpu_set_fflags(env
, val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
));
616 return RISCV_EXCP_NONE
;
619 static RISCVException
read_frm(CPURISCVState
*env
, int csrno
,
623 return RISCV_EXCP_NONE
;
626 static RISCVException
write_frm(CPURISCVState
*env
, int csrno
,
629 #if !defined(CONFIG_USER_ONLY)
630 if (riscv_has_ext(env
, RVF
)) {
631 env
->mstatus
|= MSTATUS_FS
;
634 env
->frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
635 return RISCV_EXCP_NONE
;
638 static RISCVException
read_fcsr(CPURISCVState
*env
, int csrno
,
641 *val
= (riscv_cpu_get_fflags(env
) << FSR_AEXC_SHIFT
)
642 | (env
->frm
<< FSR_RD_SHIFT
);
643 return RISCV_EXCP_NONE
;
646 static RISCVException
write_fcsr(CPURISCVState
*env
, int csrno
,
649 #if !defined(CONFIG_USER_ONLY)
650 if (riscv_has_ext(env
, RVF
)) {
651 env
->mstatus
|= MSTATUS_FS
;
654 env
->frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
655 riscv_cpu_set_fflags(env
, (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
);
656 return RISCV_EXCP_NONE
;
659 static RISCVException
read_vtype(CPURISCVState
*env
, int csrno
,
665 vill
= (uint32_t)env
->vill
<< 31;
668 vill
= (uint64_t)env
->vill
<< 63;
671 g_assert_not_reached();
673 *val
= (target_ulong
)vill
| env
->vtype
;
674 return RISCV_EXCP_NONE
;
677 static RISCVException
read_vl(CPURISCVState
*env
, int csrno
,
681 return RISCV_EXCP_NONE
;
684 static RISCVException
read_vlenb(CPURISCVState
*env
, int csrno
,
687 *val
= riscv_cpu_cfg(env
)->vlenb
;
688 return RISCV_EXCP_NONE
;
691 static RISCVException
read_vxrm(CPURISCVState
*env
, int csrno
,
695 return RISCV_EXCP_NONE
;
698 static RISCVException
write_vxrm(CPURISCVState
*env
, int csrno
,
701 #if !defined(CONFIG_USER_ONLY)
702 env
->mstatus
|= MSTATUS_VS
;
705 return RISCV_EXCP_NONE
;
708 static RISCVException
read_vxsat(CPURISCVState
*env
, int csrno
,
712 return RISCV_EXCP_NONE
;
715 static RISCVException
write_vxsat(CPURISCVState
*env
, int csrno
,
718 #if !defined(CONFIG_USER_ONLY)
719 env
->mstatus
|= MSTATUS_VS
;
722 return RISCV_EXCP_NONE
;
725 static RISCVException
read_vstart(CPURISCVState
*env
, int csrno
,
729 return RISCV_EXCP_NONE
;
732 static RISCVException
write_vstart(CPURISCVState
*env
, int csrno
,
735 #if !defined(CONFIG_USER_ONLY)
736 env
->mstatus
|= MSTATUS_VS
;
739 * The vstart CSR is defined to have only enough writable bits
740 * to hold the largest element index, i.e. lg2(VLEN) bits.
742 env
->vstart
= val
& ~(~0ULL << ctzl(riscv_cpu_cfg(env
)->vlenb
<< 3));
743 return RISCV_EXCP_NONE
;
746 static RISCVException
read_vcsr(CPURISCVState
*env
, int csrno
,
749 *val
= (env
->vxrm
<< VCSR_VXRM_SHIFT
) | (env
->vxsat
<< VCSR_VXSAT_SHIFT
);
750 return RISCV_EXCP_NONE
;
753 static RISCVException
write_vcsr(CPURISCVState
*env
, int csrno
,
756 #if !defined(CONFIG_USER_ONLY)
757 env
->mstatus
|= MSTATUS_VS
;
759 env
->vxrm
= (val
& VCSR_VXRM
) >> VCSR_VXRM_SHIFT
;
760 env
->vxsat
= (val
& VCSR_VXSAT
) >> VCSR_VXSAT_SHIFT
;
761 return RISCV_EXCP_NONE
;
764 /* User Timers and Counters */
765 static target_ulong
get_ticks(bool shift
)
770 #if !defined(CONFIG_USER_ONLY)
771 if (icount_enabled()) {
774 val
= cpu_get_host_ticks();
777 val
= cpu_get_host_ticks();
789 #if defined(CONFIG_USER_ONLY)
790 static RISCVException
read_time(CPURISCVState
*env
, int csrno
,
793 *val
= cpu_get_host_ticks();
794 return RISCV_EXCP_NONE
;
797 static RISCVException
read_timeh(CPURISCVState
*env
, int csrno
,
800 *val
= cpu_get_host_ticks() >> 32;
801 return RISCV_EXCP_NONE
;
804 static RISCVException
read_hpmcounter(CPURISCVState
*env
, int csrno
,
807 *val
= get_ticks(false);
808 return RISCV_EXCP_NONE
;
811 static RISCVException
read_hpmcounterh(CPURISCVState
*env
, int csrno
,
814 *val
= get_ticks(true);
815 return RISCV_EXCP_NONE
;
818 #else /* CONFIG_USER_ONLY */
820 static RISCVException
read_mhpmevent(CPURISCVState
*env
, int csrno
,
823 int evt_index
= csrno
- CSR_MCOUNTINHIBIT
;
825 *val
= env
->mhpmevent_val
[evt_index
];
827 return RISCV_EXCP_NONE
;
830 static RISCVException
write_mhpmevent(CPURISCVState
*env
, int csrno
,
833 int evt_index
= csrno
- CSR_MCOUNTINHIBIT
;
834 uint64_t mhpmevt_val
= val
;
836 env
->mhpmevent_val
[evt_index
] = val
;
838 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
839 mhpmevt_val
= mhpmevt_val
|
840 ((uint64_t)env
->mhpmeventh_val
[evt_index
] << 32);
842 riscv_pmu_update_event_map(env
, mhpmevt_val
, evt_index
);
844 return RISCV_EXCP_NONE
;
847 static RISCVException
read_mhpmeventh(CPURISCVState
*env
, int csrno
,
850 int evt_index
= csrno
- CSR_MHPMEVENT3H
+ 3;
852 *val
= env
->mhpmeventh_val
[evt_index
];
854 return RISCV_EXCP_NONE
;
857 static RISCVException
write_mhpmeventh(CPURISCVState
*env
, int csrno
,
860 int evt_index
= csrno
- CSR_MHPMEVENT3H
+ 3;
861 uint64_t mhpmevth_val
= val
;
862 uint64_t mhpmevt_val
= env
->mhpmevent_val
[evt_index
];
864 mhpmevt_val
= mhpmevt_val
| (mhpmevth_val
<< 32);
865 env
->mhpmeventh_val
[evt_index
] = val
;
867 riscv_pmu_update_event_map(env
, mhpmevt_val
, evt_index
);
869 return RISCV_EXCP_NONE
;
872 static RISCVException
write_mhpmcounter(CPURISCVState
*env
, int csrno
,
875 int ctr_idx
= csrno
- CSR_MCYCLE
;
876 PMUCTRState
*counter
= &env
->pmu_ctrs
[ctr_idx
];
877 uint64_t mhpmctr_val
= val
;
879 counter
->mhpmcounter_val
= val
;
880 if (riscv_pmu_ctr_monitor_cycles(env
, ctr_idx
) ||
881 riscv_pmu_ctr_monitor_instructions(env
, ctr_idx
)) {
882 counter
->mhpmcounter_prev
= get_ticks(false);
884 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
885 mhpmctr_val
= mhpmctr_val
|
886 ((uint64_t)counter
->mhpmcounterh_val
<< 32);
888 riscv_pmu_setup_timer(env
, mhpmctr_val
, ctr_idx
);
891 /* Other counters can keep incrementing from the given value */
892 counter
->mhpmcounter_prev
= val
;
895 return RISCV_EXCP_NONE
;
898 static RISCVException
write_mhpmcounterh(CPURISCVState
*env
, int csrno
,
901 int ctr_idx
= csrno
- CSR_MCYCLEH
;
902 PMUCTRState
*counter
= &env
->pmu_ctrs
[ctr_idx
];
903 uint64_t mhpmctr_val
= counter
->mhpmcounter_val
;
904 uint64_t mhpmctrh_val
= val
;
906 counter
->mhpmcounterh_val
= val
;
907 mhpmctr_val
= mhpmctr_val
| (mhpmctrh_val
<< 32);
908 if (riscv_pmu_ctr_monitor_cycles(env
, ctr_idx
) ||
909 riscv_pmu_ctr_monitor_instructions(env
, ctr_idx
)) {
910 counter
->mhpmcounterh_prev
= get_ticks(true);
912 riscv_pmu_setup_timer(env
, mhpmctr_val
, ctr_idx
);
915 counter
->mhpmcounterh_prev
= val
;
918 return RISCV_EXCP_NONE
;
921 static RISCVException
riscv_pmu_read_ctr(CPURISCVState
*env
, target_ulong
*val
,
922 bool upper_half
, uint32_t ctr_idx
)
924 PMUCTRState
*counter
= &env
->pmu_ctrs
[ctr_idx
];
925 target_ulong ctr_prev
= upper_half
? counter
->mhpmcounterh_prev
:
926 counter
->mhpmcounter_prev
;
927 target_ulong ctr_val
= upper_half
? counter
->mhpmcounterh_val
:
928 counter
->mhpmcounter_val
;
930 if (get_field(env
->mcountinhibit
, BIT(ctr_idx
))) {
932 * Counter should not increment if inhibit bit is set. We can't really
933 * stop the icount counting. Just return the counter value written by
934 * the supervisor to indicate that counter was not incremented.
936 if (!counter
->started
) {
938 return RISCV_EXCP_NONE
;
940 /* Mark that the counter has been stopped */
941 counter
->started
= false;
946 * The kernel computes the perf delta by subtracting the current value from
947 * the value it initialized previously (ctr_val).
949 if (riscv_pmu_ctr_monitor_cycles(env
, ctr_idx
) ||
950 riscv_pmu_ctr_monitor_instructions(env
, ctr_idx
)) {
951 *val
= get_ticks(upper_half
) - ctr_prev
+ ctr_val
;
956 return RISCV_EXCP_NONE
;
959 static RISCVException
read_hpmcounter(CPURISCVState
*env
, int csrno
,
964 if (csrno
>= CSR_MCYCLE
&& csrno
<= CSR_MHPMCOUNTER31
) {
965 ctr_index
= csrno
- CSR_MCYCLE
;
966 } else if (csrno
>= CSR_CYCLE
&& csrno
<= CSR_HPMCOUNTER31
) {
967 ctr_index
= csrno
- CSR_CYCLE
;
969 return RISCV_EXCP_ILLEGAL_INST
;
972 return riscv_pmu_read_ctr(env
, val
, false, ctr_index
);
975 static RISCVException
read_hpmcounterh(CPURISCVState
*env
, int csrno
,
980 if (csrno
>= CSR_MCYCLEH
&& csrno
<= CSR_MHPMCOUNTER31H
) {
981 ctr_index
= csrno
- CSR_MCYCLEH
;
982 } else if (csrno
>= CSR_CYCLEH
&& csrno
<= CSR_HPMCOUNTER31H
) {
983 ctr_index
= csrno
- CSR_CYCLEH
;
985 return RISCV_EXCP_ILLEGAL_INST
;
988 return riscv_pmu_read_ctr(env
, val
, true, ctr_index
);
991 static RISCVException
read_scountovf(CPURISCVState
*env
, int csrno
,
994 int mhpmevt_start
= CSR_MHPMEVENT3
- CSR_MCOUNTINHIBIT
;
997 target_ulong
*mhpm_evt_val
;
998 uint64_t of_bit_mask
;
1000 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
1001 mhpm_evt_val
= env
->mhpmeventh_val
;
1002 of_bit_mask
= MHPMEVENTH_BIT_OF
;
1004 mhpm_evt_val
= env
->mhpmevent_val
;
1005 of_bit_mask
= MHPMEVENT_BIT_OF
;
1008 for (i
= mhpmevt_start
; i
< RV_MAX_MHPMEVENTS
; i
++) {
1009 if ((get_field(env
->mcounteren
, BIT(i
))) &&
1010 (mhpm_evt_val
[i
] & of_bit_mask
)) {
1015 return RISCV_EXCP_NONE
;
1018 static RISCVException
read_time(CPURISCVState
*env
, int csrno
,
1021 uint64_t delta
= env
->virt_enabled
? env
->htimedelta
: 0;
1023 if (!env
->rdtime_fn
) {
1024 return RISCV_EXCP_ILLEGAL_INST
;
1027 *val
= env
->rdtime_fn(env
->rdtime_fn_arg
) + delta
;
1028 return RISCV_EXCP_NONE
;
1031 static RISCVException
read_timeh(CPURISCVState
*env
, int csrno
,
1034 uint64_t delta
= env
->virt_enabled
? env
->htimedelta
: 0;
1036 if (!env
->rdtime_fn
) {
1037 return RISCV_EXCP_ILLEGAL_INST
;
1040 *val
= (env
->rdtime_fn(env
->rdtime_fn_arg
) + delta
) >> 32;
1041 return RISCV_EXCP_NONE
;
1044 static RISCVException
read_vstimecmp(CPURISCVState
*env
, int csrno
,
1047 *val
= env
->vstimecmp
;
1049 return RISCV_EXCP_NONE
;
1052 static RISCVException
read_vstimecmph(CPURISCVState
*env
, int csrno
,
1055 *val
= env
->vstimecmp
>> 32;
1057 return RISCV_EXCP_NONE
;
1060 static RISCVException
write_vstimecmp(CPURISCVState
*env
, int csrno
,
1063 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
1064 env
->vstimecmp
= deposit64(env
->vstimecmp
, 0, 32, (uint64_t)val
);
1066 env
->vstimecmp
= val
;
1069 riscv_timer_write_timecmp(env
, env
->vstimer
, env
->vstimecmp
,
1070 env
->htimedelta
, MIP_VSTIP
);
1072 return RISCV_EXCP_NONE
;
1075 static RISCVException
write_vstimecmph(CPURISCVState
*env
, int csrno
,
1078 env
->vstimecmp
= deposit64(env
->vstimecmp
, 32, 32, (uint64_t)val
);
1079 riscv_timer_write_timecmp(env
, env
->vstimer
, env
->vstimecmp
,
1080 env
->htimedelta
, MIP_VSTIP
);
1082 return RISCV_EXCP_NONE
;
1085 static RISCVException
read_stimecmp(CPURISCVState
*env
, int csrno
,
1088 if (env
->virt_enabled
) {
1089 *val
= env
->vstimecmp
;
1091 *val
= env
->stimecmp
;
1094 return RISCV_EXCP_NONE
;
1097 static RISCVException
read_stimecmph(CPURISCVState
*env
, int csrno
,
1100 if (env
->virt_enabled
) {
1101 *val
= env
->vstimecmp
>> 32;
1103 *val
= env
->stimecmp
>> 32;
1106 return RISCV_EXCP_NONE
;
1109 static RISCVException
write_stimecmp(CPURISCVState
*env
, int csrno
,
1112 if (env
->virt_enabled
) {
1113 if (env
->hvictl
& HVICTL_VTI
) {
1114 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
1116 return write_vstimecmp(env
, csrno
, val
);
1119 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
1120 env
->stimecmp
= deposit64(env
->stimecmp
, 0, 32, (uint64_t)val
);
1122 env
->stimecmp
= val
;
1125 riscv_timer_write_timecmp(env
, env
->stimer
, env
->stimecmp
, 0, MIP_STIP
);
1127 return RISCV_EXCP_NONE
;
1130 static RISCVException
write_stimecmph(CPURISCVState
*env
, int csrno
,
1133 if (env
->virt_enabled
) {
1134 if (env
->hvictl
& HVICTL_VTI
) {
1135 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
1137 return write_vstimecmph(env
, csrno
, val
);
1140 env
->stimecmp
= deposit64(env
->stimecmp
, 32, 32, (uint64_t)val
);
1141 riscv_timer_write_timecmp(env
, env
->stimer
, env
->stimecmp
, 0, MIP_STIP
);
1143 return RISCV_EXCP_NONE
;
1146 #define VSTOPI_NUM_SRCS 5
1148 #define LOCAL_INTERRUPTS (~0x1FFF)
1150 static const uint64_t delegable_ints
=
1151 S_MODE_INTERRUPTS
| VS_MODE_INTERRUPTS
| MIP_LCOFIP
;
1152 static const uint64_t vs_delegable_ints
=
1153 (VS_MODE_INTERRUPTS
| LOCAL_INTERRUPTS
) & ~MIP_LCOFIP
;
1154 static const uint64_t all_ints
= M_MODE_INTERRUPTS
| S_MODE_INTERRUPTS
|
1155 HS_MODE_INTERRUPTS
| LOCAL_INTERRUPTS
;
1156 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
1157 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
1158 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
1159 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
1160 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
1161 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
1162 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
1163 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
1164 (1ULL << (RISCV_EXCP_U_ECALL)) | \
1165 (1ULL << (RISCV_EXCP_S_ECALL)) | \
1166 (1ULL << (RISCV_EXCP_VS_ECALL)) | \
1167 (1ULL << (RISCV_EXCP_M_ECALL)) | \
1168 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
1169 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
1170 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
1171 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
1172 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
1173 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
1174 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
1175 static const target_ulong vs_delegable_excps
= DELEGABLE_EXCPS
&
1176 ~((1ULL << (RISCV_EXCP_S_ECALL
)) |
1177 (1ULL << (RISCV_EXCP_VS_ECALL
)) |
1178 (1ULL << (RISCV_EXCP_M_ECALL
)) |
1179 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT
)) |
1180 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT
)) |
1181 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT
)) |
1182 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT
)));
1183 static const target_ulong sstatus_v1_10_mask
= SSTATUS_SIE
| SSTATUS_SPIE
|
1184 SSTATUS_UIE
| SSTATUS_UPIE
| SSTATUS_SPP
| SSTATUS_FS
| SSTATUS_XS
|
1185 SSTATUS_SUM
| SSTATUS_MXR
| SSTATUS_VS
;
1188 * Spec allows for bits 13:63 to be either read-only or writable.
1189 * So far we have interrupt LCOFIP in that region which is writable.
1191 * Also, spec allows to inject virtual interrupts in this region even
1192 * without any hardware interrupts for that interrupt number.
1194 * For now interrupt in 13:63 region are all kept writable. 13 being
1195 * LCOFIP and 14:63 being virtual only. Change this in future if we
1196 * introduce more interrupts that are not writable.
1199 /* Bit STIP can be an alias of mip.STIP that's why it's writable in mvip. */
1200 static const target_ulong mvip_writable_mask
= MIP_SSIP
| MIP_STIP
| MIP_SEIP
|
1202 static const target_ulong mvien_writable_mask
= MIP_SSIP
| MIP_SEIP
|
1205 static const target_ulong sip_writable_mask
= SIP_SSIP
| LOCAL_INTERRUPTS
;
1206 static const target_ulong hip_writable_mask
= MIP_VSSIP
;
1207 static const target_ulong hvip_writable_mask
= MIP_VSSIP
| MIP_VSTIP
|
1208 MIP_VSEIP
| LOCAL_INTERRUPTS
;
1209 static const target_ulong hvien_writable_mask
= LOCAL_INTERRUPTS
;
1211 static const target_ulong vsip_writable_mask
= MIP_VSSIP
| LOCAL_INTERRUPTS
;
1213 const bool valid_vm_1_10_32
[16] = {
1214 [VM_1_10_MBARE
] = true,
1215 [VM_1_10_SV32
] = true
1218 const bool valid_vm_1_10_64
[16] = {
1219 [VM_1_10_MBARE
] = true,
1220 [VM_1_10_SV39
] = true,
1221 [VM_1_10_SV48
] = true,
1222 [VM_1_10_SV57
] = true
1225 /* Machine Information Registers */
1226 static RISCVException
read_zero(CPURISCVState
*env
, int csrno
,
1230 return RISCV_EXCP_NONE
;
1233 static RISCVException
write_ignore(CPURISCVState
*env
, int csrno
,
1236 return RISCV_EXCP_NONE
;
1239 static RISCVException
read_mvendorid(CPURISCVState
*env
, int csrno
,
1242 *val
= riscv_cpu_cfg(env
)->mvendorid
;
1243 return RISCV_EXCP_NONE
;
1246 static RISCVException
read_marchid(CPURISCVState
*env
, int csrno
,
1249 *val
= riscv_cpu_cfg(env
)->marchid
;
1250 return RISCV_EXCP_NONE
;
1253 static RISCVException
read_mimpid(CPURISCVState
*env
, int csrno
,
1256 *val
= riscv_cpu_cfg(env
)->mimpid
;
1257 return RISCV_EXCP_NONE
;
1260 static RISCVException
read_mhartid(CPURISCVState
*env
, int csrno
,
1263 *val
= env
->mhartid
;
1264 return RISCV_EXCP_NONE
;
1267 /* Machine Trap Setup */
1269 /* We do not store SD explicitly, only compute it on demand. */
1270 static uint64_t add_status_sd(RISCVMXL xl
, uint64_t status
)
1272 if ((status
& MSTATUS_FS
) == MSTATUS_FS
||
1273 (status
& MSTATUS_VS
) == MSTATUS_VS
||
1274 (status
& MSTATUS_XS
) == MSTATUS_XS
) {
1277 return status
| MSTATUS32_SD
;
1279 return status
| MSTATUS64_SD
;
1281 return MSTATUSH128_SD
;
1283 g_assert_not_reached();
1289 static RISCVException
read_mstatus(CPURISCVState
*env
, int csrno
,
1292 *val
= add_status_sd(riscv_cpu_mxl(env
), env
->mstatus
);
1293 return RISCV_EXCP_NONE
;
1296 static bool validate_vm(CPURISCVState
*env
, target_ulong vm
)
1298 uint64_t mode_supported
= riscv_cpu_cfg(env
)->satp_mode
.map
;
1299 return get_field(mode_supported
, (1 << vm
));
1302 static target_ulong
legalize_xatp(CPURISCVState
*env
, target_ulong old_xatp
,
1307 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
1308 vm
= validate_vm(env
, get_field(val
, SATP32_MODE
));
1309 mask
= (val
^ old_xatp
) & (SATP32_MODE
| SATP32_ASID
| SATP32_PPN
);
1311 vm
= validate_vm(env
, get_field(val
, SATP64_MODE
));
1312 mask
= (val
^ old_xatp
) & (SATP64_MODE
| SATP64_ASID
| SATP64_PPN
);
1317 * The ISA defines SATP.MODE=Bare as "no translation", but we still
1318 * pass these through QEMU's TLB emulation as it improves
1319 * performance. Flushing the TLB on SATP writes with paging
1320 * enabled avoids leaking those invalid cached mappings.
1322 tlb_flush(env_cpu(env
));
1328 static target_ulong
legalize_mpp(CPURISCVState
*env
, target_ulong old_mpp
,
1332 target_ulong new_mpp
= get_field(val
, MSTATUS_MPP
);
1339 valid
= riscv_has_ext(env
, RVS
);
1342 valid
= riscv_has_ext(env
, RVU
);
1346 /* Remain field unchanged if new_mpp value is invalid */
1348 val
= set_field(val
, MSTATUS_MPP
, old_mpp
);
1354 static RISCVException
write_mstatus(CPURISCVState
*env
, int csrno
,
1357 uint64_t mstatus
= env
->mstatus
;
1359 RISCVMXL xl
= riscv_cpu_mxl(env
);
1362 * MPP field have been made WARL since priv version 1.11. However,
1363 * legalization for it will not break any software running on 1.10.
1365 val
= legalize_mpp(env
, get_field(mstatus
, MSTATUS_MPP
), val
);
1367 /* flush tlb on mstatus fields that affect VM */
1368 if ((val
^ mstatus
) & MSTATUS_MXR
) {
1369 tlb_flush(env_cpu(env
));
1371 mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
|
1372 MSTATUS_SPP
| MSTATUS_MPRV
| MSTATUS_SUM
|
1373 MSTATUS_MPP
| MSTATUS_MXR
| MSTATUS_TVM
| MSTATUS_TSR
|
1376 if (riscv_has_ext(env
, RVF
)) {
1379 if (riscv_has_ext(env
, RVV
)) {
1383 if (xl
!= MXL_RV32
|| env
->debugger
) {
1384 if (riscv_has_ext(env
, RVH
)) {
1385 mask
|= MSTATUS_MPV
| MSTATUS_GVA
;
1387 if ((val
& MSTATUS64_UXL
) != 0) {
1388 mask
|= MSTATUS64_UXL
;
1392 mstatus
= (mstatus
& ~mask
) | (val
& mask
);
1394 env
->mstatus
= mstatus
;
1397 * Except in debug mode, UXL/SXL can only be modified by higher
1398 * privilege mode. So xl will not be changed in normal mode.
1400 if (env
->debugger
) {
1401 env
->xl
= cpu_recompute_xl(env
);
1404 riscv_cpu_update_mask(env
);
1405 return RISCV_EXCP_NONE
;
1408 static RISCVException
read_mstatush(CPURISCVState
*env
, int csrno
,
1411 *val
= env
->mstatus
>> 32;
1412 return RISCV_EXCP_NONE
;
1415 static RISCVException
write_mstatush(CPURISCVState
*env
, int csrno
,
1418 uint64_t valh
= (uint64_t)val
<< 32;
1419 uint64_t mask
= riscv_has_ext(env
, RVH
) ? MSTATUS_MPV
| MSTATUS_GVA
: 0;
1421 env
->mstatus
= (env
->mstatus
& ~mask
) | (valh
& mask
);
1423 return RISCV_EXCP_NONE
;
1426 static RISCVException
read_mstatus_i128(CPURISCVState
*env
, int csrno
,
1429 *val
= int128_make128(env
->mstatus
, add_status_sd(MXL_RV128
,
1431 return RISCV_EXCP_NONE
;
1434 static RISCVException
read_misa_i128(CPURISCVState
*env
, int csrno
,
1437 *val
= int128_make128(env
->misa_ext
, (uint64_t)MXL_RV128
<< 62);
1438 return RISCV_EXCP_NONE
;
1441 static RISCVException
read_misa(CPURISCVState
*env
, int csrno
,
1446 switch (env
->misa_mxl
) {
1448 misa
= (target_ulong
)MXL_RV32
<< 30;
1450 #ifdef TARGET_RISCV64
1452 misa
= (target_ulong
)MXL_RV64
<< 62;
1456 g_assert_not_reached();
1459 *val
= misa
| env
->misa_ext
;
1460 return RISCV_EXCP_NONE
;
1463 static RISCVException
write_misa(CPURISCVState
*env
, int csrno
,
1466 RISCVCPU
*cpu
= env_archcpu(env
);
1467 uint32_t orig_misa_ext
= env
->misa_ext
;
1468 Error
*local_err
= NULL
;
1470 if (!riscv_cpu_cfg(env
)->misa_w
) {
1471 /* drop write to misa */
1472 return RISCV_EXCP_NONE
;
1475 /* Mask extensions that are not supported by this hart */
1476 val
&= env
->misa_ext_mask
;
1479 * Suppress 'C' if next instruction is not aligned
1480 * TODO: this should check next_pc
1482 if ((val
& RVC
) && (GETPC() & ~3) != 0) {
1486 /* Disable RVG if any of its dependencies are disabled */
1487 if (!(val
& RVI
&& val
& RVM
&& val
& RVA
&&
1488 val
& RVF
&& val
& RVD
)) {
1492 /* If nothing changed, do nothing. */
1493 if (val
== env
->misa_ext
) {
1494 return RISCV_EXCP_NONE
;
1497 env
->misa_ext
= val
;
1498 riscv_cpu_validate_set_extensions(cpu
, &local_err
);
1499 if (local_err
!= NULL
) {
1500 /* Rollback on validation error */
1501 qemu_log_mask(LOG_GUEST_ERROR
, "Unable to write MISA ext value "
1502 "0x%x, keeping existing MISA ext 0x%x\n",
1503 env
->misa_ext
, orig_misa_ext
);
1505 env
->misa_ext
= orig_misa_ext
;
1507 return RISCV_EXCP_NONE
;
1510 if (!(env
->misa_ext
& RVF
)) {
1511 env
->mstatus
&= ~MSTATUS_FS
;
1514 /* flush translation cache */
1515 tb_flush(env_cpu(env
));
1516 env
->xl
= riscv_cpu_mxl(env
);
1517 return RISCV_EXCP_NONE
;
1520 static RISCVException
read_medeleg(CPURISCVState
*env
, int csrno
,
1523 *val
= env
->medeleg
;
1524 return RISCV_EXCP_NONE
;
1527 static RISCVException
write_medeleg(CPURISCVState
*env
, int csrno
,
1530 env
->medeleg
= (env
->medeleg
& ~DELEGABLE_EXCPS
) | (val
& DELEGABLE_EXCPS
);
1531 return RISCV_EXCP_NONE
;
1534 static RISCVException
rmw_mideleg64(CPURISCVState
*env
, int csrno
,
1536 uint64_t new_val
, uint64_t wr_mask
)
1538 uint64_t mask
= wr_mask
& delegable_ints
;
1541 *ret_val
= env
->mideleg
;
1544 env
->mideleg
= (env
->mideleg
& ~mask
) | (new_val
& mask
);
1546 if (riscv_has_ext(env
, RVH
)) {
1547 env
->mideleg
|= HS_MODE_INTERRUPTS
;
1550 return RISCV_EXCP_NONE
;
1553 static RISCVException
rmw_mideleg(CPURISCVState
*env
, int csrno
,
1554 target_ulong
*ret_val
,
1555 target_ulong new_val
, target_ulong wr_mask
)
1560 ret
= rmw_mideleg64(env
, csrno
, &rval
, new_val
, wr_mask
);
1568 static RISCVException
rmw_midelegh(CPURISCVState
*env
, int csrno
,
1569 target_ulong
*ret_val
,
1570 target_ulong new_val
,
1571 target_ulong wr_mask
)
1576 ret
= rmw_mideleg64(env
, csrno
, &rval
,
1577 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
1579 *ret_val
= rval
>> 32;
1585 static RISCVException
rmw_mie64(CPURISCVState
*env
, int csrno
,
1587 uint64_t new_val
, uint64_t wr_mask
)
1589 uint64_t mask
= wr_mask
& all_ints
;
1592 *ret_val
= env
->mie
;
1595 env
->mie
= (env
->mie
& ~mask
) | (new_val
& mask
);
1597 if (!riscv_has_ext(env
, RVH
)) {
1598 env
->mie
&= ~((uint64_t)HS_MODE_INTERRUPTS
);
1601 return RISCV_EXCP_NONE
;
1604 static RISCVException
rmw_mie(CPURISCVState
*env
, int csrno
,
1605 target_ulong
*ret_val
,
1606 target_ulong new_val
, target_ulong wr_mask
)
1611 ret
= rmw_mie64(env
, csrno
, &rval
, new_val
, wr_mask
);
1619 static RISCVException
rmw_mieh(CPURISCVState
*env
, int csrno
,
1620 target_ulong
*ret_val
,
1621 target_ulong new_val
, target_ulong wr_mask
)
1626 ret
= rmw_mie64(env
, csrno
, &rval
,
1627 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
1629 *ret_val
= rval
>> 32;
1635 static RISCVException
rmw_mvien64(CPURISCVState
*env
, int csrno
,
1637 uint64_t new_val
, uint64_t wr_mask
)
1639 uint64_t mask
= wr_mask
& mvien_writable_mask
;
1642 *ret_val
= env
->mvien
;
1645 env
->mvien
= (env
->mvien
& ~mask
) | (new_val
& mask
);
1647 return RISCV_EXCP_NONE
;
1650 static RISCVException
rmw_mvien(CPURISCVState
*env
, int csrno
,
1651 target_ulong
*ret_val
,
1652 target_ulong new_val
, target_ulong wr_mask
)
1657 ret
= rmw_mvien64(env
, csrno
, &rval
, new_val
, wr_mask
);
1665 static RISCVException
rmw_mvienh(CPURISCVState
*env
, int csrno
,
1666 target_ulong
*ret_val
,
1667 target_ulong new_val
, target_ulong wr_mask
)
1672 ret
= rmw_mvien64(env
, csrno
, &rval
,
1673 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
1675 *ret_val
= rval
>> 32;
1681 static RISCVException
read_mtopi(CPURISCVState
*env
, int csrno
,
1687 irq
= riscv_cpu_mirq_pending(env
);
1688 if (irq
<= 0 || irq
> 63) {
1691 iprio
= env
->miprio
[irq
];
1693 if (riscv_cpu_default_priority(irq
) > IPRIO_DEFAULT_M
) {
1694 iprio
= IPRIO_MMAXIPRIO
;
1697 *val
= (irq
& TOPI_IID_MASK
) << TOPI_IID_SHIFT
;
1701 return RISCV_EXCP_NONE
;
1704 static int aia_xlate_vs_csrno(CPURISCVState
*env
, int csrno
)
1706 if (!env
->virt_enabled
) {
1712 return CSR_VSISELECT
;
1722 static RISCVException
rmw_xiselect(CPURISCVState
*env
, int csrno
,
1723 target_ulong
*val
, target_ulong new_val
,
1724 target_ulong wr_mask
)
1726 target_ulong
*iselect
;
1728 /* Translate CSR number for VS-mode */
1729 csrno
= aia_xlate_vs_csrno(env
, csrno
);
1731 /* Find the iselect CSR based on CSR number */
1734 iselect
= &env
->miselect
;
1737 iselect
= &env
->siselect
;
1740 iselect
= &env
->vsiselect
;
1743 return RISCV_EXCP_ILLEGAL_INST
;
1750 wr_mask
&= ISELECT_MASK
;
1752 *iselect
= (*iselect
& ~wr_mask
) | (new_val
& wr_mask
);
1755 return RISCV_EXCP_NONE
;
1758 static int rmw_iprio(target_ulong xlen
,
1759 target_ulong iselect
, uint8_t *iprio
,
1760 target_ulong
*val
, target_ulong new_val
,
1761 target_ulong wr_mask
, int ext_irq_no
)
1764 target_ulong old_val
;
1766 if (iselect
< ISELECT_IPRIO0
|| ISELECT_IPRIO15
< iselect
) {
1769 if (xlen
!= 32 && iselect
& 0x1) {
1773 nirqs
= 4 * (xlen
/ 32);
1774 firq
= ((iselect
- ISELECT_IPRIO0
) / (xlen
/ 32)) * (nirqs
);
1777 for (i
= 0; i
< nirqs
; i
++) {
1778 old_val
|= ((target_ulong
)iprio
[firq
+ i
]) << (IPRIO_IRQ_BITS
* i
);
1786 new_val
= (old_val
& ~wr_mask
) | (new_val
& wr_mask
);
1787 for (i
= 0; i
< nirqs
; i
++) {
1789 * M-level and S-level external IRQ priority always read-only
1790 * zero. This means default priority order is always preferred
1791 * for M-level and S-level external IRQs.
1793 if ((firq
+ i
) == ext_irq_no
) {
1796 iprio
[firq
+ i
] = (new_val
>> (IPRIO_IRQ_BITS
* i
)) & 0xff;
1803 static RISCVException
rmw_xireg(CPURISCVState
*env
, int csrno
,
1804 target_ulong
*val
, target_ulong new_val
,
1805 target_ulong wr_mask
)
1807 bool virt
, isel_reserved
;
1810 target_ulong priv
, isel
, vgein
;
1812 /* Translate CSR number for VS-mode */
1813 csrno
= aia_xlate_vs_csrno(env
, csrno
);
1815 /* Decode register details from CSR number */
1817 isel_reserved
= false;
1820 iprio
= env
->miprio
;
1821 isel
= env
->miselect
;
1825 if (env
->priv
== PRV_S
&& env
->mvien
& MIP_SEIP
&&
1826 env
->siselect
>= ISELECT_IMSIC_EIDELIVERY
&&
1827 env
->siselect
<= ISELECT_IMSIC_EIE63
) {
1830 iprio
= env
->siprio
;
1831 isel
= env
->siselect
;
1835 iprio
= env
->hviprio
;
1836 isel
= env
->vsiselect
;
1844 /* Find the selected guest interrupt file */
1845 vgein
= (virt
) ? get_field(env
->hstatus
, HSTATUS_VGEIN
) : 0;
1847 if (ISELECT_IPRIO0
<= isel
&& isel
<= ISELECT_IPRIO15
) {
1848 /* Local interrupt priority registers not available for VS-mode */
1850 ret
= rmw_iprio(riscv_cpu_mxl_bits(env
),
1851 isel
, iprio
, val
, new_val
, wr_mask
,
1852 (priv
== PRV_M
) ? IRQ_M_EXT
: IRQ_S_EXT
);
1854 } else if (ISELECT_IMSIC_FIRST
<= isel
&& isel
<= ISELECT_IMSIC_LAST
) {
1855 /* IMSIC registers only available when machine implements it. */
1856 if (env
->aia_ireg_rmw_fn
[priv
]) {
1857 /* Selected guest interrupt file should not be zero */
1858 if (virt
&& (!vgein
|| env
->geilen
< vgein
)) {
1861 /* Call machine specific IMSIC register emulation */
1862 ret
= env
->aia_ireg_rmw_fn
[priv
](env
->aia_ireg_rmw_fn_arg
[priv
],
1863 AIA_MAKE_IREG(isel
, priv
, virt
, vgein
,
1864 riscv_cpu_mxl_bits(env
)),
1865 val
, new_val
, wr_mask
);
1868 isel_reserved
= true;
1873 return (env
->virt_enabled
&& virt
&& !isel_reserved
) ?
1874 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
1876 return RISCV_EXCP_NONE
;
1879 static RISCVException
rmw_xtopei(CPURISCVState
*env
, int csrno
,
1880 target_ulong
*val
, target_ulong new_val
,
1881 target_ulong wr_mask
)
1885 target_ulong priv
, vgein
;
1887 /* Translate CSR number for VS-mode */
1888 csrno
= aia_xlate_vs_csrno(env
, csrno
);
1890 /* Decode register details from CSR number */
1897 if (env
->mvien
& MIP_SEIP
&& env
->priv
== PRV_S
) {
1910 /* IMSIC CSRs only available when machine implements IMSIC. */
1911 if (!env
->aia_ireg_rmw_fn
[priv
]) {
1915 /* Find the selected guest interrupt file */
1916 vgein
= (virt
) ? get_field(env
->hstatus
, HSTATUS_VGEIN
) : 0;
1918 /* Selected guest interrupt file should be valid */
1919 if (virt
&& (!vgein
|| env
->geilen
< vgein
)) {
1923 /* Call machine specific IMSIC register emulation for TOPEI */
1924 ret
= env
->aia_ireg_rmw_fn
[priv
](env
->aia_ireg_rmw_fn_arg
[priv
],
1925 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI
, priv
, virt
, vgein
,
1926 riscv_cpu_mxl_bits(env
)),
1927 val
, new_val
, wr_mask
);
1931 return (env
->virt_enabled
&& virt
) ?
1932 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
1934 return RISCV_EXCP_NONE
;
1937 static RISCVException
read_mtvec(CPURISCVState
*env
, int csrno
,
1941 return RISCV_EXCP_NONE
;
1944 static RISCVException
write_mtvec(CPURISCVState
*env
, int csrno
,
1947 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
1948 if ((val
& 3) < 2) {
1951 qemu_log_mask(LOG_UNIMP
, "CSR_MTVEC: reserved mode not supported\n");
1953 return RISCV_EXCP_NONE
;
1956 static RISCVException
read_mcountinhibit(CPURISCVState
*env
, int csrno
,
1959 *val
= env
->mcountinhibit
;
1960 return RISCV_EXCP_NONE
;
1963 static RISCVException
write_mcountinhibit(CPURISCVState
*env
, int csrno
,
1967 PMUCTRState
*counter
;
1968 RISCVCPU
*cpu
= env_archcpu(env
);
1970 /* WARL register - disable unavailable counters; TM bit is always 0 */
1971 env
->mcountinhibit
=
1972 val
& (cpu
->pmu_avail_ctrs
| COUNTEREN_CY
| COUNTEREN_IR
);
1974 /* Check if any other counter is also monitoring cycles/instructions */
1975 for (cidx
= 0; cidx
< RV_MAX_MHPMCOUNTERS
; cidx
++) {
1976 if (!get_field(env
->mcountinhibit
, BIT(cidx
))) {
1977 counter
= &env
->pmu_ctrs
[cidx
];
1978 counter
->started
= true;
1982 return RISCV_EXCP_NONE
;
1985 static RISCVException
read_mcounteren(CPURISCVState
*env
, int csrno
,
1988 *val
= env
->mcounteren
;
1989 return RISCV_EXCP_NONE
;
1992 static RISCVException
write_mcounteren(CPURISCVState
*env
, int csrno
,
1995 RISCVCPU
*cpu
= env_archcpu(env
);
1997 /* WARL register - disable unavailable counters */
1998 env
->mcounteren
= val
& (cpu
->pmu_avail_ctrs
| COUNTEREN_CY
| COUNTEREN_TM
|
2000 return RISCV_EXCP_NONE
;
2003 /* Machine Trap Handling */
2004 static RISCVException
read_mscratch_i128(CPURISCVState
*env
, int csrno
,
2007 *val
= int128_make128(env
->mscratch
, env
->mscratchh
);
2008 return RISCV_EXCP_NONE
;
2011 static RISCVException
write_mscratch_i128(CPURISCVState
*env
, int csrno
,
2014 env
->mscratch
= int128_getlo(val
);
2015 env
->mscratchh
= int128_gethi(val
);
2016 return RISCV_EXCP_NONE
;
2019 static RISCVException
read_mscratch(CPURISCVState
*env
, int csrno
,
2022 *val
= env
->mscratch
;
2023 return RISCV_EXCP_NONE
;
2026 static RISCVException
write_mscratch(CPURISCVState
*env
, int csrno
,
2029 env
->mscratch
= val
;
2030 return RISCV_EXCP_NONE
;
2033 static RISCVException
read_mepc(CPURISCVState
*env
, int csrno
,
2037 return RISCV_EXCP_NONE
;
2040 static RISCVException
write_mepc(CPURISCVState
*env
, int csrno
,
2044 return RISCV_EXCP_NONE
;
2047 static RISCVException
read_mcause(CPURISCVState
*env
, int csrno
,
2051 return RISCV_EXCP_NONE
;
2054 static RISCVException
write_mcause(CPURISCVState
*env
, int csrno
,
2058 return RISCV_EXCP_NONE
;
2061 static RISCVException
read_mtval(CPURISCVState
*env
, int csrno
,
2065 return RISCV_EXCP_NONE
;
2068 static RISCVException
write_mtval(CPURISCVState
*env
, int csrno
,
2072 return RISCV_EXCP_NONE
;
2075 /* Execution environment configuration setup */
2076 static RISCVException
read_menvcfg(CPURISCVState
*env
, int csrno
,
2079 *val
= env
->menvcfg
;
2080 return RISCV_EXCP_NONE
;
2083 static RISCVException
write_menvcfg(CPURISCVState
*env
, int csrno
,
2086 const RISCVCPUConfig
*cfg
= riscv_cpu_cfg(env
);
2087 uint64_t mask
= MENVCFG_FIOM
| MENVCFG_CBIE
| MENVCFG_CBCFE
| MENVCFG_CBZE
;
2089 if (riscv_cpu_mxl(env
) == MXL_RV64
) {
2090 mask
|= (cfg
->ext_svpbmt
? MENVCFG_PBMTE
: 0) |
2091 (cfg
->ext_sstc
? MENVCFG_STCE
: 0) |
2092 (cfg
->ext_svadu
? MENVCFG_ADUE
: 0);
2094 env
->menvcfg
= (env
->menvcfg
& ~mask
) | (val
& mask
);
2096 return RISCV_EXCP_NONE
;
2099 static RISCVException
read_menvcfgh(CPURISCVState
*env
, int csrno
,
2102 *val
= env
->menvcfg
>> 32;
2103 return RISCV_EXCP_NONE
;
2106 static RISCVException
write_menvcfgh(CPURISCVState
*env
, int csrno
,
2109 const RISCVCPUConfig
*cfg
= riscv_cpu_cfg(env
);
2110 uint64_t mask
= (cfg
->ext_svpbmt
? MENVCFG_PBMTE
: 0) |
2111 (cfg
->ext_sstc
? MENVCFG_STCE
: 0) |
2112 (cfg
->ext_svadu
? MENVCFG_ADUE
: 0);
2113 uint64_t valh
= (uint64_t)val
<< 32;
2115 env
->menvcfg
= (env
->menvcfg
& ~mask
) | (valh
& mask
);
2117 return RISCV_EXCP_NONE
;
2120 static RISCVException
read_senvcfg(CPURISCVState
*env
, int csrno
,
2125 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
2126 if (ret
!= RISCV_EXCP_NONE
) {
2130 *val
= env
->senvcfg
;
2131 return RISCV_EXCP_NONE
;
2134 static RISCVException
write_senvcfg(CPURISCVState
*env
, int csrno
,
2137 uint64_t mask
= SENVCFG_FIOM
| SENVCFG_CBIE
| SENVCFG_CBCFE
| SENVCFG_CBZE
;
2140 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
2141 if (ret
!= RISCV_EXCP_NONE
) {
2145 env
->senvcfg
= (env
->senvcfg
& ~mask
) | (val
& mask
);
2146 return RISCV_EXCP_NONE
;
2149 static RISCVException
read_henvcfg(CPURISCVState
*env
, int csrno
,
2154 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
2155 if (ret
!= RISCV_EXCP_NONE
) {
2160 * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
2161 * henvcfg.stce is read_only 0 when menvcfg.stce = 0
2162 * henvcfg.adue is read_only 0 when menvcfg.adue = 0
2164 *val
= env
->henvcfg
& (~(HENVCFG_PBMTE
| HENVCFG_STCE
| HENVCFG_ADUE
) |
2166 return RISCV_EXCP_NONE
;
2169 static RISCVException
write_henvcfg(CPURISCVState
*env
, int csrno
,
2172 uint64_t mask
= HENVCFG_FIOM
| HENVCFG_CBIE
| HENVCFG_CBCFE
| HENVCFG_CBZE
;
2175 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
2176 if (ret
!= RISCV_EXCP_NONE
) {
2180 if (riscv_cpu_mxl(env
) == MXL_RV64
) {
2181 mask
|= env
->menvcfg
& (HENVCFG_PBMTE
| HENVCFG_STCE
| HENVCFG_ADUE
);
2184 env
->henvcfg
= (env
->henvcfg
& ~mask
) | (val
& mask
);
2186 return RISCV_EXCP_NONE
;
2189 static RISCVException
read_henvcfgh(CPURISCVState
*env
, int csrno
,
2194 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
2195 if (ret
!= RISCV_EXCP_NONE
) {
2199 *val
= (env
->henvcfg
& (~(HENVCFG_PBMTE
| HENVCFG_STCE
| HENVCFG_ADUE
) |
2200 env
->menvcfg
)) >> 32;
2201 return RISCV_EXCP_NONE
;
2204 static RISCVException
write_henvcfgh(CPURISCVState
*env
, int csrno
,
2207 uint64_t mask
= env
->menvcfg
& (HENVCFG_PBMTE
| HENVCFG_STCE
|
2209 uint64_t valh
= (uint64_t)val
<< 32;
2212 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
2213 if (ret
!= RISCV_EXCP_NONE
) {
2217 env
->henvcfg
= (env
->henvcfg
& ~mask
) | (valh
& mask
);
2218 return RISCV_EXCP_NONE
;
2221 static RISCVException
read_mstateen(CPURISCVState
*env
, int csrno
,
2224 *val
= env
->mstateen
[csrno
- CSR_MSTATEEN0
];
2226 return RISCV_EXCP_NONE
;
2229 static RISCVException
write_mstateen(CPURISCVState
*env
, int csrno
,
2230 uint64_t wr_mask
, target_ulong new_val
)
2234 reg
= &env
->mstateen
[csrno
- CSR_MSTATEEN0
];
2235 *reg
= (*reg
& ~wr_mask
) | (new_val
& wr_mask
);
2237 return RISCV_EXCP_NONE
;
2240 static RISCVException
write_mstateen0(CPURISCVState
*env
, int csrno
,
2241 target_ulong new_val
)
2243 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2244 if (!riscv_has_ext(env
, RVF
)) {
2245 wr_mask
|= SMSTATEEN0_FCSR
;
2248 return write_mstateen(env
, csrno
, wr_mask
, new_val
);
2251 static RISCVException
write_mstateen_1_3(CPURISCVState
*env
, int csrno
,
2252 target_ulong new_val
)
2254 return write_mstateen(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2257 static RISCVException
read_mstateenh(CPURISCVState
*env
, int csrno
,
2260 *val
= env
->mstateen
[csrno
- CSR_MSTATEEN0H
] >> 32;
2262 return RISCV_EXCP_NONE
;
2265 static RISCVException
write_mstateenh(CPURISCVState
*env
, int csrno
,
2266 uint64_t wr_mask
, target_ulong new_val
)
2270 reg
= &env
->mstateen
[csrno
- CSR_MSTATEEN0H
];
2271 val
= (uint64_t)new_val
<< 32;
2272 val
|= *reg
& 0xFFFFFFFF;
2273 *reg
= (*reg
& ~wr_mask
) | (val
& wr_mask
);
2275 return RISCV_EXCP_NONE
;
2278 static RISCVException
write_mstateen0h(CPURISCVState
*env
, int csrno
,
2279 target_ulong new_val
)
2281 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2283 return write_mstateenh(env
, csrno
, wr_mask
, new_val
);
2286 static RISCVException
write_mstateenh_1_3(CPURISCVState
*env
, int csrno
,
2287 target_ulong new_val
)
2289 return write_mstateenh(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2292 static RISCVException
read_hstateen(CPURISCVState
*env
, int csrno
,
2295 int index
= csrno
- CSR_HSTATEEN0
;
2297 *val
= env
->hstateen
[index
] & env
->mstateen
[index
];
2299 return RISCV_EXCP_NONE
;
2302 static RISCVException
write_hstateen(CPURISCVState
*env
, int csrno
,
2303 uint64_t mask
, target_ulong new_val
)
2305 int index
= csrno
- CSR_HSTATEEN0
;
2306 uint64_t *reg
, wr_mask
;
2308 reg
= &env
->hstateen
[index
];
2309 wr_mask
= env
->mstateen
[index
] & mask
;
2310 *reg
= (*reg
& ~wr_mask
) | (new_val
& wr_mask
);
2312 return RISCV_EXCP_NONE
;
2315 static RISCVException
write_hstateen0(CPURISCVState
*env
, int csrno
,
2316 target_ulong new_val
)
2318 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2320 if (!riscv_has_ext(env
, RVF
)) {
2321 wr_mask
|= SMSTATEEN0_FCSR
;
2324 return write_hstateen(env
, csrno
, wr_mask
, new_val
);
2327 static RISCVException
write_hstateen_1_3(CPURISCVState
*env
, int csrno
,
2328 target_ulong new_val
)
2330 return write_hstateen(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2333 static RISCVException
read_hstateenh(CPURISCVState
*env
, int csrno
,
2336 int index
= csrno
- CSR_HSTATEEN0H
;
2338 *val
= (env
->hstateen
[index
] >> 32) & (env
->mstateen
[index
] >> 32);
2340 return RISCV_EXCP_NONE
;
2343 static RISCVException
write_hstateenh(CPURISCVState
*env
, int csrno
,
2344 uint64_t mask
, target_ulong new_val
)
2346 int index
= csrno
- CSR_HSTATEEN0H
;
2347 uint64_t *reg
, wr_mask
, val
;
2349 reg
= &env
->hstateen
[index
];
2350 val
= (uint64_t)new_val
<< 32;
2351 val
|= *reg
& 0xFFFFFFFF;
2352 wr_mask
= env
->mstateen
[index
] & mask
;
2353 *reg
= (*reg
& ~wr_mask
) | (val
& wr_mask
);
2355 return RISCV_EXCP_NONE
;
2358 static RISCVException
write_hstateen0h(CPURISCVState
*env
, int csrno
,
2359 target_ulong new_val
)
2361 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2363 return write_hstateenh(env
, csrno
, wr_mask
, new_val
);
2366 static RISCVException
write_hstateenh_1_3(CPURISCVState
*env
, int csrno
,
2367 target_ulong new_val
)
2369 return write_hstateenh(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2372 static RISCVException
read_sstateen(CPURISCVState
*env
, int csrno
,
2375 bool virt
= env
->virt_enabled
;
2376 int index
= csrno
- CSR_SSTATEEN0
;
2378 *val
= env
->sstateen
[index
] & env
->mstateen
[index
];
2380 *val
&= env
->hstateen
[index
];
2383 return RISCV_EXCP_NONE
;
2386 static RISCVException
write_sstateen(CPURISCVState
*env
, int csrno
,
2387 uint64_t mask
, target_ulong new_val
)
2389 bool virt
= env
->virt_enabled
;
2390 int index
= csrno
- CSR_SSTATEEN0
;
2394 wr_mask
= env
->mstateen
[index
] & mask
;
2396 wr_mask
&= env
->hstateen
[index
];
2399 reg
= &env
->sstateen
[index
];
2400 *reg
= (*reg
& ~wr_mask
) | (new_val
& wr_mask
);
2402 return RISCV_EXCP_NONE
;
2405 static RISCVException
write_sstateen0(CPURISCVState
*env
, int csrno
,
2406 target_ulong new_val
)
2408 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2410 if (!riscv_has_ext(env
, RVF
)) {
2411 wr_mask
|= SMSTATEEN0_FCSR
;
2414 return write_sstateen(env
, csrno
, wr_mask
, new_val
);
2417 static RISCVException
write_sstateen_1_3(CPURISCVState
*env
, int csrno
,
2418 target_ulong new_val
)
2420 return write_sstateen(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2423 static RISCVException
rmw_mip64(CPURISCVState
*env
, int csrno
,
2425 uint64_t new_val
, uint64_t wr_mask
)
2427 uint64_t old_mip
, mask
= wr_mask
& delegable_ints
;
2430 if (mask
& MIP_SEIP
) {
2431 env
->software_seip
= new_val
& MIP_SEIP
;
2432 new_val
|= env
->external_seip
* MIP_SEIP
;
2435 if (riscv_cpu_cfg(env
)->ext_sstc
&& (env
->priv
== PRV_M
) &&
2436 get_field(env
->menvcfg
, MENVCFG_STCE
)) {
2437 /* sstc extension forbids STIP & VSTIP to be writeable in mip */
2438 mask
= mask
& ~(MIP_STIP
| MIP_VSTIP
);
2442 old_mip
= riscv_cpu_update_mip(env
, mask
, (new_val
& mask
));
2447 if (csrno
!= CSR_HVIP
) {
2448 gin
= get_field(env
->hstatus
, HSTATUS_VGEIN
);
2449 old_mip
|= (env
->hgeip
& ((target_ulong
)1 << gin
)) ? MIP_VSEIP
: 0;
2450 old_mip
|= env
->vstime_irq
? MIP_VSTIP
: 0;
2457 return RISCV_EXCP_NONE
;
2460 static RISCVException
rmw_mip(CPURISCVState
*env
, int csrno
,
2461 target_ulong
*ret_val
,
2462 target_ulong new_val
, target_ulong wr_mask
)
2467 ret
= rmw_mip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2475 static RISCVException
rmw_miph(CPURISCVState
*env
, int csrno
,
2476 target_ulong
*ret_val
,
2477 target_ulong new_val
, target_ulong wr_mask
)
2482 ret
= rmw_mip64(env
, csrno
, &rval
,
2483 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2485 *ret_val
= rval
>> 32;
2492 * The function is written for two use-cases:
2493 * 1- To access mvip csr as is for m-mode access.
2494 * 2- To access sip as a combination of mip and mvip for s-mode.
2496 * Both report bits 1, 5, 9 and 13:63 but with the exception of
2497 * STIP being read-only zero in case of mvip when sstc extension
2499 * Also, sip needs to be read-only zero when both mideleg[i] and
2500 * mvien[i] are zero but mvip needs to be an alias of mip.
2502 static RISCVException
rmw_mvip64(CPURISCVState
*env
, int csrno
,
2504 uint64_t new_val
, uint64_t wr_mask
)
2506 RISCVCPU
*cpu
= env_archcpu(env
);
2507 target_ulong ret_mip
= 0;
2512 * mideleg[i] mvien[i]
2513 * 0 0 No delegation. mvip[i] is alias of mip[i].
2514 * 0 1 mvip[i] becomes source of interrupt, mip bypassed.
2515 * 1 X mip[i] is source of interrupt and mvip[i] aliases
2518 * So alias condition would be for bits:
2519 * ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & (mideleg | ~mvien)) |
2520 * (!sstc & MIP_STIP)
2522 * Non-alias condition will be for bits:
2523 * (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & (~mideleg & mvien)
2525 * alias_mask denotes the bits that come from mip nalias_mask denotes bits
2526 * that come from hvip.
2528 uint64_t alias_mask
= ((S_MODE_INTERRUPTS
| LOCAL_INTERRUPTS
) &
2529 (env
->mideleg
| ~env
->mvien
)) | MIP_STIP
;
2530 uint64_t nalias_mask
= (S_MODE_INTERRUPTS
| LOCAL_INTERRUPTS
) &
2531 (~env
->mideleg
& env
->mvien
);
2532 uint64_t wr_mask_mvip
;
2533 uint64_t wr_mask_mip
;
2536 * mideleg[i] mvien[i]
2537 * 0 0 sip[i] read-only zero.
2538 * 0 1 sip[i] alias of mvip[i].
2539 * 1 X sip[i] alias of mip[i].
2541 * Both alias and non-alias mask remain same for sip except for bits
2542 * which are zero in both mideleg and mvien.
2544 if (csrno
== CSR_SIP
) {
2545 /* Remove bits that are zero in both mideleg and mvien. */
2546 alias_mask
&= (env
->mideleg
| env
->mvien
);
2547 nalias_mask
&= (env
->mideleg
| env
->mvien
);
2551 * If sstc is present, mvip.STIP is not an alias of mip.STIP so clear
2552 * that our in mip returned value.
2554 if (cpu
->cfg
.ext_sstc
&& (env
->priv
== PRV_M
) &&
2555 get_field(env
->menvcfg
, MENVCFG_STCE
)) {
2556 alias_mask
&= ~MIP_STIP
;
2559 wr_mask_mip
= wr_mask
& alias_mask
& mvip_writable_mask
;
2560 wr_mask_mvip
= wr_mask
& nalias_mask
& mvip_writable_mask
;
2563 * For bits set in alias_mask, mvip needs to be alias of mip, so forward
2566 ret
= rmw_mip(env
, CSR_MIP
, &ret_mip
, new_val
, wr_mask_mip
);
2567 if (ret
!= RISCV_EXCP_NONE
) {
2571 old_mvip
= env
->mvip
;
2574 * Write to mvip. Update only non-alias bits. Alias bits were updated
2575 * in mip in rmw_mip above.
2578 env
->mvip
= (env
->mvip
& ~wr_mask_mvip
) | (new_val
& wr_mask_mvip
);
2581 * Given mvip is separate source from mip, we need to trigger interrupt
2582 * from here separately. Normally this happen from riscv_cpu_update_mip.
2584 riscv_cpu_interrupt(env
);
2588 ret_mip
&= alias_mask
;
2589 old_mvip
&= nalias_mask
;
2591 *ret_val
= old_mvip
| ret_mip
;
2594 return RISCV_EXCP_NONE
;
2597 static RISCVException
rmw_mvip(CPURISCVState
*env
, int csrno
,
2598 target_ulong
*ret_val
,
2599 target_ulong new_val
, target_ulong wr_mask
)
2604 ret
= rmw_mvip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2612 static RISCVException
rmw_mviph(CPURISCVState
*env
, int csrno
,
2613 target_ulong
*ret_val
,
2614 target_ulong new_val
, target_ulong wr_mask
)
2619 ret
= rmw_mvip64(env
, csrno
, &rval
,
2620 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2622 *ret_val
= rval
>> 32;
2628 /* Supervisor Trap Setup */
2629 static RISCVException
read_sstatus_i128(CPURISCVState
*env
, int csrno
,
2632 uint64_t mask
= sstatus_v1_10_mask
;
2633 uint64_t sstatus
= env
->mstatus
& mask
;
2634 if (env
->xl
!= MXL_RV32
|| env
->debugger
) {
2635 mask
|= SSTATUS64_UXL
;
2638 *val
= int128_make128(sstatus
, add_status_sd(MXL_RV128
, sstatus
));
2639 return RISCV_EXCP_NONE
;
2642 static RISCVException
read_sstatus(CPURISCVState
*env
, int csrno
,
2645 target_ulong mask
= (sstatus_v1_10_mask
);
2646 if (env
->xl
!= MXL_RV32
|| env
->debugger
) {
2647 mask
|= SSTATUS64_UXL
;
2649 /* TODO: Use SXL not MXL. */
2650 *val
= add_status_sd(riscv_cpu_mxl(env
), env
->mstatus
& mask
);
2651 return RISCV_EXCP_NONE
;
2654 static RISCVException
write_sstatus(CPURISCVState
*env
, int csrno
,
2657 target_ulong mask
= (sstatus_v1_10_mask
);
2659 if (env
->xl
!= MXL_RV32
|| env
->debugger
) {
2660 if ((val
& SSTATUS64_UXL
) != 0) {
2661 mask
|= SSTATUS64_UXL
;
2664 target_ulong newval
= (env
->mstatus
& ~mask
) | (val
& mask
);
2665 return write_mstatus(env
, CSR_MSTATUS
, newval
);
2668 static RISCVException
rmw_vsie64(CPURISCVState
*env
, int csrno
,
2670 uint64_t new_val
, uint64_t wr_mask
)
2672 uint64_t alias_mask
= (LOCAL_INTERRUPTS
| VS_MODE_INTERRUPTS
) &
2674 uint64_t nalias_mask
= LOCAL_INTERRUPTS
& (~env
->hideleg
& env
->hvien
);
2675 uint64_t rval
, rval_vs
, vsbits
;
2676 uint64_t wr_mask_vsie
;
2677 uint64_t wr_mask_mie
;
2680 /* Bring VS-level bits to correct position */
2681 vsbits
= new_val
& (VS_MODE_INTERRUPTS
>> 1);
2682 new_val
&= ~(VS_MODE_INTERRUPTS
>> 1);
2683 new_val
|= vsbits
<< 1;
2685 vsbits
= wr_mask
& (VS_MODE_INTERRUPTS
>> 1);
2686 wr_mask
&= ~(VS_MODE_INTERRUPTS
>> 1);
2687 wr_mask
|= vsbits
<< 1;
2689 wr_mask_mie
= wr_mask
& alias_mask
;
2690 wr_mask_vsie
= wr_mask
& nalias_mask
;
2692 ret
= rmw_mie64(env
, csrno
, &rval
, new_val
, wr_mask_mie
);
2694 rval_vs
= env
->vsie
& nalias_mask
;
2695 env
->vsie
= (env
->vsie
& ~wr_mask_vsie
) | (new_val
& wr_mask_vsie
);
2699 vsbits
= rval
& VS_MODE_INTERRUPTS
;
2700 rval
&= ~VS_MODE_INTERRUPTS
;
2701 *ret_val
= rval
| (vsbits
>> 1) | rval_vs
;
2707 static RISCVException
rmw_vsie(CPURISCVState
*env
, int csrno
,
2708 target_ulong
*ret_val
,
2709 target_ulong new_val
, target_ulong wr_mask
)
2714 ret
= rmw_vsie64(env
, csrno
, &rval
, new_val
, wr_mask
);
2722 static RISCVException
rmw_vsieh(CPURISCVState
*env
, int csrno
,
2723 target_ulong
*ret_val
,
2724 target_ulong new_val
, target_ulong wr_mask
)
2729 ret
= rmw_vsie64(env
, csrno
, &rval
,
2730 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2732 *ret_val
= rval
>> 32;
2738 static RISCVException
rmw_sie64(CPURISCVState
*env
, int csrno
,
2740 uint64_t new_val
, uint64_t wr_mask
)
2742 uint64_t nalias_mask
= (S_MODE_INTERRUPTS
| LOCAL_INTERRUPTS
) &
2743 (~env
->mideleg
& env
->mvien
);
2744 uint64_t alias_mask
= (S_MODE_INTERRUPTS
| LOCAL_INTERRUPTS
) & env
->mideleg
;
2745 uint64_t sie_mask
= wr_mask
& nalias_mask
;
2749 * mideleg[i] mvien[i]
2750 * 0 0 sie[i] read-only zero.
2751 * 0 1 sie[i] is a separate writable bit.
2752 * 1 X sie[i] alias of mie[i].
2754 * Both alias and non-alias mask remain same for sip except for bits
2755 * which are zero in both mideleg and mvien.
2757 if (env
->virt_enabled
) {
2758 if (env
->hvictl
& HVICTL_VTI
) {
2759 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
2761 ret
= rmw_vsie64(env
, CSR_VSIE
, ret_val
, new_val
, wr_mask
);
2763 *ret_val
&= alias_mask
;
2766 ret
= rmw_mie64(env
, csrno
, ret_val
, new_val
, wr_mask
& alias_mask
);
2768 *ret_val
&= alias_mask
;
2769 *ret_val
|= env
->sie
& nalias_mask
;
2772 env
->sie
= (env
->sie
& ~sie_mask
) | (new_val
& sie_mask
);
2778 static RISCVException
rmw_sie(CPURISCVState
*env
, int csrno
,
2779 target_ulong
*ret_val
,
2780 target_ulong new_val
, target_ulong wr_mask
)
2785 ret
= rmw_sie64(env
, csrno
, &rval
, new_val
, wr_mask
);
2786 if (ret
== RISCV_EXCP_NONE
&& ret_val
) {
2793 static RISCVException
rmw_sieh(CPURISCVState
*env
, int csrno
,
2794 target_ulong
*ret_val
,
2795 target_ulong new_val
, target_ulong wr_mask
)
2800 ret
= rmw_sie64(env
, csrno
, &rval
,
2801 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2803 *ret_val
= rval
>> 32;
2809 static RISCVException
read_stvec(CPURISCVState
*env
, int csrno
,
2813 return RISCV_EXCP_NONE
;
2816 static RISCVException
write_stvec(CPURISCVState
*env
, int csrno
,
2819 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
2820 if ((val
& 3) < 2) {
2823 qemu_log_mask(LOG_UNIMP
, "CSR_STVEC: reserved mode not supported\n");
2825 return RISCV_EXCP_NONE
;
2828 static RISCVException
read_scounteren(CPURISCVState
*env
, int csrno
,
2831 *val
= env
->scounteren
;
2832 return RISCV_EXCP_NONE
;
2835 static RISCVException
write_scounteren(CPURISCVState
*env
, int csrno
,
2838 env
->scounteren
= val
;
2839 return RISCV_EXCP_NONE
;
2842 /* Supervisor Trap Handling */
2843 static RISCVException
read_sscratch_i128(CPURISCVState
*env
, int csrno
,
2846 *val
= int128_make128(env
->sscratch
, env
->sscratchh
);
2847 return RISCV_EXCP_NONE
;
2850 static RISCVException
write_sscratch_i128(CPURISCVState
*env
, int csrno
,
2853 env
->sscratch
= int128_getlo(val
);
2854 env
->sscratchh
= int128_gethi(val
);
2855 return RISCV_EXCP_NONE
;
2858 static RISCVException
read_sscratch(CPURISCVState
*env
, int csrno
,
2861 *val
= env
->sscratch
;
2862 return RISCV_EXCP_NONE
;
2865 static RISCVException
write_sscratch(CPURISCVState
*env
, int csrno
,
2868 env
->sscratch
= val
;
2869 return RISCV_EXCP_NONE
;
2872 static RISCVException
read_sepc(CPURISCVState
*env
, int csrno
,
2876 return RISCV_EXCP_NONE
;
2879 static RISCVException
write_sepc(CPURISCVState
*env
, int csrno
,
2883 return RISCV_EXCP_NONE
;
2886 static RISCVException
read_scause(CPURISCVState
*env
, int csrno
,
2890 return RISCV_EXCP_NONE
;
2893 static RISCVException
write_scause(CPURISCVState
*env
, int csrno
,
2897 return RISCV_EXCP_NONE
;
2900 static RISCVException
read_stval(CPURISCVState
*env
, int csrno
,
2904 return RISCV_EXCP_NONE
;
2907 static RISCVException
write_stval(CPURISCVState
*env
, int csrno
,
2911 return RISCV_EXCP_NONE
;
2914 static RISCVException
rmw_hvip64(CPURISCVState
*env
, int csrno
,
2916 uint64_t new_val
, uint64_t wr_mask
);
2918 static RISCVException
rmw_vsip64(CPURISCVState
*env
, int csrno
,
2920 uint64_t new_val
, uint64_t wr_mask
)
2923 uint64_t rval
, mask
= env
->hideleg
& VS_MODE_INTERRUPTS
;
2926 /* Add virtualized bits into vsip mask. */
2927 mask
|= env
->hvien
& ~env
->hideleg
;
2929 /* Bring VS-level bits to correct position */
2930 vsbits
= new_val
& (VS_MODE_INTERRUPTS
>> 1);
2931 new_val
&= ~(VS_MODE_INTERRUPTS
>> 1);
2932 new_val
|= vsbits
<< 1;
2933 vsbits
= wr_mask
& (VS_MODE_INTERRUPTS
>> 1);
2934 wr_mask
&= ~(VS_MODE_INTERRUPTS
>> 1);
2935 wr_mask
|= vsbits
<< 1;
2937 ret
= rmw_hvip64(env
, csrno
, &rval
, new_val
,
2938 wr_mask
& mask
& vsip_writable_mask
);
2941 vsbits
= rval
& VS_MODE_INTERRUPTS
;
2942 rval
&= ~VS_MODE_INTERRUPTS
;
2943 *ret_val
= rval
| (vsbits
>> 1);
2949 static RISCVException
rmw_vsip(CPURISCVState
*env
, int csrno
,
2950 target_ulong
*ret_val
,
2951 target_ulong new_val
, target_ulong wr_mask
)
2956 ret
= rmw_vsip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2964 static RISCVException
rmw_vsiph(CPURISCVState
*env
, int csrno
,
2965 target_ulong
*ret_val
,
2966 target_ulong new_val
, target_ulong wr_mask
)
2971 ret
= rmw_vsip64(env
, csrno
, &rval
,
2972 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2974 *ret_val
= rval
>> 32;
2980 static RISCVException
rmw_sip64(CPURISCVState
*env
, int csrno
,
2982 uint64_t new_val
, uint64_t wr_mask
)
2985 uint64_t mask
= (env
->mideleg
| env
->mvien
) & sip_writable_mask
;
2987 if (env
->virt_enabled
) {
2988 if (env
->hvictl
& HVICTL_VTI
) {
2989 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
2991 ret
= rmw_vsip64(env
, CSR_VSIP
, ret_val
, new_val
, wr_mask
);
2993 ret
= rmw_mvip64(env
, csrno
, ret_val
, new_val
, wr_mask
& mask
);
2997 *ret_val
&= (env
->mideleg
| env
->mvien
) &
2998 (S_MODE_INTERRUPTS
| LOCAL_INTERRUPTS
);
3004 static RISCVException
rmw_sip(CPURISCVState
*env
, int csrno
,
3005 target_ulong
*ret_val
,
3006 target_ulong new_val
, target_ulong wr_mask
)
3011 ret
= rmw_sip64(env
, csrno
, &rval
, new_val
, wr_mask
);
3019 static RISCVException
rmw_siph(CPURISCVState
*env
, int csrno
,
3020 target_ulong
*ret_val
,
3021 target_ulong new_val
, target_ulong wr_mask
)
3026 ret
= rmw_sip64(env
, csrno
, &rval
,
3027 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
3029 *ret_val
= rval
>> 32;
3035 /* Supervisor Protection and Translation */
3036 static RISCVException
read_satp(CPURISCVState
*env
, int csrno
,
3039 if (!riscv_cpu_cfg(env
)->mmu
) {
3041 return RISCV_EXCP_NONE
;
3044 return RISCV_EXCP_NONE
;
3047 static RISCVException
write_satp(CPURISCVState
*env
, int csrno
,
3050 if (!riscv_cpu_cfg(env
)->mmu
) {
3051 return RISCV_EXCP_NONE
;
3054 env
->satp
= legalize_xatp(env
, env
->satp
, val
);
3055 return RISCV_EXCP_NONE
;
3058 static RISCVException
read_vstopi(CPURISCVState
*env
, int csrno
,
3063 uint64_t vseip
, vsgein
;
3064 uint32_t iid
, iprio
, hviid
, hviprio
, gein
;
3065 uint32_t s
, scount
= 0, siid
[VSTOPI_NUM_SRCS
], siprio
[VSTOPI_NUM_SRCS
];
3067 gein
= get_field(env
->hstatus
, HSTATUS_VGEIN
);
3068 hviid
= get_field(env
->hvictl
, HVICTL_IID
);
3069 hviprio
= get_field(env
->hvictl
, HVICTL_IPRIO
);
3072 vsgein
= (env
->hgeip
& (1ULL << gein
)) ? MIP_VSEIP
: 0;
3073 vseip
= env
->mie
& (env
->mip
| vsgein
) & MIP_VSEIP
;
3074 if (gein
<= env
->geilen
&& vseip
) {
3075 siid
[scount
] = IRQ_S_EXT
;
3076 siprio
[scount
] = IPRIO_MMAXIPRIO
+ 1;
3077 if (env
->aia_ireg_rmw_fn
[PRV_S
]) {
3079 * Call machine specific IMSIC register emulation for
3082 ret
= env
->aia_ireg_rmw_fn
[PRV_S
](
3083 env
->aia_ireg_rmw_fn_arg
[PRV_S
],
3084 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI
, PRV_S
, true, gein
,
3085 riscv_cpu_mxl_bits(env
)),
3087 if (!ret
&& topei
) {
3088 siprio
[scount
] = topei
& IMSIC_TOPEI_IPRIO_MASK
;
3094 if (hviid
== IRQ_S_EXT
&& hviprio
) {
3095 siid
[scount
] = IRQ_S_EXT
;
3096 siprio
[scount
] = hviprio
;
3101 if (env
->hvictl
& HVICTL_VTI
) {
3102 if (hviid
!= IRQ_S_EXT
) {
3103 siid
[scount
] = hviid
;
3104 siprio
[scount
] = hviprio
;
3108 irq
= riscv_cpu_vsirq_pending(env
);
3109 if (irq
!= IRQ_S_EXT
&& 0 < irq
&& irq
<= 63) {
3111 siprio
[scount
] = env
->hviprio
[irq
];
3118 for (s
= 0; s
< scount
; s
++) {
3119 if (siprio
[s
] < iprio
) {
3126 if (env
->hvictl
& HVICTL_IPRIOM
) {
3127 if (iprio
> IPRIO_MMAXIPRIO
) {
3128 iprio
= IPRIO_MMAXIPRIO
;
3131 if (riscv_cpu_default_priority(iid
) > IPRIO_DEFAULT_S
) {
3132 iprio
= IPRIO_MMAXIPRIO
;
3142 *val
= (iid
& TOPI_IID_MASK
) << TOPI_IID_SHIFT
;
3145 return RISCV_EXCP_NONE
;
3148 static RISCVException
read_stopi(CPURISCVState
*env
, int csrno
,
3154 if (env
->virt_enabled
) {
3155 return read_vstopi(env
, CSR_VSTOPI
, val
);
3158 irq
= riscv_cpu_sirq_pending(env
);
3159 if (irq
<= 0 || irq
> 63) {
3162 iprio
= env
->siprio
[irq
];
3164 if (riscv_cpu_default_priority(irq
) > IPRIO_DEFAULT_S
) {
3165 iprio
= IPRIO_MMAXIPRIO
;
3168 *val
= (irq
& TOPI_IID_MASK
) << TOPI_IID_SHIFT
;
3172 return RISCV_EXCP_NONE
;
3175 /* Hypervisor Extensions */
3176 static RISCVException
read_hstatus(CPURISCVState
*env
, int csrno
,
3179 *val
= env
->hstatus
;
3180 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
3181 /* We only support 64-bit VSXL */
3182 *val
= set_field(*val
, HSTATUS_VSXL
, 2);
3184 /* We only support little endian */
3185 *val
= set_field(*val
, HSTATUS_VSBE
, 0);
3186 return RISCV_EXCP_NONE
;
3189 static RISCVException
write_hstatus(CPURISCVState
*env
, int csrno
,
3193 if (riscv_cpu_mxl(env
) != MXL_RV32
&& get_field(val
, HSTATUS_VSXL
) != 2) {
3194 qemu_log_mask(LOG_UNIMP
,
3195 "QEMU does not support mixed HSXLEN options.");
3197 if (get_field(val
, HSTATUS_VSBE
) != 0) {
3198 qemu_log_mask(LOG_UNIMP
, "QEMU does not support big endian guests.");
3200 return RISCV_EXCP_NONE
;
3203 static RISCVException
read_hedeleg(CPURISCVState
*env
, int csrno
,
3206 *val
= env
->hedeleg
;
3207 return RISCV_EXCP_NONE
;
3210 static RISCVException
write_hedeleg(CPURISCVState
*env
, int csrno
,
3213 env
->hedeleg
= val
& vs_delegable_excps
;
3214 return RISCV_EXCP_NONE
;
3217 static RISCVException
rmw_hvien64(CPURISCVState
*env
, int csrno
,
3219 uint64_t new_val
, uint64_t wr_mask
)
3221 uint64_t mask
= wr_mask
& hvien_writable_mask
;
3224 *ret_val
= env
->hvien
;
3227 env
->hvien
= (env
->hvien
& ~mask
) | (new_val
& mask
);
3229 return RISCV_EXCP_NONE
;
3232 static RISCVException
rmw_hvien(CPURISCVState
*env
, int csrno
,
3233 target_ulong
*ret_val
,
3234 target_ulong new_val
, target_ulong wr_mask
)
3239 ret
= rmw_hvien64(env
, csrno
, &rval
, new_val
, wr_mask
);
3247 static RISCVException
rmw_hvienh(CPURISCVState
*env
, int csrno
,
3248 target_ulong
*ret_val
,
3249 target_ulong new_val
, target_ulong wr_mask
)
3254 ret
= rmw_hvien64(env
, csrno
, &rval
,
3255 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
3257 *ret_val
= rval
>> 32;
3263 static RISCVException
rmw_hideleg64(CPURISCVState
*env
, int csrno
,
3265 uint64_t new_val
, uint64_t wr_mask
)
3267 uint64_t mask
= wr_mask
& vs_delegable_ints
;
3270 *ret_val
= env
->hideleg
& vs_delegable_ints
;
3273 env
->hideleg
= (env
->hideleg
& ~mask
) | (new_val
& mask
);
3274 return RISCV_EXCP_NONE
;
3277 static RISCVException
rmw_hideleg(CPURISCVState
*env
, int csrno
,
3278 target_ulong
*ret_val
,
3279 target_ulong new_val
, target_ulong wr_mask
)
3284 ret
= rmw_hideleg64(env
, csrno
, &rval
, new_val
, wr_mask
);
3292 static RISCVException
rmw_hidelegh(CPURISCVState
*env
, int csrno
,
3293 target_ulong
*ret_val
,
3294 target_ulong new_val
, target_ulong wr_mask
)
3299 ret
= rmw_hideleg64(env
, csrno
, &rval
,
3300 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
3302 *ret_val
= rval
>> 32;
3309 * The function is written for two use-cases:
3310 * 1- To access hvip csr as is for HS-mode access.
3311 * 2- To access vsip as a combination of hvip, and mip for vs-mode.
3313 * Both report bits 2, 6, 10 and 13:63.
3314 * vsip needs to be read-only zero when both hideleg[i] and
3315 * hvien[i] are zero.
3317 static RISCVException
rmw_hvip64(CPURISCVState
*env
, int csrno
,
3319 uint64_t new_val
, uint64_t wr_mask
)
3326 * For bits 10, 6 and 2, vsip[i] is an alias of hip[i]. These bits are
3327 * present in hip, hvip and mip. Where mip[i] is alias of hip[i] and hvip[i]
3328 * is OR'ed in hip[i] to inject virtual interrupts from hypervisor. These
3329 * bits are actually being maintained in mip so we read them from there.
3330 * This way we have a single source of truth and allows for easier
3333 * For bits 13:63 we have:
3335 * hideleg[i] hvien[i]
3336 * 0 0 No delegation. vsip[i] readonly zero.
3337 * 0 1 vsip[i] is alias of hvip[i], sip bypassed.
3338 * 1 X vsip[i] is alias of sip[i], hvip bypassed.
3340 * alias_mask denotes the bits that come from sip (mip here given we
3341 * maintain all bits there). nalias_mask denotes bits that come from
3344 uint64_t alias_mask
= (env
->hideleg
| ~env
->hvien
) | VS_MODE_INTERRUPTS
;
3345 uint64_t nalias_mask
= (~env
->hideleg
& env
->hvien
);
3346 uint64_t wr_mask_hvip
;
3347 uint64_t wr_mask_mip
;
3350 * Both alias and non-alias mask remain same for vsip except:
3351 * 1- For VS* bits if they are zero in hideleg.
3352 * 2- For 13:63 bits if they are zero in both hideleg and hvien.
3354 if (csrno
== CSR_VSIP
) {
3355 /* zero-out VS* bits that are not delegated to VS mode. */
3356 alias_mask
&= (env
->hideleg
| ~VS_MODE_INTERRUPTS
);
3359 * zero-out 13:63 bits that are zero in both hideleg and hvien.
3360 * nalias_mask mask can not contain any VS* bits so only second
3361 * condition applies on it.
3363 nalias_mask
&= (env
->hideleg
| env
->hvien
);
3364 alias_mask
&= (env
->hideleg
| env
->hvien
);
3367 wr_mask_hvip
= wr_mask
& nalias_mask
& hvip_writable_mask
;
3368 wr_mask_mip
= wr_mask
& alias_mask
& hvip_writable_mask
;
3370 /* Aliased bits, bits 10, 6, 2 need to come from mip. */
3371 ret
= rmw_mip64(env
, csrno
, &ret_mip
, new_val
, wr_mask_mip
);
3372 if (ret
!= RISCV_EXCP_NONE
) {
3376 old_hvip
= env
->hvip
;
3379 env
->hvip
= (env
->hvip
& ~wr_mask_hvip
) | (new_val
& wr_mask_hvip
);
3382 * Given hvip is separate source from mip, we need to trigger interrupt
3383 * from here separately. Normally this happen from riscv_cpu_update_mip.
3385 riscv_cpu_interrupt(env
);
3389 /* Only take VS* bits from mip. */
3390 ret_mip
&= alias_mask
;
3392 /* Take in non-delegated 13:63 bits from hvip. */
3393 old_hvip
&= nalias_mask
;
3395 *ret_val
= ret_mip
| old_hvip
;
3401 static RISCVException
rmw_hvip(CPURISCVState
*env
, int csrno
,
3402 target_ulong
*ret_val
,
3403 target_ulong new_val
, target_ulong wr_mask
)
3408 ret
= rmw_hvip64(env
, csrno
, &rval
, new_val
, wr_mask
);
3416 static RISCVException
rmw_hviph(CPURISCVState
*env
, int csrno
,
3417 target_ulong
*ret_val
,
3418 target_ulong new_val
, target_ulong wr_mask
)
3423 ret
= rmw_hvip64(env
, csrno
, &rval
,
3424 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
3426 *ret_val
= rval
>> 32;
3432 static RISCVException
rmw_hip(CPURISCVState
*env
, int csrno
,
3433 target_ulong
*ret_value
,
3434 target_ulong new_value
, target_ulong write_mask
)
3436 int ret
= rmw_mip(env
, csrno
, ret_value
, new_value
,
3437 write_mask
& hip_writable_mask
);
3440 *ret_value
&= HS_MODE_INTERRUPTS
;
3445 static RISCVException
rmw_hie(CPURISCVState
*env
, int csrno
,
3446 target_ulong
*ret_val
,
3447 target_ulong new_val
, target_ulong wr_mask
)
3452 ret
= rmw_mie64(env
, csrno
, &rval
, new_val
, wr_mask
& HS_MODE_INTERRUPTS
);
3454 *ret_val
= rval
& HS_MODE_INTERRUPTS
;
3460 static RISCVException
read_hcounteren(CPURISCVState
*env
, int csrno
,
3463 *val
= env
->hcounteren
;
3464 return RISCV_EXCP_NONE
;
3467 static RISCVException
write_hcounteren(CPURISCVState
*env
, int csrno
,
3470 env
->hcounteren
= val
;
3471 return RISCV_EXCP_NONE
;
3474 static RISCVException
read_hgeie(CPURISCVState
*env
, int csrno
,
3480 return RISCV_EXCP_NONE
;
3483 static RISCVException
write_hgeie(CPURISCVState
*env
, int csrno
,
3486 /* Only GEILEN:1 bits implemented and BIT0 is never implemented */
3487 val
&= ((((target_ulong
)1) << env
->geilen
) - 1) << 1;
3489 /* Update mip.SGEIP bit */
3490 riscv_cpu_update_mip(env
, MIP_SGEIP
,
3491 BOOL_TO_MASK(!!(env
->hgeie
& env
->hgeip
)));
3492 return RISCV_EXCP_NONE
;
3495 static RISCVException
read_htval(CPURISCVState
*env
, int csrno
,
3499 return RISCV_EXCP_NONE
;
3502 static RISCVException
write_htval(CPURISCVState
*env
, int csrno
,
3506 return RISCV_EXCP_NONE
;
3509 static RISCVException
read_htinst(CPURISCVState
*env
, int csrno
,
3513 return RISCV_EXCP_NONE
;
3516 static RISCVException
write_htinst(CPURISCVState
*env
, int csrno
,
3519 return RISCV_EXCP_NONE
;
3522 static RISCVException
read_hgeip(CPURISCVState
*env
, int csrno
,
3528 return RISCV_EXCP_NONE
;
3531 static RISCVException
read_hgatp(CPURISCVState
*env
, int csrno
,
3535 return RISCV_EXCP_NONE
;
3538 static RISCVException
write_hgatp(CPURISCVState
*env
, int csrno
,
3541 env
->hgatp
= legalize_xatp(env
, env
->hgatp
, val
);
3542 return RISCV_EXCP_NONE
;
3545 static RISCVException
read_htimedelta(CPURISCVState
*env
, int csrno
,
3548 if (!env
->rdtime_fn
) {
3549 return RISCV_EXCP_ILLEGAL_INST
;
3552 *val
= env
->htimedelta
;
3553 return RISCV_EXCP_NONE
;
3556 static RISCVException
write_htimedelta(CPURISCVState
*env
, int csrno
,
3559 if (!env
->rdtime_fn
) {
3560 return RISCV_EXCP_ILLEGAL_INST
;
3563 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
3564 env
->htimedelta
= deposit64(env
->htimedelta
, 0, 32, (uint64_t)val
);
3566 env
->htimedelta
= val
;
3569 if (riscv_cpu_cfg(env
)->ext_sstc
&& env
->rdtime_fn
) {
3570 riscv_timer_write_timecmp(env
, env
->vstimer
, env
->vstimecmp
,
3571 env
->htimedelta
, MIP_VSTIP
);
3574 return RISCV_EXCP_NONE
;
3577 static RISCVException
read_htimedeltah(CPURISCVState
*env
, int csrno
,
3580 if (!env
->rdtime_fn
) {
3581 return RISCV_EXCP_ILLEGAL_INST
;
3584 *val
= env
->htimedelta
>> 32;
3585 return RISCV_EXCP_NONE
;
3588 static RISCVException
write_htimedeltah(CPURISCVState
*env
, int csrno
,
3591 if (!env
->rdtime_fn
) {
3592 return RISCV_EXCP_ILLEGAL_INST
;
3595 env
->htimedelta
= deposit64(env
->htimedelta
, 32, 32, (uint64_t)val
);
3597 if (riscv_cpu_cfg(env
)->ext_sstc
&& env
->rdtime_fn
) {
3598 riscv_timer_write_timecmp(env
, env
->vstimer
, env
->vstimecmp
,
3599 env
->htimedelta
, MIP_VSTIP
);
3602 return RISCV_EXCP_NONE
;
3605 static RISCVException
read_hvictl(CPURISCVState
*env
, int csrno
,
3609 return RISCV_EXCP_NONE
;
3612 static RISCVException
write_hvictl(CPURISCVState
*env
, int csrno
,
3615 env
->hvictl
= val
& HVICTL_VALID_MASK
;
3616 return RISCV_EXCP_NONE
;
3619 static RISCVException
read_hvipriox(CPURISCVState
*env
, int first_index
,
3620 uint8_t *iprio
, target_ulong
*val
)
3622 int i
, irq
, rdzero
, num_irqs
= 4 * (riscv_cpu_mxl_bits(env
) / 32);
3624 /* First index has to be a multiple of number of irqs per register */
3625 if (first_index
% num_irqs
) {
3626 return (env
->virt_enabled
) ?
3627 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
3630 /* Fill-up return value */
3632 for (i
= 0; i
< num_irqs
; i
++) {
3633 if (riscv_cpu_hviprio_index2irq(first_index
+ i
, &irq
, &rdzero
)) {
3639 *val
|= ((target_ulong
)iprio
[irq
]) << (i
* 8);
3642 return RISCV_EXCP_NONE
;
3645 static RISCVException
write_hvipriox(CPURISCVState
*env
, int first_index
,
3646 uint8_t *iprio
, target_ulong val
)
3648 int i
, irq
, rdzero
, num_irqs
= 4 * (riscv_cpu_mxl_bits(env
) / 32);
3650 /* First index has to be a multiple of number of irqs per register */
3651 if (first_index
% num_irqs
) {
3652 return (env
->virt_enabled
) ?
3653 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
3656 /* Fill-up priority array */
3657 for (i
= 0; i
< num_irqs
; i
++) {
3658 if (riscv_cpu_hviprio_index2irq(first_index
+ i
, &irq
, &rdzero
)) {
3664 iprio
[irq
] = (val
>> (i
* 8)) & 0xff;
3668 return RISCV_EXCP_NONE
;
3671 static RISCVException
read_hviprio1(CPURISCVState
*env
, int csrno
,
3674 return read_hvipriox(env
, 0, env
->hviprio
, val
);
3677 static RISCVException
write_hviprio1(CPURISCVState
*env
, int csrno
,
3680 return write_hvipriox(env
, 0, env
->hviprio
, val
);
3683 static RISCVException
read_hviprio1h(CPURISCVState
*env
, int csrno
,
3686 return read_hvipriox(env
, 4, env
->hviprio
, val
);
3689 static RISCVException
write_hviprio1h(CPURISCVState
*env
, int csrno
,
3692 return write_hvipriox(env
, 4, env
->hviprio
, val
);
3695 static RISCVException
read_hviprio2(CPURISCVState
*env
, int csrno
,
3698 return read_hvipriox(env
, 8, env
->hviprio
, val
);
3701 static RISCVException
write_hviprio2(CPURISCVState
*env
, int csrno
,
3704 return write_hvipriox(env
, 8, env
->hviprio
, val
);
3707 static RISCVException
read_hviprio2h(CPURISCVState
*env
, int csrno
,
3710 return read_hvipriox(env
, 12, env
->hviprio
, val
);
3713 static RISCVException
write_hviprio2h(CPURISCVState
*env
, int csrno
,
3716 return write_hvipriox(env
, 12, env
->hviprio
, val
);
3719 /* Virtual CSR Registers */
3720 static RISCVException
read_vsstatus(CPURISCVState
*env
, int csrno
,
3723 *val
= env
->vsstatus
;
3724 return RISCV_EXCP_NONE
;
3727 static RISCVException
write_vsstatus(CPURISCVState
*env
, int csrno
,
3730 uint64_t mask
= (target_ulong
)-1;
3731 if ((val
& VSSTATUS64_UXL
) == 0) {
3732 mask
&= ~VSSTATUS64_UXL
;
3734 env
->vsstatus
= (env
->vsstatus
& ~mask
) | (uint64_t)val
;
3735 return RISCV_EXCP_NONE
;
3738 static RISCVException
read_vstvec(CPURISCVState
*env
, int csrno
,
3742 return RISCV_EXCP_NONE
;
3745 static RISCVException
write_vstvec(CPURISCVState
*env
, int csrno
,
3749 return RISCV_EXCP_NONE
;
3752 static RISCVException
read_vsscratch(CPURISCVState
*env
, int csrno
,
3755 *val
= env
->vsscratch
;
3756 return RISCV_EXCP_NONE
;
3759 static RISCVException
write_vsscratch(CPURISCVState
*env
, int csrno
,
3762 env
->vsscratch
= val
;
3763 return RISCV_EXCP_NONE
;
3766 static RISCVException
read_vsepc(CPURISCVState
*env
, int csrno
,
3770 return RISCV_EXCP_NONE
;
3773 static RISCVException
write_vsepc(CPURISCVState
*env
, int csrno
,
3777 return RISCV_EXCP_NONE
;
3780 static RISCVException
read_vscause(CPURISCVState
*env
, int csrno
,
3783 *val
= env
->vscause
;
3784 return RISCV_EXCP_NONE
;
3787 static RISCVException
write_vscause(CPURISCVState
*env
, int csrno
,
3791 return RISCV_EXCP_NONE
;
3794 static RISCVException
read_vstval(CPURISCVState
*env
, int csrno
,
3798 return RISCV_EXCP_NONE
;
3801 static RISCVException
write_vstval(CPURISCVState
*env
, int csrno
,
3805 return RISCV_EXCP_NONE
;
3808 static RISCVException
read_vsatp(CPURISCVState
*env
, int csrno
,
3812 return RISCV_EXCP_NONE
;
3815 static RISCVException
write_vsatp(CPURISCVState
*env
, int csrno
,
3818 env
->vsatp
= legalize_xatp(env
, env
->vsatp
, val
);
3819 return RISCV_EXCP_NONE
;
3822 static RISCVException
read_mtval2(CPURISCVState
*env
, int csrno
,
3826 return RISCV_EXCP_NONE
;
3829 static RISCVException
write_mtval2(CPURISCVState
*env
, int csrno
,
3833 return RISCV_EXCP_NONE
;
3836 static RISCVException
read_mtinst(CPURISCVState
*env
, int csrno
,
3840 return RISCV_EXCP_NONE
;
3843 static RISCVException
write_mtinst(CPURISCVState
*env
, int csrno
,
3847 return RISCV_EXCP_NONE
;
3850 /* Physical Memory Protection */
3851 static RISCVException
read_mseccfg(CPURISCVState
*env
, int csrno
,
3854 *val
= mseccfg_csr_read(env
);
3855 return RISCV_EXCP_NONE
;
3858 static RISCVException
write_mseccfg(CPURISCVState
*env
, int csrno
,
3861 mseccfg_csr_write(env
, val
);
3862 return RISCV_EXCP_NONE
;
3865 static RISCVException
read_pmpcfg(CPURISCVState
*env
, int csrno
,
3868 uint32_t reg_index
= csrno
- CSR_PMPCFG0
;
3870 *val
= pmpcfg_csr_read(env
, reg_index
);
3871 return RISCV_EXCP_NONE
;
3874 static RISCVException
write_pmpcfg(CPURISCVState
*env
, int csrno
,
3877 uint32_t reg_index
= csrno
- CSR_PMPCFG0
;
3879 pmpcfg_csr_write(env
, reg_index
, val
);
3880 return RISCV_EXCP_NONE
;
3883 static RISCVException
read_pmpaddr(CPURISCVState
*env
, int csrno
,
3886 *val
= pmpaddr_csr_read(env
, csrno
- CSR_PMPADDR0
);
3887 return RISCV_EXCP_NONE
;
3890 static RISCVException
write_pmpaddr(CPURISCVState
*env
, int csrno
,
3893 pmpaddr_csr_write(env
, csrno
- CSR_PMPADDR0
, val
);
3894 return RISCV_EXCP_NONE
;
3897 static RISCVException
read_tselect(CPURISCVState
*env
, int csrno
,
3900 *val
= tselect_csr_read(env
);
3901 return RISCV_EXCP_NONE
;
3904 static RISCVException
write_tselect(CPURISCVState
*env
, int csrno
,
3907 tselect_csr_write(env
, val
);
3908 return RISCV_EXCP_NONE
;
3911 static RISCVException
read_tdata(CPURISCVState
*env
, int csrno
,
3914 /* return 0 in tdata1 to end the trigger enumeration */
3915 if (env
->trigger_cur
>= RV_MAX_TRIGGERS
&& csrno
== CSR_TDATA1
) {
3917 return RISCV_EXCP_NONE
;
3920 if (!tdata_available(env
, csrno
- CSR_TDATA1
)) {
3921 return RISCV_EXCP_ILLEGAL_INST
;
3924 *val
= tdata_csr_read(env
, csrno
- CSR_TDATA1
);
3925 return RISCV_EXCP_NONE
;
3928 static RISCVException
write_tdata(CPURISCVState
*env
, int csrno
,
3931 if (!tdata_available(env
, csrno
- CSR_TDATA1
)) {
3932 return RISCV_EXCP_ILLEGAL_INST
;
3935 tdata_csr_write(env
, csrno
- CSR_TDATA1
, val
);
3936 return RISCV_EXCP_NONE
;
3939 static RISCVException
read_tinfo(CPURISCVState
*env
, int csrno
,
3942 *val
= tinfo_csr_read(env
);
3943 return RISCV_EXCP_NONE
;
3946 static RISCVException
read_mcontext(CPURISCVState
*env
, int csrno
,
3949 *val
= env
->mcontext
;
3950 return RISCV_EXCP_NONE
;
3953 static RISCVException
write_mcontext(CPURISCVState
*env
, int csrno
,
3956 bool rv32
= riscv_cpu_mxl(env
) == MXL_RV32
? true : false;
3959 if (riscv_has_ext(env
, RVH
)) {
3960 /* Spec suggest 7-bit for RV32 and 14-bit for RV64 w/ H extension */
3961 mask
= rv32
? MCONTEXT32_HCONTEXT
: MCONTEXT64_HCONTEXT
;
3963 /* Spec suggest 6-bit for RV32 and 13-bit for RV64 w/o H extension */
3964 mask
= rv32
? MCONTEXT32
: MCONTEXT64
;
3967 env
->mcontext
= val
& mask
;
3968 return RISCV_EXCP_NONE
;
3972 * Functions to access Pointer Masking feature registers
3973 * We have to check if current priv lvl could modify
3976 static bool check_pm_current_disabled(CPURISCVState
*env
, int csrno
)
3978 int csr_priv
= get_field(csrno
, 0x300);
3981 if (env
->debugger
) {
3985 * If priv lvls differ that means we're accessing csr from higher priv lvl,
3986 * so allow the access
3988 if (env
->priv
!= csr_priv
) {
3991 switch (env
->priv
) {
3993 pm_current
= get_field(env
->mmte
, M_PM_CURRENT
);
3996 pm_current
= get_field(env
->mmte
, S_PM_CURRENT
);
3999 pm_current
= get_field(env
->mmte
, U_PM_CURRENT
);
4002 g_assert_not_reached();
4004 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
4008 static RISCVException
read_mmte(CPURISCVState
*env
, int csrno
,
4011 *val
= env
->mmte
& MMTE_MASK
;
4012 return RISCV_EXCP_NONE
;
4015 static RISCVException
write_mmte(CPURISCVState
*env
, int csrno
,
4019 target_ulong wpri_val
= val
& MMTE_MASK
;
4021 if (val
!= wpri_val
) {
4022 qemu_log_mask(LOG_GUEST_ERROR
, "%s" TARGET_FMT_lx
" %s"
4023 TARGET_FMT_lx
"\n", "MMTE: WPRI violation written 0x",
4024 val
, "vs expected 0x", wpri_val
);
4026 /* for machine mode pm.current is hardwired to 1 */
4027 wpri_val
|= MMTE_M_PM_CURRENT
;
4029 /* hardwiring pm.instruction bit to 0, since it's not supported yet */
4030 wpri_val
&= ~(MMTE_M_PM_INSN
| MMTE_S_PM_INSN
| MMTE_U_PM_INSN
);
4031 env
->mmte
= wpri_val
| EXT_STATUS_DIRTY
;
4032 riscv_cpu_update_mask(env
);
4034 /* Set XS and SD bits, since PM CSRs are dirty */
4035 mstatus
= env
->mstatus
| MSTATUS_XS
;
4036 write_mstatus(env
, csrno
, mstatus
);
4037 return RISCV_EXCP_NONE
;
4040 static RISCVException
read_smte(CPURISCVState
*env
, int csrno
,
4043 *val
= env
->mmte
& SMTE_MASK
;
4044 return RISCV_EXCP_NONE
;
4047 static RISCVException
write_smte(CPURISCVState
*env
, int csrno
,
4050 target_ulong wpri_val
= val
& SMTE_MASK
;
4052 if (val
!= wpri_val
) {
4053 qemu_log_mask(LOG_GUEST_ERROR
, "%s" TARGET_FMT_lx
" %s"
4054 TARGET_FMT_lx
"\n", "SMTE: WPRI violation written 0x",
4055 val
, "vs expected 0x", wpri_val
);
4058 /* if pm.current==0 we can't modify current PM CSRs */
4059 if (check_pm_current_disabled(env
, csrno
)) {
4060 return RISCV_EXCP_NONE
;
4063 wpri_val
|= (env
->mmte
& ~SMTE_MASK
);
4064 write_mmte(env
, csrno
, wpri_val
);
4065 return RISCV_EXCP_NONE
;
4068 static RISCVException
read_umte(CPURISCVState
*env
, int csrno
,
4071 *val
= env
->mmte
& UMTE_MASK
;
4072 return RISCV_EXCP_NONE
;
4075 static RISCVException
write_umte(CPURISCVState
*env
, int csrno
,
4078 target_ulong wpri_val
= val
& UMTE_MASK
;
4080 if (val
!= wpri_val
) {
4081 qemu_log_mask(LOG_GUEST_ERROR
, "%s" TARGET_FMT_lx
" %s"
4082 TARGET_FMT_lx
"\n", "UMTE: WPRI violation written 0x",
4083 val
, "vs expected 0x", wpri_val
);
4086 if (check_pm_current_disabled(env
, csrno
)) {
4087 return RISCV_EXCP_NONE
;
4090 wpri_val
|= (env
->mmte
& ~UMTE_MASK
);
4091 write_mmte(env
, csrno
, wpri_val
);
4092 return RISCV_EXCP_NONE
;
4095 static RISCVException
read_mpmmask(CPURISCVState
*env
, int csrno
,
4098 *val
= env
->mpmmask
;
4099 return RISCV_EXCP_NONE
;
4102 static RISCVException
write_mpmmask(CPURISCVState
*env
, int csrno
,
4108 if ((cpu_address_mode(env
) == PRV_M
) && (env
->mmte
& M_PM_ENABLE
)) {
4109 env
->cur_pmmask
= val
;
4111 env
->mmte
|= EXT_STATUS_DIRTY
;
4113 /* Set XS and SD bits, since PM CSRs are dirty */
4114 mstatus
= env
->mstatus
| MSTATUS_XS
;
4115 write_mstatus(env
, csrno
, mstatus
);
4116 return RISCV_EXCP_NONE
;
4119 static RISCVException
read_spmmask(CPURISCVState
*env
, int csrno
,
4122 *val
= env
->spmmask
;
4123 return RISCV_EXCP_NONE
;
4126 static RISCVException
write_spmmask(CPURISCVState
*env
, int csrno
,
4131 /* if pm.current==0 we can't modify current PM CSRs */
4132 if (check_pm_current_disabled(env
, csrno
)) {
4133 return RISCV_EXCP_NONE
;
4136 if ((cpu_address_mode(env
) == PRV_S
) && (env
->mmte
& S_PM_ENABLE
)) {
4137 env
->cur_pmmask
= val
;
4138 if (cpu_get_xl(env
, PRV_S
) == MXL_RV32
) {
4139 env
->cur_pmmask
&= UINT32_MAX
;
4142 env
->mmte
|= EXT_STATUS_DIRTY
;
4144 /* Set XS and SD bits, since PM CSRs are dirty */
4145 mstatus
= env
->mstatus
| MSTATUS_XS
;
4146 write_mstatus(env
, csrno
, mstatus
);
4147 return RISCV_EXCP_NONE
;
4150 static RISCVException
read_upmmask(CPURISCVState
*env
, int csrno
,
4153 *val
= env
->upmmask
;
4154 return RISCV_EXCP_NONE
;
4157 static RISCVException
write_upmmask(CPURISCVState
*env
, int csrno
,
4162 /* if pm.current==0 we can't modify current PM CSRs */
4163 if (check_pm_current_disabled(env
, csrno
)) {
4164 return RISCV_EXCP_NONE
;
4167 if ((cpu_address_mode(env
) == PRV_U
) && (env
->mmte
& U_PM_ENABLE
)) {
4168 env
->cur_pmmask
= val
;
4169 if (cpu_get_xl(env
, PRV_U
) == MXL_RV32
) {
4170 env
->cur_pmmask
&= UINT32_MAX
;
4173 env
->mmte
|= EXT_STATUS_DIRTY
;
4175 /* Set XS and SD bits, since PM CSRs are dirty */
4176 mstatus
= env
->mstatus
| MSTATUS_XS
;
4177 write_mstatus(env
, csrno
, mstatus
);
4178 return RISCV_EXCP_NONE
;
4181 static RISCVException
read_mpmbase(CPURISCVState
*env
, int csrno
,
4184 *val
= env
->mpmbase
;
4185 return RISCV_EXCP_NONE
;
4188 static RISCVException
write_mpmbase(CPURISCVState
*env
, int csrno
,
4194 if ((cpu_address_mode(env
) == PRV_M
) && (env
->mmte
& M_PM_ENABLE
)) {
4195 env
->cur_pmbase
= val
;
4197 env
->mmte
|= EXT_STATUS_DIRTY
;
4199 /* Set XS and SD bits, since PM CSRs are dirty */
4200 mstatus
= env
->mstatus
| MSTATUS_XS
;
4201 write_mstatus(env
, csrno
, mstatus
);
4202 return RISCV_EXCP_NONE
;
4205 static RISCVException
read_spmbase(CPURISCVState
*env
, int csrno
,
4208 *val
= env
->spmbase
;
4209 return RISCV_EXCP_NONE
;
4212 static RISCVException
write_spmbase(CPURISCVState
*env
, int csrno
,
4217 /* if pm.current==0 we can't modify current PM CSRs */
4218 if (check_pm_current_disabled(env
, csrno
)) {
4219 return RISCV_EXCP_NONE
;
4222 if ((cpu_address_mode(env
) == PRV_S
) && (env
->mmte
& S_PM_ENABLE
)) {
4223 env
->cur_pmbase
= val
;
4224 if (cpu_get_xl(env
, PRV_S
) == MXL_RV32
) {
4225 env
->cur_pmbase
&= UINT32_MAX
;
4228 env
->mmte
|= EXT_STATUS_DIRTY
;
4230 /* Set XS and SD bits, since PM CSRs are dirty */
4231 mstatus
= env
->mstatus
| MSTATUS_XS
;
4232 write_mstatus(env
, csrno
, mstatus
);
4233 return RISCV_EXCP_NONE
;
4236 static RISCVException
read_upmbase(CPURISCVState
*env
, int csrno
,
4239 *val
= env
->upmbase
;
4240 return RISCV_EXCP_NONE
;
4243 static RISCVException
write_upmbase(CPURISCVState
*env
, int csrno
,
4248 /* if pm.current==0 we can't modify current PM CSRs */
4249 if (check_pm_current_disabled(env
, csrno
)) {
4250 return RISCV_EXCP_NONE
;
4253 if ((cpu_address_mode(env
) == PRV_U
) && (env
->mmte
& U_PM_ENABLE
)) {
4254 env
->cur_pmbase
= val
;
4255 if (cpu_get_xl(env
, PRV_U
) == MXL_RV32
) {
4256 env
->cur_pmbase
&= UINT32_MAX
;
4259 env
->mmte
|= EXT_STATUS_DIRTY
;
4261 /* Set XS and SD bits, since PM CSRs are dirty */
4262 mstatus
= env
->mstatus
| MSTATUS_XS
;
4263 write_mstatus(env
, csrno
, mstatus
);
4264 return RISCV_EXCP_NONE
;
4269 /* Crypto Extension */
4270 static RISCVException
rmw_seed(CPURISCVState
*env
, int csrno
,
4271 target_ulong
*ret_value
,
4272 target_ulong new_value
,
4273 target_ulong write_mask
)
4276 Error
*random_e
= NULL
;
4280 random_r
= qemu_guest_getrandom(&random_v
, 2, &random_e
);
4281 if (unlikely(random_r
< 0)) {
4283 * Failed, for unknown reasons in the crypto subsystem.
4284 * The best we can do is log the reason and return a
4285 * failure indication to the guest. There is no reason
4286 * we know to expect the failure to be transitory, so
4287 * indicate DEAD to avoid having the guest spin on WAIT.
4289 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
4290 __func__
, error_get_pretty(random_e
));
4291 error_free(random_e
);
4292 rval
= SEED_OPST_DEAD
;
4294 rval
= random_v
| SEED_OPST_ES16
;
4301 return RISCV_EXCP_NONE
;
4305 * riscv_csrrw - read and/or update control and status register
4307 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0);
4308 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1);
4309 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value);
4310 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value);
4313 static inline RISCVException
riscv_csrrw_check(CPURISCVState
*env
,
4317 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
4318 bool read_only
= get_field(csrno
, 0xC00) == 3;
4319 int csr_min_priv
= csr_ops
[csrno
].min_priv_ver
;
4321 /* ensure the CSR extension is enabled */
4322 if (!riscv_cpu_cfg(env
)->ext_zicsr
) {
4323 return RISCV_EXCP_ILLEGAL_INST
;
4326 /* ensure CSR is implemented by checking predicate */
4327 if (!csr_ops
[csrno
].predicate
) {
4328 return RISCV_EXCP_ILLEGAL_INST
;
4331 /* privileged spec version check */
4332 if (env
->priv_ver
< csr_min_priv
) {
4333 return RISCV_EXCP_ILLEGAL_INST
;
4336 /* read / write check */
4337 if (write_mask
&& read_only
) {
4338 return RISCV_EXCP_ILLEGAL_INST
;
4342 * The predicate() not only does existence check but also does some
4343 * access control check which triggers for example virtual instruction
4344 * exception in some cases. When writing read-only CSRs in those cases
4345 * illegal instruction exception should be triggered instead of virtual
4346 * instruction exception. Hence this comes after the read / write check.
4348 RISCVException ret
= csr_ops
[csrno
].predicate(env
, csrno
);
4349 if (ret
!= RISCV_EXCP_NONE
) {
4353 #if !defined(CONFIG_USER_ONLY)
4354 int csr_priv
, effective_priv
= env
->priv
;
4356 if (riscv_has_ext(env
, RVH
) && env
->priv
== PRV_S
&&
4357 !env
->virt_enabled
) {
4359 * We are in HS mode. Add 1 to the effective privilege level to
4360 * allow us to access the Hypervisor CSRs.
4365 csr_priv
= get_field(csrno
, 0x300);
4366 if (!env
->debugger
&& (effective_priv
< csr_priv
)) {
4367 if (csr_priv
== (PRV_S
+ 1) && env
->virt_enabled
) {
4368 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
4370 return RISCV_EXCP_ILLEGAL_INST
;
4373 return RISCV_EXCP_NONE
;
4376 static RISCVException
riscv_csrrw_do64(CPURISCVState
*env
, int csrno
,
4377 target_ulong
*ret_value
,
4378 target_ulong new_value
,
4379 target_ulong write_mask
)
4382 target_ulong old_value
= 0;
4384 /* execute combined read/write operation if it exists */
4385 if (csr_ops
[csrno
].op
) {
4386 return csr_ops
[csrno
].op(env
, csrno
, ret_value
, new_value
, write_mask
);
4390 * ret_value == NULL means that rd=x0 and we're coming from helper_csrw()
4391 * and we can't throw side effects caused by CSR reads.
4394 /* if no accessor exists then return failure */
4395 if (!csr_ops
[csrno
].read
) {
4396 return RISCV_EXCP_ILLEGAL_INST
;
4398 /* read old value */
4399 ret
= csr_ops
[csrno
].read(env
, csrno
, &old_value
);
4400 if (ret
!= RISCV_EXCP_NONE
) {
4405 /* write value if writable and write mask set, otherwise drop writes */
4407 new_value
= (old_value
& ~write_mask
) | (new_value
& write_mask
);
4408 if (csr_ops
[csrno
].write
) {
4409 ret
= csr_ops
[csrno
].write(env
, csrno
, new_value
);
4410 if (ret
!= RISCV_EXCP_NONE
) {
4416 /* return old value */
4418 *ret_value
= old_value
;
4421 return RISCV_EXCP_NONE
;
4424 RISCVException
riscv_csrrw(CPURISCVState
*env
, int csrno
,
4425 target_ulong
*ret_value
,
4426 target_ulong new_value
, target_ulong write_mask
)
4428 RISCVException ret
= riscv_csrrw_check(env
, csrno
, write_mask
);
4429 if (ret
!= RISCV_EXCP_NONE
) {
4433 return riscv_csrrw_do64(env
, csrno
, ret_value
, new_value
, write_mask
);
4436 static RISCVException
riscv_csrrw_do128(CPURISCVState
*env
, int csrno
,
4444 /* read old value */
4445 ret
= csr_ops
[csrno
].read128(env
, csrno
, &old_value
);
4446 if (ret
!= RISCV_EXCP_NONE
) {
4450 /* write value if writable and write mask set, otherwise drop writes */
4451 if (int128_nz(write_mask
)) {
4452 new_value
= int128_or(int128_and(old_value
, int128_not(write_mask
)),
4453 int128_and(new_value
, write_mask
));
4454 if (csr_ops
[csrno
].write128
) {
4455 ret
= csr_ops
[csrno
].write128(env
, csrno
, new_value
);
4456 if (ret
!= RISCV_EXCP_NONE
) {
4459 } else if (csr_ops
[csrno
].write
) {
4460 /* avoids having to write wrappers for all registers */
4461 ret
= csr_ops
[csrno
].write(env
, csrno
, int128_getlo(new_value
));
4462 if (ret
!= RISCV_EXCP_NONE
) {
4468 /* return old value */
4470 *ret_value
= old_value
;
4473 return RISCV_EXCP_NONE
;
4476 RISCVException
riscv_csrrw_i128(CPURISCVState
*env
, int csrno
,
4478 Int128 new_value
, Int128 write_mask
)
4482 ret
= riscv_csrrw_check(env
, csrno
, int128_nz(write_mask
));
4483 if (ret
!= RISCV_EXCP_NONE
) {
4487 if (csr_ops
[csrno
].read128
) {
4488 return riscv_csrrw_do128(env
, csrno
, ret_value
, new_value
, write_mask
);
4492 * Fall back to 64-bit version for now, if the 128-bit alternative isn't
4494 * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
4495 * significant), for those, this fallback is correctly handling the
4498 target_ulong old_value
;
4499 ret
= riscv_csrrw_do64(env
, csrno
, &old_value
,
4500 int128_getlo(new_value
),
4501 int128_getlo(write_mask
));
4502 if (ret
== RISCV_EXCP_NONE
&& ret_value
) {
4503 *ret_value
= int128_make64(old_value
);
4509 * Debugger support. If not in user mode, set env->debugger before the
4510 * riscv_csrrw call and clear it after the call.
4512 RISCVException
riscv_csrrw_debug(CPURISCVState
*env
, int csrno
,
4513 target_ulong
*ret_value
,
4514 target_ulong new_value
,
4515 target_ulong write_mask
)
4518 #if !defined(CONFIG_USER_ONLY)
4519 env
->debugger
= true;
4521 ret
= riscv_csrrw(env
, csrno
, ret_value
, new_value
, write_mask
);
4522 #if !defined(CONFIG_USER_ONLY)
4523 env
->debugger
= false;
4528 static RISCVException
read_jvt(CPURISCVState
*env
, int csrno
,
4532 return RISCV_EXCP_NONE
;
4535 static RISCVException
write_jvt(CPURISCVState
*env
, int csrno
,
4539 return RISCV_EXCP_NONE
;
4543 * Control and Status Register function table
4544 * riscv_csr_operations::predicate() must be provided for an implemented CSR
4546 riscv_csr_operations csr_ops
[CSR_TABLE_SIZE
] = {
4547 /* User Floating-Point CSRs */
4548 [CSR_FFLAGS
] = { "fflags", fs
, read_fflags
, write_fflags
},
4549 [CSR_FRM
] = { "frm", fs
, read_frm
, write_frm
},
4550 [CSR_FCSR
] = { "fcsr", fs
, read_fcsr
, write_fcsr
},
4552 [CSR_VSTART
] = { "vstart", vs
, read_vstart
, write_vstart
},
4553 [CSR_VXSAT
] = { "vxsat", vs
, read_vxsat
, write_vxsat
},
4554 [CSR_VXRM
] = { "vxrm", vs
, read_vxrm
, write_vxrm
},
4555 [CSR_VCSR
] = { "vcsr", vs
, read_vcsr
, write_vcsr
},
4556 [CSR_VL
] = { "vl", vs
, read_vl
},
4557 [CSR_VTYPE
] = { "vtype", vs
, read_vtype
},
4558 [CSR_VLENB
] = { "vlenb", vs
, read_vlenb
},
4559 /* User Timers and Counters */
4560 [CSR_CYCLE
] = { "cycle", ctr
, read_hpmcounter
},
4561 [CSR_INSTRET
] = { "instret", ctr
, read_hpmcounter
},
4562 [CSR_CYCLEH
] = { "cycleh", ctr32
, read_hpmcounterh
},
4563 [CSR_INSTRETH
] = { "instreth", ctr32
, read_hpmcounterh
},
4566 * In privileged mode, the monitor will have to emulate TIME CSRs only if
4567 * rdtime callback is not provided by machine/platform emulation.
4569 [CSR_TIME
] = { "time", ctr
, read_time
},
4570 [CSR_TIMEH
] = { "timeh", ctr32
, read_timeh
},
4572 /* Crypto Extension */
4573 [CSR_SEED
] = { "seed", seed
, NULL
, NULL
, rmw_seed
},
4575 /* Zcmt Extension */
4576 [CSR_JVT
] = {"jvt", zcmt
, read_jvt
, write_jvt
},
4578 #if !defined(CONFIG_USER_ONLY)
4579 /* Machine Timers and Counters */
4580 [CSR_MCYCLE
] = { "mcycle", any
, read_hpmcounter
,
4581 write_mhpmcounter
},
4582 [CSR_MINSTRET
] = { "minstret", any
, read_hpmcounter
,
4583 write_mhpmcounter
},
4584 [CSR_MCYCLEH
] = { "mcycleh", any32
, read_hpmcounterh
,
4585 write_mhpmcounterh
},
4586 [CSR_MINSTRETH
] = { "minstreth", any32
, read_hpmcounterh
,
4587 write_mhpmcounterh
},
4589 /* Machine Information Registers */
4590 [CSR_MVENDORID
] = { "mvendorid", any
, read_mvendorid
},
4591 [CSR_MARCHID
] = { "marchid", any
, read_marchid
},
4592 [CSR_MIMPID
] = { "mimpid", any
, read_mimpid
},
4593 [CSR_MHARTID
] = { "mhartid", any
, read_mhartid
},
4595 [CSR_MCONFIGPTR
] = { "mconfigptr", any
, read_zero
,
4596 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4597 /* Machine Trap Setup */
4598 [CSR_MSTATUS
] = { "mstatus", any
, read_mstatus
, write_mstatus
,
4599 NULL
, read_mstatus_i128
},
4600 [CSR_MISA
] = { "misa", any
, read_misa
, write_misa
,
4601 NULL
, read_misa_i128
},
4602 [CSR_MIDELEG
] = { "mideleg", any
, NULL
, NULL
, rmw_mideleg
},
4603 [CSR_MEDELEG
] = { "medeleg", any
, read_medeleg
, write_medeleg
},
4604 [CSR_MIE
] = { "mie", any
, NULL
, NULL
, rmw_mie
},
4605 [CSR_MTVEC
] = { "mtvec", any
, read_mtvec
, write_mtvec
},
4606 [CSR_MCOUNTEREN
] = { "mcounteren", umode
, read_mcounteren
,
4609 [CSR_MSTATUSH
] = { "mstatush", any32
, read_mstatush
,
4612 /* Machine Trap Handling */
4613 [CSR_MSCRATCH
] = { "mscratch", any
, read_mscratch
, write_mscratch
,
4614 NULL
, read_mscratch_i128
, write_mscratch_i128
},
4615 [CSR_MEPC
] = { "mepc", any
, read_mepc
, write_mepc
},
4616 [CSR_MCAUSE
] = { "mcause", any
, read_mcause
, write_mcause
},
4617 [CSR_MTVAL
] = { "mtval", any
, read_mtval
, write_mtval
},
4618 [CSR_MIP
] = { "mip", any
, NULL
, NULL
, rmw_mip
},
4620 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
4621 [CSR_MISELECT
] = { "miselect", aia_any
, NULL
, NULL
, rmw_xiselect
},
4622 [CSR_MIREG
] = { "mireg", aia_any
, NULL
, NULL
, rmw_xireg
},
4624 /* Machine-Level Interrupts (AIA) */
4625 [CSR_MTOPEI
] = { "mtopei", aia_any
, NULL
, NULL
, rmw_xtopei
},
4626 [CSR_MTOPI
] = { "mtopi", aia_any
, read_mtopi
},
4628 /* Virtual Interrupts for Supervisor Level (AIA) */
4629 [CSR_MVIEN
] = { "mvien", aia_any
, NULL
, NULL
, rmw_mvien
},
4630 [CSR_MVIP
] = { "mvip", aia_any
, NULL
, NULL
, rmw_mvip
},
4632 /* Machine-Level High-Half CSRs (AIA) */
4633 [CSR_MIDELEGH
] = { "midelegh", aia_any32
, NULL
, NULL
, rmw_midelegh
},
4634 [CSR_MIEH
] = { "mieh", aia_any32
, NULL
, NULL
, rmw_mieh
},
4635 [CSR_MVIENH
] = { "mvienh", aia_any32
, NULL
, NULL
, rmw_mvienh
},
4636 [CSR_MVIPH
] = { "mviph", aia_any32
, NULL
, NULL
, rmw_mviph
},
4637 [CSR_MIPH
] = { "miph", aia_any32
, NULL
, NULL
, rmw_miph
},
4639 /* Execution environment configuration */
4640 [CSR_MENVCFG
] = { "menvcfg", umode
, read_menvcfg
, write_menvcfg
,
4641 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4642 [CSR_MENVCFGH
] = { "menvcfgh", umode32
, read_menvcfgh
, write_menvcfgh
,
4643 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4644 [CSR_SENVCFG
] = { "senvcfg", smode
, read_senvcfg
, write_senvcfg
,
4645 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4646 [CSR_HENVCFG
] = { "henvcfg", hmode
, read_henvcfg
, write_henvcfg
,
4647 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4648 [CSR_HENVCFGH
] = { "henvcfgh", hmode32
, read_henvcfgh
, write_henvcfgh
,
4649 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4651 /* Smstateen extension CSRs */
4652 [CSR_MSTATEEN0
] = { "mstateen0", mstateen
, read_mstateen
, write_mstateen0
,
4653 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4654 [CSR_MSTATEEN0H
] = { "mstateen0h", mstateen
, read_mstateenh
,
4656 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4657 [CSR_MSTATEEN1
] = { "mstateen1", mstateen
, read_mstateen
,
4659 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4660 [CSR_MSTATEEN1H
] = { "mstateen1h", mstateen
, read_mstateenh
,
4661 write_mstateenh_1_3
,
4662 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4663 [CSR_MSTATEEN2
] = { "mstateen2", mstateen
, read_mstateen
,
4665 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4666 [CSR_MSTATEEN2H
] = { "mstateen2h", mstateen
, read_mstateenh
,
4667 write_mstateenh_1_3
,
4668 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4669 [CSR_MSTATEEN3
] = { "mstateen3", mstateen
, read_mstateen
,
4671 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4672 [CSR_MSTATEEN3H
] = { "mstateen3h", mstateen
, read_mstateenh
,
4673 write_mstateenh_1_3
,
4674 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4675 [CSR_HSTATEEN0
] = { "hstateen0", hstateen
, read_hstateen
, write_hstateen0
,
4676 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4677 [CSR_HSTATEEN0H
] = { "hstateen0h", hstateenh
, read_hstateenh
,
4679 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4680 [CSR_HSTATEEN1
] = { "hstateen1", hstateen
, read_hstateen
,
4682 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4683 [CSR_HSTATEEN1H
] = { "hstateen1h", hstateenh
, read_hstateenh
,
4684 write_hstateenh_1_3
,
4685 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4686 [CSR_HSTATEEN2
] = { "hstateen2", hstateen
, read_hstateen
,
4688 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4689 [CSR_HSTATEEN2H
] = { "hstateen2h", hstateenh
, read_hstateenh
,
4690 write_hstateenh_1_3
,
4691 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4692 [CSR_HSTATEEN3
] = { "hstateen3", hstateen
, read_hstateen
,
4694 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4695 [CSR_HSTATEEN3H
] = { "hstateen3h", hstateenh
, read_hstateenh
,
4696 write_hstateenh_1_3
,
4697 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4698 [CSR_SSTATEEN0
] = { "sstateen0", sstateen
, read_sstateen
, write_sstateen0
,
4699 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4700 [CSR_SSTATEEN1
] = { "sstateen1", sstateen
, read_sstateen
,
4702 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4703 [CSR_SSTATEEN2
] = { "sstateen2", sstateen
, read_sstateen
,
4705 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4706 [CSR_SSTATEEN3
] = { "sstateen3", sstateen
, read_sstateen
,
4708 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4710 /* Supervisor Trap Setup */
4711 [CSR_SSTATUS
] = { "sstatus", smode
, read_sstatus
, write_sstatus
,
4712 NULL
, read_sstatus_i128
},
4713 [CSR_SIE
] = { "sie", smode
, NULL
, NULL
, rmw_sie
},
4714 [CSR_STVEC
] = { "stvec", smode
, read_stvec
, write_stvec
},
4715 [CSR_SCOUNTEREN
] = { "scounteren", smode
, read_scounteren
,
4718 /* Supervisor Trap Handling */
4719 [CSR_SSCRATCH
] = { "sscratch", smode
, read_sscratch
, write_sscratch
,
4720 NULL
, read_sscratch_i128
, write_sscratch_i128
},
4721 [CSR_SEPC
] = { "sepc", smode
, read_sepc
, write_sepc
},
4722 [CSR_SCAUSE
] = { "scause", smode
, read_scause
, write_scause
},
4723 [CSR_STVAL
] = { "stval", smode
, read_stval
, write_stval
},
4724 [CSR_SIP
] = { "sip", smode
, NULL
, NULL
, rmw_sip
},
4725 [CSR_STIMECMP
] = { "stimecmp", sstc
, read_stimecmp
, write_stimecmp
,
4726 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4727 [CSR_STIMECMPH
] = { "stimecmph", sstc_32
, read_stimecmph
, write_stimecmph
,
4728 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4729 [CSR_VSTIMECMP
] = { "vstimecmp", sstc
, read_vstimecmp
,
4731 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4732 [CSR_VSTIMECMPH
] = { "vstimecmph", sstc_32
, read_vstimecmph
,
4734 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4736 /* Supervisor Protection and Translation */
4737 [CSR_SATP
] = { "satp", satp
, read_satp
, write_satp
},
4739 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
4740 [CSR_SISELECT
] = { "siselect", aia_smode
, NULL
, NULL
, rmw_xiselect
},
4741 [CSR_SIREG
] = { "sireg", aia_smode
, NULL
, NULL
, rmw_xireg
},
4743 /* Supervisor-Level Interrupts (AIA) */
4744 [CSR_STOPEI
] = { "stopei", aia_smode
, NULL
, NULL
, rmw_xtopei
},
4745 [CSR_STOPI
] = { "stopi", aia_smode
, read_stopi
},
4747 /* Supervisor-Level High-Half CSRs (AIA) */
4748 [CSR_SIEH
] = { "sieh", aia_smode32
, NULL
, NULL
, rmw_sieh
},
4749 [CSR_SIPH
] = { "siph", aia_smode32
, NULL
, NULL
, rmw_siph
},
4751 [CSR_HSTATUS
] = { "hstatus", hmode
, read_hstatus
, write_hstatus
,
4752 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4753 [CSR_HEDELEG
] = { "hedeleg", hmode
, read_hedeleg
, write_hedeleg
,
4754 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4755 [CSR_HIDELEG
] = { "hideleg", hmode
, NULL
, NULL
, rmw_hideleg
,
4756 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4757 [CSR_HVIP
] = { "hvip", hmode
, NULL
, NULL
, rmw_hvip
,
4758 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4759 [CSR_HIP
] = { "hip", hmode
, NULL
, NULL
, rmw_hip
,
4760 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4761 [CSR_HIE
] = { "hie", hmode
, NULL
, NULL
, rmw_hie
,
4762 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4763 [CSR_HCOUNTEREN
] = { "hcounteren", hmode
, read_hcounteren
,
4765 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4766 [CSR_HGEIE
] = { "hgeie", hmode
, read_hgeie
, write_hgeie
,
4767 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4768 [CSR_HTVAL
] = { "htval", hmode
, read_htval
, write_htval
,
4769 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4770 [CSR_HTINST
] = { "htinst", hmode
, read_htinst
, write_htinst
,
4771 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4772 [CSR_HGEIP
] = { "hgeip", hmode
, read_hgeip
,
4773 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4774 [CSR_HGATP
] = { "hgatp", hgatp
, read_hgatp
, write_hgatp
,
4775 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4776 [CSR_HTIMEDELTA
] = { "htimedelta", hmode
, read_htimedelta
,
4778 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4779 [CSR_HTIMEDELTAH
] = { "htimedeltah", hmode32
, read_htimedeltah
,
4781 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4783 [CSR_VSSTATUS
] = { "vsstatus", hmode
, read_vsstatus
,
4785 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4786 [CSR_VSIP
] = { "vsip", hmode
, NULL
, NULL
, rmw_vsip
,
4787 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4788 [CSR_VSIE
] = { "vsie", hmode
, NULL
, NULL
, rmw_vsie
,
4789 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4790 [CSR_VSTVEC
] = { "vstvec", hmode
, read_vstvec
, write_vstvec
,
4791 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4792 [CSR_VSSCRATCH
] = { "vsscratch", hmode
, read_vsscratch
,
4794 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4795 [CSR_VSEPC
] = { "vsepc", hmode
, read_vsepc
, write_vsepc
,
4796 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4797 [CSR_VSCAUSE
] = { "vscause", hmode
, read_vscause
, write_vscause
,
4798 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4799 [CSR_VSTVAL
] = { "vstval", hmode
, read_vstval
, write_vstval
,
4800 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4801 [CSR_VSATP
] = { "vsatp", hmode
, read_vsatp
, write_vsatp
,
4802 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4804 [CSR_MTVAL2
] = { "mtval2", hmode
, read_mtval2
, write_mtval2
,
4805 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4806 [CSR_MTINST
] = { "mtinst", hmode
, read_mtinst
, write_mtinst
,
4807 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4809 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
4810 [CSR_HVIEN
] = { "hvien", aia_hmode
, NULL
, NULL
, rmw_hvien
},
4811 [CSR_HVICTL
] = { "hvictl", aia_hmode
, read_hvictl
,
4813 [CSR_HVIPRIO1
] = { "hviprio1", aia_hmode
, read_hviprio1
,
4815 [CSR_HVIPRIO2
] = { "hviprio2", aia_hmode
, read_hviprio2
,
4818 * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA)
4820 [CSR_VSISELECT
] = { "vsiselect", aia_hmode
, NULL
, NULL
,
4822 [CSR_VSIREG
] = { "vsireg", aia_hmode
, NULL
, NULL
, rmw_xireg
},
4824 /* VS-Level Interrupts (H-extension with AIA) */
4825 [CSR_VSTOPEI
] = { "vstopei", aia_hmode
, NULL
, NULL
, rmw_xtopei
},
4826 [CSR_VSTOPI
] = { "vstopi", aia_hmode
, read_vstopi
},
4828 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
4829 [CSR_HIDELEGH
] = { "hidelegh", aia_hmode32
, NULL
, NULL
,
4831 [CSR_HVIENH
] = { "hvienh", aia_hmode32
, NULL
, NULL
, rmw_hvienh
},
4832 [CSR_HVIPH
] = { "hviph", aia_hmode32
, NULL
, NULL
, rmw_hviph
},
4833 [CSR_HVIPRIO1H
] = { "hviprio1h", aia_hmode32
, read_hviprio1h
,
4835 [CSR_HVIPRIO2H
] = { "hviprio2h", aia_hmode32
, read_hviprio2h
,
4837 [CSR_VSIEH
] = { "vsieh", aia_hmode32
, NULL
, NULL
, rmw_vsieh
},
4838 [CSR_VSIPH
] = { "vsiph", aia_hmode32
, NULL
, NULL
, rmw_vsiph
},
4840 /* Physical Memory Protection */
4841 [CSR_MSECCFG
] = { "mseccfg", have_mseccfg
, read_mseccfg
, write_mseccfg
,
4842 .min_priv_ver
= PRIV_VERSION_1_11_0
},
4843 [CSR_PMPCFG0
] = { "pmpcfg0", pmp
, read_pmpcfg
, write_pmpcfg
},
4844 [CSR_PMPCFG1
] = { "pmpcfg1", pmp
, read_pmpcfg
, write_pmpcfg
},
4845 [CSR_PMPCFG2
] = { "pmpcfg2", pmp
, read_pmpcfg
, write_pmpcfg
},
4846 [CSR_PMPCFG3
] = { "pmpcfg3", pmp
, read_pmpcfg
, write_pmpcfg
},
4847 [CSR_PMPADDR0
] = { "pmpaddr0", pmp
, read_pmpaddr
, write_pmpaddr
},
4848 [CSR_PMPADDR1
] = { "pmpaddr1", pmp
, read_pmpaddr
, write_pmpaddr
},
4849 [CSR_PMPADDR2
] = { "pmpaddr2", pmp
, read_pmpaddr
, write_pmpaddr
},
4850 [CSR_PMPADDR3
] = { "pmpaddr3", pmp
, read_pmpaddr
, write_pmpaddr
},
4851 [CSR_PMPADDR4
] = { "pmpaddr4", pmp
, read_pmpaddr
, write_pmpaddr
},
4852 [CSR_PMPADDR5
] = { "pmpaddr5", pmp
, read_pmpaddr
, write_pmpaddr
},
4853 [CSR_PMPADDR6
] = { "pmpaddr6", pmp
, read_pmpaddr
, write_pmpaddr
},
4854 [CSR_PMPADDR7
] = { "pmpaddr7", pmp
, read_pmpaddr
, write_pmpaddr
},
4855 [CSR_PMPADDR8
] = { "pmpaddr8", pmp
, read_pmpaddr
, write_pmpaddr
},
4856 [CSR_PMPADDR9
] = { "pmpaddr9", pmp
, read_pmpaddr
, write_pmpaddr
},
4857 [CSR_PMPADDR10
] = { "pmpaddr10", pmp
, read_pmpaddr
, write_pmpaddr
},
4858 [CSR_PMPADDR11
] = { "pmpaddr11", pmp
, read_pmpaddr
, write_pmpaddr
},
4859 [CSR_PMPADDR12
] = { "pmpaddr12", pmp
, read_pmpaddr
, write_pmpaddr
},
4860 [CSR_PMPADDR13
] = { "pmpaddr13", pmp
, read_pmpaddr
, write_pmpaddr
},
4861 [CSR_PMPADDR14
] = { "pmpaddr14", pmp
, read_pmpaddr
, write_pmpaddr
},
4862 [CSR_PMPADDR15
] = { "pmpaddr15", pmp
, read_pmpaddr
, write_pmpaddr
},
4865 [CSR_TSELECT
] = { "tselect", debug
, read_tselect
, write_tselect
},
4866 [CSR_TDATA1
] = { "tdata1", debug
, read_tdata
, write_tdata
},
4867 [CSR_TDATA2
] = { "tdata2", debug
, read_tdata
, write_tdata
},
4868 [CSR_TDATA3
] = { "tdata3", debug
, read_tdata
, write_tdata
},
4869 [CSR_TINFO
] = { "tinfo", debug
, read_tinfo
, write_ignore
},
4870 [CSR_MCONTEXT
] = { "mcontext", debug
, read_mcontext
, write_mcontext
},
4872 /* User Pointer Masking */
4873 [CSR_UMTE
] = { "umte", pointer_masking
, read_umte
, write_umte
},
4874 [CSR_UPMMASK
] = { "upmmask", pointer_masking
, read_upmmask
,
4876 [CSR_UPMBASE
] = { "upmbase", pointer_masking
, read_upmbase
,
4878 /* Machine Pointer Masking */
4879 [CSR_MMTE
] = { "mmte", pointer_masking
, read_mmte
, write_mmte
},
4880 [CSR_MPMMASK
] = { "mpmmask", pointer_masking
, read_mpmmask
,
4882 [CSR_MPMBASE
] = { "mpmbase", pointer_masking
, read_mpmbase
,
4884 /* Supervisor Pointer Masking */
4885 [CSR_SMTE
] = { "smte", pointer_masking
, read_smte
, write_smte
},
4886 [CSR_SPMMASK
] = { "spmmask", pointer_masking
, read_spmmask
,
4888 [CSR_SPMBASE
] = { "spmbase", pointer_masking
, read_spmbase
,
4891 /* Performance Counters */
4892 [CSR_HPMCOUNTER3
] = { "hpmcounter3", ctr
, read_hpmcounter
},
4893 [CSR_HPMCOUNTER4
] = { "hpmcounter4", ctr
, read_hpmcounter
},
4894 [CSR_HPMCOUNTER5
] = { "hpmcounter5", ctr
, read_hpmcounter
},
4895 [CSR_HPMCOUNTER6
] = { "hpmcounter6", ctr
, read_hpmcounter
},
4896 [CSR_HPMCOUNTER7
] = { "hpmcounter7", ctr
, read_hpmcounter
},
4897 [CSR_HPMCOUNTER8
] = { "hpmcounter8", ctr
, read_hpmcounter
},
4898 [CSR_HPMCOUNTER9
] = { "hpmcounter9", ctr
, read_hpmcounter
},
4899 [CSR_HPMCOUNTER10
] = { "hpmcounter10", ctr
, read_hpmcounter
},
4900 [CSR_HPMCOUNTER11
] = { "hpmcounter11", ctr
, read_hpmcounter
},
4901 [CSR_HPMCOUNTER12
] = { "hpmcounter12", ctr
, read_hpmcounter
},
4902 [CSR_HPMCOUNTER13
] = { "hpmcounter13", ctr
, read_hpmcounter
},
4903 [CSR_HPMCOUNTER14
] = { "hpmcounter14", ctr
, read_hpmcounter
},
4904 [CSR_HPMCOUNTER15
] = { "hpmcounter15", ctr
, read_hpmcounter
},
4905 [CSR_HPMCOUNTER16
] = { "hpmcounter16", ctr
, read_hpmcounter
},
4906 [CSR_HPMCOUNTER17
] = { "hpmcounter17", ctr
, read_hpmcounter
},
4907 [CSR_HPMCOUNTER18
] = { "hpmcounter18", ctr
, read_hpmcounter
},
4908 [CSR_HPMCOUNTER19
] = { "hpmcounter19", ctr
, read_hpmcounter
},
4909 [CSR_HPMCOUNTER20
] = { "hpmcounter20", ctr
, read_hpmcounter
},
4910 [CSR_HPMCOUNTER21
] = { "hpmcounter21", ctr
, read_hpmcounter
},
4911 [CSR_HPMCOUNTER22
] = { "hpmcounter22", ctr
, read_hpmcounter
},
4912 [CSR_HPMCOUNTER23
] = { "hpmcounter23", ctr
, read_hpmcounter
},
4913 [CSR_HPMCOUNTER24
] = { "hpmcounter24", ctr
, read_hpmcounter
},
4914 [CSR_HPMCOUNTER25
] = { "hpmcounter25", ctr
, read_hpmcounter
},
4915 [CSR_HPMCOUNTER26
] = { "hpmcounter26", ctr
, read_hpmcounter
},
4916 [CSR_HPMCOUNTER27
] = { "hpmcounter27", ctr
, read_hpmcounter
},
4917 [CSR_HPMCOUNTER28
] = { "hpmcounter28", ctr
, read_hpmcounter
},
4918 [CSR_HPMCOUNTER29
] = { "hpmcounter29", ctr
, read_hpmcounter
},
4919 [CSR_HPMCOUNTER30
] = { "hpmcounter30", ctr
, read_hpmcounter
},
4920 [CSR_HPMCOUNTER31
] = { "hpmcounter31", ctr
, read_hpmcounter
},
4922 [CSR_MHPMCOUNTER3
] = { "mhpmcounter3", mctr
, read_hpmcounter
,
4923 write_mhpmcounter
},
4924 [CSR_MHPMCOUNTER4
] = { "mhpmcounter4", mctr
, read_hpmcounter
,
4925 write_mhpmcounter
},
4926 [CSR_MHPMCOUNTER5
] = { "mhpmcounter5", mctr
, read_hpmcounter
,
4927 write_mhpmcounter
},
4928 [CSR_MHPMCOUNTER6
] = { "mhpmcounter6", mctr
, read_hpmcounter
,
4929 write_mhpmcounter
},
4930 [CSR_MHPMCOUNTER7
] = { "mhpmcounter7", mctr
, read_hpmcounter
,
4931 write_mhpmcounter
},
4932 [CSR_MHPMCOUNTER8
] = { "mhpmcounter8", mctr
, read_hpmcounter
,
4933 write_mhpmcounter
},
4934 [CSR_MHPMCOUNTER9
] = { "mhpmcounter9", mctr
, read_hpmcounter
,
4935 write_mhpmcounter
},
4936 [CSR_MHPMCOUNTER10
] = { "mhpmcounter10", mctr
, read_hpmcounter
,
4937 write_mhpmcounter
},
4938 [CSR_MHPMCOUNTER11
] = { "mhpmcounter11", mctr
, read_hpmcounter
,
4939 write_mhpmcounter
},
4940 [CSR_MHPMCOUNTER12
] = { "mhpmcounter12", mctr
, read_hpmcounter
,
4941 write_mhpmcounter
},
4942 [CSR_MHPMCOUNTER13
] = { "mhpmcounter13", mctr
, read_hpmcounter
,
4943 write_mhpmcounter
},
4944 [CSR_MHPMCOUNTER14
] = { "mhpmcounter14", mctr
, read_hpmcounter
,
4945 write_mhpmcounter
},
4946 [CSR_MHPMCOUNTER15
] = { "mhpmcounter15", mctr
, read_hpmcounter
,
4947 write_mhpmcounter
},
4948 [CSR_MHPMCOUNTER16
] = { "mhpmcounter16", mctr
, read_hpmcounter
,
4949 write_mhpmcounter
},
4950 [CSR_MHPMCOUNTER17
] = { "mhpmcounter17", mctr
, read_hpmcounter
,
4951 write_mhpmcounter
},
4952 [CSR_MHPMCOUNTER18
] = { "mhpmcounter18", mctr
, read_hpmcounter
,
4953 write_mhpmcounter
},
4954 [CSR_MHPMCOUNTER19
] = { "mhpmcounter19", mctr
, read_hpmcounter
,
4955 write_mhpmcounter
},
4956 [CSR_MHPMCOUNTER20
] = { "mhpmcounter20", mctr
, read_hpmcounter
,
4957 write_mhpmcounter
},
4958 [CSR_MHPMCOUNTER21
] = { "mhpmcounter21", mctr
, read_hpmcounter
,
4959 write_mhpmcounter
},
4960 [CSR_MHPMCOUNTER22
] = { "mhpmcounter22", mctr
, read_hpmcounter
,
4961 write_mhpmcounter
},
4962 [CSR_MHPMCOUNTER23
] = { "mhpmcounter23", mctr
, read_hpmcounter
,
4963 write_mhpmcounter
},
4964 [CSR_MHPMCOUNTER24
] = { "mhpmcounter24", mctr
, read_hpmcounter
,
4965 write_mhpmcounter
},
4966 [CSR_MHPMCOUNTER25
] = { "mhpmcounter25", mctr
, read_hpmcounter
,
4967 write_mhpmcounter
},
4968 [CSR_MHPMCOUNTER26
] = { "mhpmcounter26", mctr
, read_hpmcounter
,
4969 write_mhpmcounter
},
4970 [CSR_MHPMCOUNTER27
] = { "mhpmcounter27", mctr
, read_hpmcounter
,
4971 write_mhpmcounter
},
4972 [CSR_MHPMCOUNTER28
] = { "mhpmcounter28", mctr
, read_hpmcounter
,
4973 write_mhpmcounter
},
4974 [CSR_MHPMCOUNTER29
] = { "mhpmcounter29", mctr
, read_hpmcounter
,
4975 write_mhpmcounter
},
4976 [CSR_MHPMCOUNTER30
] = { "mhpmcounter30", mctr
, read_hpmcounter
,
4977 write_mhpmcounter
},
4978 [CSR_MHPMCOUNTER31
] = { "mhpmcounter31", mctr
, read_hpmcounter
,
4979 write_mhpmcounter
},
4981 [CSR_MCOUNTINHIBIT
] = { "mcountinhibit", any
, read_mcountinhibit
,
4982 write_mcountinhibit
,
4983 .min_priv_ver
= PRIV_VERSION_1_11_0
},
4985 [CSR_MHPMEVENT3
] = { "mhpmevent3", any
, read_mhpmevent
,
4987 [CSR_MHPMEVENT4
] = { "mhpmevent4", any
, read_mhpmevent
,
4989 [CSR_MHPMEVENT5
] = { "mhpmevent5", any
, read_mhpmevent
,
4991 [CSR_MHPMEVENT6
] = { "mhpmevent6", any
, read_mhpmevent
,
4993 [CSR_MHPMEVENT7
] = { "mhpmevent7", any
, read_mhpmevent
,
4995 [CSR_MHPMEVENT8
] = { "mhpmevent8", any
, read_mhpmevent
,
4997 [CSR_MHPMEVENT9
] = { "mhpmevent9", any
, read_mhpmevent
,
4999 [CSR_MHPMEVENT10
] = { "mhpmevent10", any
, read_mhpmevent
,
5001 [CSR_MHPMEVENT11
] = { "mhpmevent11", any
, read_mhpmevent
,
5003 [CSR_MHPMEVENT12
] = { "mhpmevent12", any
, read_mhpmevent
,
5005 [CSR_MHPMEVENT13
] = { "mhpmevent13", any
, read_mhpmevent
,
5007 [CSR_MHPMEVENT14
] = { "mhpmevent14", any
, read_mhpmevent
,
5009 [CSR_MHPMEVENT15
] = { "mhpmevent15", any
, read_mhpmevent
,
5011 [CSR_MHPMEVENT16
] = { "mhpmevent16", any
, read_mhpmevent
,
5013 [CSR_MHPMEVENT17
] = { "mhpmevent17", any
, read_mhpmevent
,
5015 [CSR_MHPMEVENT18
] = { "mhpmevent18", any
, read_mhpmevent
,
5017 [CSR_MHPMEVENT19
] = { "mhpmevent19", any
, read_mhpmevent
,
5019 [CSR_MHPMEVENT20
] = { "mhpmevent20", any
, read_mhpmevent
,
5021 [CSR_MHPMEVENT21
] = { "mhpmevent21", any
, read_mhpmevent
,
5023 [CSR_MHPMEVENT22
] = { "mhpmevent22", any
, read_mhpmevent
,
5025 [CSR_MHPMEVENT23
] = { "mhpmevent23", any
, read_mhpmevent
,
5027 [CSR_MHPMEVENT24
] = { "mhpmevent24", any
, read_mhpmevent
,
5029 [CSR_MHPMEVENT25
] = { "mhpmevent25", any
, read_mhpmevent
,
5031 [CSR_MHPMEVENT26
] = { "mhpmevent26", any
, read_mhpmevent
,
5033 [CSR_MHPMEVENT27
] = { "mhpmevent27", any
, read_mhpmevent
,
5035 [CSR_MHPMEVENT28
] = { "mhpmevent28", any
, read_mhpmevent
,
5037 [CSR_MHPMEVENT29
] = { "mhpmevent29", any
, read_mhpmevent
,
5039 [CSR_MHPMEVENT30
] = { "mhpmevent30", any
, read_mhpmevent
,
5041 [CSR_MHPMEVENT31
] = { "mhpmevent31", any
, read_mhpmevent
,
5044 [CSR_MHPMEVENT3H
] = { "mhpmevent3h", sscofpmf
, read_mhpmeventh
,
5046 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5047 [CSR_MHPMEVENT4H
] = { "mhpmevent4h", sscofpmf
, read_mhpmeventh
,
5049 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5050 [CSR_MHPMEVENT5H
] = { "mhpmevent5h", sscofpmf
, read_mhpmeventh
,
5052 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5053 [CSR_MHPMEVENT6H
] = { "mhpmevent6h", sscofpmf
, read_mhpmeventh
,
5055 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5056 [CSR_MHPMEVENT7H
] = { "mhpmevent7h", sscofpmf
, read_mhpmeventh
,
5058 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5059 [CSR_MHPMEVENT8H
] = { "mhpmevent8h", sscofpmf
, read_mhpmeventh
,
5061 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5062 [CSR_MHPMEVENT9H
] = { "mhpmevent9h", sscofpmf
, read_mhpmeventh
,
5064 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5065 [CSR_MHPMEVENT10H
] = { "mhpmevent10h", sscofpmf
, read_mhpmeventh
,
5067 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5068 [CSR_MHPMEVENT11H
] = { "mhpmevent11h", sscofpmf
, read_mhpmeventh
,
5070 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5071 [CSR_MHPMEVENT12H
] = { "mhpmevent12h", sscofpmf
, read_mhpmeventh
,
5073 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5074 [CSR_MHPMEVENT13H
] = { "mhpmevent13h", sscofpmf
, read_mhpmeventh
,
5076 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5077 [CSR_MHPMEVENT14H
] = { "mhpmevent14h", sscofpmf
, read_mhpmeventh
,
5079 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5080 [CSR_MHPMEVENT15H
] = { "mhpmevent15h", sscofpmf
, read_mhpmeventh
,
5082 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5083 [CSR_MHPMEVENT16H
] = { "mhpmevent16h", sscofpmf
, read_mhpmeventh
,
5085 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5086 [CSR_MHPMEVENT17H
] = { "mhpmevent17h", sscofpmf
, read_mhpmeventh
,
5088 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5089 [CSR_MHPMEVENT18H
] = { "mhpmevent18h", sscofpmf
, read_mhpmeventh
,
5091 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5092 [CSR_MHPMEVENT19H
] = { "mhpmevent19h", sscofpmf
, read_mhpmeventh
,
5094 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5095 [CSR_MHPMEVENT20H
] = { "mhpmevent20h", sscofpmf
, read_mhpmeventh
,
5097 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5098 [CSR_MHPMEVENT21H
] = { "mhpmevent21h", sscofpmf
, read_mhpmeventh
,
5100 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5101 [CSR_MHPMEVENT22H
] = { "mhpmevent22h", sscofpmf
, read_mhpmeventh
,
5103 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5104 [CSR_MHPMEVENT23H
] = { "mhpmevent23h", sscofpmf
, read_mhpmeventh
,
5106 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5107 [CSR_MHPMEVENT24H
] = { "mhpmevent24h", sscofpmf
, read_mhpmeventh
,
5109 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5110 [CSR_MHPMEVENT25H
] = { "mhpmevent25h", sscofpmf
, read_mhpmeventh
,
5112 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5113 [CSR_MHPMEVENT26H
] = { "mhpmevent26h", sscofpmf
, read_mhpmeventh
,
5115 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5116 [CSR_MHPMEVENT27H
] = { "mhpmevent27h", sscofpmf
, read_mhpmeventh
,
5118 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5119 [CSR_MHPMEVENT28H
] = { "mhpmevent28h", sscofpmf
, read_mhpmeventh
,
5121 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5122 [CSR_MHPMEVENT29H
] = { "mhpmevent29h", sscofpmf
, read_mhpmeventh
,
5124 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5125 [CSR_MHPMEVENT30H
] = { "mhpmevent30h", sscofpmf
, read_mhpmeventh
,
5127 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5128 [CSR_MHPMEVENT31H
] = { "mhpmevent31h", sscofpmf
, read_mhpmeventh
,
5130 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5132 [CSR_HPMCOUNTER3H
] = { "hpmcounter3h", ctr32
, read_hpmcounterh
},
5133 [CSR_HPMCOUNTER4H
] = { "hpmcounter4h", ctr32
, read_hpmcounterh
},
5134 [CSR_HPMCOUNTER5H
] = { "hpmcounter5h", ctr32
, read_hpmcounterh
},
5135 [CSR_HPMCOUNTER6H
] = { "hpmcounter6h", ctr32
, read_hpmcounterh
},
5136 [CSR_HPMCOUNTER7H
] = { "hpmcounter7h", ctr32
, read_hpmcounterh
},
5137 [CSR_HPMCOUNTER8H
] = { "hpmcounter8h", ctr32
, read_hpmcounterh
},
5138 [CSR_HPMCOUNTER9H
] = { "hpmcounter9h", ctr32
, read_hpmcounterh
},
5139 [CSR_HPMCOUNTER10H
] = { "hpmcounter10h", ctr32
, read_hpmcounterh
},
5140 [CSR_HPMCOUNTER11H
] = { "hpmcounter11h", ctr32
, read_hpmcounterh
},
5141 [CSR_HPMCOUNTER12H
] = { "hpmcounter12h", ctr32
, read_hpmcounterh
},
5142 [CSR_HPMCOUNTER13H
] = { "hpmcounter13h", ctr32
, read_hpmcounterh
},
5143 [CSR_HPMCOUNTER14H
] = { "hpmcounter14h", ctr32
, read_hpmcounterh
},
5144 [CSR_HPMCOUNTER15H
] = { "hpmcounter15h", ctr32
, read_hpmcounterh
},
5145 [CSR_HPMCOUNTER16H
] = { "hpmcounter16h", ctr32
, read_hpmcounterh
},
5146 [CSR_HPMCOUNTER17H
] = { "hpmcounter17h", ctr32
, read_hpmcounterh
},
5147 [CSR_HPMCOUNTER18H
] = { "hpmcounter18h", ctr32
, read_hpmcounterh
},
5148 [CSR_HPMCOUNTER19H
] = { "hpmcounter19h", ctr32
, read_hpmcounterh
},
5149 [CSR_HPMCOUNTER20H
] = { "hpmcounter20h", ctr32
, read_hpmcounterh
},
5150 [CSR_HPMCOUNTER21H
] = { "hpmcounter21h", ctr32
, read_hpmcounterh
},
5151 [CSR_HPMCOUNTER22H
] = { "hpmcounter22h", ctr32
, read_hpmcounterh
},
5152 [CSR_HPMCOUNTER23H
] = { "hpmcounter23h", ctr32
, read_hpmcounterh
},
5153 [CSR_HPMCOUNTER24H
] = { "hpmcounter24h", ctr32
, read_hpmcounterh
},
5154 [CSR_HPMCOUNTER25H
] = { "hpmcounter25h", ctr32
, read_hpmcounterh
},
5155 [CSR_HPMCOUNTER26H
] = { "hpmcounter26h", ctr32
, read_hpmcounterh
},
5156 [CSR_HPMCOUNTER27H
] = { "hpmcounter27h", ctr32
, read_hpmcounterh
},
5157 [CSR_HPMCOUNTER28H
] = { "hpmcounter28h", ctr32
, read_hpmcounterh
},
5158 [CSR_HPMCOUNTER29H
] = { "hpmcounter29h", ctr32
, read_hpmcounterh
},
5159 [CSR_HPMCOUNTER30H
] = { "hpmcounter30h", ctr32
, read_hpmcounterh
},
5160 [CSR_HPMCOUNTER31H
] = { "hpmcounter31h", ctr32
, read_hpmcounterh
},
5162 [CSR_MHPMCOUNTER3H
] = { "mhpmcounter3h", mctr32
, read_hpmcounterh
,
5163 write_mhpmcounterh
},
5164 [CSR_MHPMCOUNTER4H
] = { "mhpmcounter4h", mctr32
, read_hpmcounterh
,
5165 write_mhpmcounterh
},
5166 [CSR_MHPMCOUNTER5H
] = { "mhpmcounter5h", mctr32
, read_hpmcounterh
,
5167 write_mhpmcounterh
},
5168 [CSR_MHPMCOUNTER6H
] = { "mhpmcounter6h", mctr32
, read_hpmcounterh
,
5169 write_mhpmcounterh
},
5170 [CSR_MHPMCOUNTER7H
] = { "mhpmcounter7h", mctr32
, read_hpmcounterh
,
5171 write_mhpmcounterh
},
5172 [CSR_MHPMCOUNTER8H
] = { "mhpmcounter8h", mctr32
, read_hpmcounterh
,
5173 write_mhpmcounterh
},
5174 [CSR_MHPMCOUNTER9H
] = { "mhpmcounter9h", mctr32
, read_hpmcounterh
,
5175 write_mhpmcounterh
},
5176 [CSR_MHPMCOUNTER10H
] = { "mhpmcounter10h", mctr32
, read_hpmcounterh
,
5177 write_mhpmcounterh
},
5178 [CSR_MHPMCOUNTER11H
] = { "mhpmcounter11h", mctr32
, read_hpmcounterh
,
5179 write_mhpmcounterh
},
5180 [CSR_MHPMCOUNTER12H
] = { "mhpmcounter12h", mctr32
, read_hpmcounterh
,
5181 write_mhpmcounterh
},
5182 [CSR_MHPMCOUNTER13H
] = { "mhpmcounter13h", mctr32
, read_hpmcounterh
,
5183 write_mhpmcounterh
},
5184 [CSR_MHPMCOUNTER14H
] = { "mhpmcounter14h", mctr32
, read_hpmcounterh
,
5185 write_mhpmcounterh
},
5186 [CSR_MHPMCOUNTER15H
] = { "mhpmcounter15h", mctr32
, read_hpmcounterh
,
5187 write_mhpmcounterh
},
5188 [CSR_MHPMCOUNTER16H
] = { "mhpmcounter16h", mctr32
, read_hpmcounterh
,
5189 write_mhpmcounterh
},
5190 [CSR_MHPMCOUNTER17H
] = { "mhpmcounter17h", mctr32
, read_hpmcounterh
,
5191 write_mhpmcounterh
},
5192 [CSR_MHPMCOUNTER18H
] = { "mhpmcounter18h", mctr32
, read_hpmcounterh
,
5193 write_mhpmcounterh
},
5194 [CSR_MHPMCOUNTER19H
] = { "mhpmcounter19h", mctr32
, read_hpmcounterh
,
5195 write_mhpmcounterh
},
5196 [CSR_MHPMCOUNTER20H
] = { "mhpmcounter20h", mctr32
, read_hpmcounterh
,
5197 write_mhpmcounterh
},
5198 [CSR_MHPMCOUNTER21H
] = { "mhpmcounter21h", mctr32
, read_hpmcounterh
,
5199 write_mhpmcounterh
},
5200 [CSR_MHPMCOUNTER22H
] = { "mhpmcounter22h", mctr32
, read_hpmcounterh
,
5201 write_mhpmcounterh
},
5202 [CSR_MHPMCOUNTER23H
] = { "mhpmcounter23h", mctr32
, read_hpmcounterh
,
5203 write_mhpmcounterh
},
5204 [CSR_MHPMCOUNTER24H
] = { "mhpmcounter24h", mctr32
, read_hpmcounterh
,
5205 write_mhpmcounterh
},
5206 [CSR_MHPMCOUNTER25H
] = { "mhpmcounter25h", mctr32
, read_hpmcounterh
,
5207 write_mhpmcounterh
},
5208 [CSR_MHPMCOUNTER26H
] = { "mhpmcounter26h", mctr32
, read_hpmcounterh
,
5209 write_mhpmcounterh
},
5210 [CSR_MHPMCOUNTER27H
] = { "mhpmcounter27h", mctr32
, read_hpmcounterh
,
5211 write_mhpmcounterh
},
5212 [CSR_MHPMCOUNTER28H
] = { "mhpmcounter28h", mctr32
, read_hpmcounterh
,
5213 write_mhpmcounterh
},
5214 [CSR_MHPMCOUNTER29H
] = { "mhpmcounter29h", mctr32
, read_hpmcounterh
,
5215 write_mhpmcounterh
},
5216 [CSR_MHPMCOUNTER30H
] = { "mhpmcounter30h", mctr32
, read_hpmcounterh
,
5217 write_mhpmcounterh
},
5218 [CSR_MHPMCOUNTER31H
] = { "mhpmcounter31h", mctr32
, read_hpmcounterh
,
5219 write_mhpmcounterh
},
5220 [CSR_SCOUNTOVF
] = { "scountovf", sscofpmf
, read_scountovf
,
5221 .min_priv_ver
= PRIV_VERSION_1_12_0
},
5223 #endif /* !CONFIG_USER_ONLY */