4 * Copyright (c) 2007 CodeSourcery
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "exec/helper-proto.h"
22 #include "exec/exec-all.h"
23 #include "exec/cpu_ldst.h"
24 #include "exec/semihost.h"
26 #if defined(CONFIG_USER_ONLY)
28 void m68k_cpu_do_interrupt(CPUState
*cs
)
30 cs
->exception_index
= -1;
33 static inline void do_interrupt_m68k_hardirq(CPUM68KState
*env
)
39 /* Try to fill the TLB and return an exception if error. If retaddr is
40 NULL, it means that the function was called in C code (i.e. not
41 from generated code or from helper.c) */
42 void tlb_fill(CPUState
*cs
, target_ulong addr
, MMUAccessType access_type
,
43 int mmu_idx
, uintptr_t retaddr
)
47 ret
= m68k_cpu_handle_mmu_fault(cs
, addr
, access_type
, mmu_idx
);
50 /* now we have a real cpu fault */
51 cpu_restore_state(cs
, retaddr
);
57 static void do_rte(CPUM68KState
*env
)
63 fmt
= cpu_ldl_kernel(env
, sp
);
64 env
->pc
= cpu_ldl_kernel(env
, sp
+ 4);
65 sp
|= (fmt
>> 28) & 3;
66 env
->aregs
[7] = sp
+ 8;
68 helper_set_sr(env
, fmt
);
71 static void do_interrupt_all(CPUM68KState
*env
, int is_hw
)
73 CPUState
*cs
= CPU(m68k_env_get_cpu(env
));
83 switch (cs
->exception_index
) {
85 /* Return from an exception. */
89 if (semihosting_enabled()
90 && (env
->sr
& SR_S
) != 0
92 && cpu_lduw_code(env
, env
->pc
- 4) == 0x4e71
93 && cpu_ldl_code(env
, env
->pc
) == 0x4e7bf000) {
95 do_m68k_semihosting(env
, env
->dregs
[0]);
99 cs
->exception_index
= EXCP_HLT
;
103 if (cs
->exception_index
>= EXCP_TRAP0
104 && cs
->exception_index
<= EXCP_TRAP15
) {
105 /* Move the PC after the trap instruction. */
110 vector
= cs
->exception_index
<< 2;
115 fmt
|= cpu_m68k_get_ccr(env
);
119 env
->sr
= (env
->sr
& ~SR_I
) | (env
->pending_level
<< SR_I_SHIFT
);
124 fmt
|= (sp
& 3) << 28;
126 /* ??? This could cause MMU faults. */
129 cpu_stl_kernel(env
, sp
, retaddr
);
131 cpu_stl_kernel(env
, sp
, fmt
);
133 /* Jump to vector. */
134 env
->pc
= cpu_ldl_kernel(env
, env
->vbr
+ vector
);
137 void m68k_cpu_do_interrupt(CPUState
*cs
)
139 M68kCPU
*cpu
= M68K_CPU(cs
);
140 CPUM68KState
*env
= &cpu
->env
;
142 do_interrupt_all(env
, 0);
145 static inline void do_interrupt_m68k_hardirq(CPUM68KState
*env
)
147 do_interrupt_all(env
, 1);
151 bool m68k_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
153 M68kCPU
*cpu
= M68K_CPU(cs
);
154 CPUM68KState
*env
= &cpu
->env
;
156 if (interrupt_request
& CPU_INTERRUPT_HARD
157 && ((env
->sr
& SR_I
) >> SR_I_SHIFT
) < env
->pending_level
) {
158 /* Real hardware gets the interrupt vector via an IACK cycle
159 at this point. Current emulated hardware doesn't rely on
160 this, so we provide/save the vector when the interrupt is
162 cs
->exception_index
= env
->pending_vector
;
163 do_interrupt_m68k_hardirq(env
);
169 static void raise_exception_ra(CPUM68KState
*env
, int tt
, uintptr_t raddr
)
171 CPUState
*cs
= CPU(m68k_env_get_cpu(env
));
173 cs
->exception_index
= tt
;
174 cpu_loop_exit_restore(cs
, raddr
);
177 static void raise_exception(CPUM68KState
*env
, int tt
)
179 raise_exception_ra(env
, tt
, 0);
182 void HELPER(raise_exception
)(CPUM68KState
*env
, uint32_t tt
)
184 raise_exception(env
, tt
);
187 void HELPER(divuw
)(CPUM68KState
*env
, int destr
, uint32_t den
)
189 uint32_t num
= env
->dregs
[destr
];
193 raise_exception_ra(env
, EXCP_DIV0
, GETPC());
198 env
->cc_c
= 0; /* always cleared, even if overflow */
201 /* real 68040 keeps N and unset Z on overflow,
202 * whereas documentation says "undefined"
207 env
->dregs
[destr
] = deposit32(quot
, 16, 16, rem
);
208 env
->cc_z
= (int16_t)quot
;
209 env
->cc_n
= (int16_t)quot
;
213 void HELPER(divsw
)(CPUM68KState
*env
, int destr
, int32_t den
)
215 int32_t num
= env
->dregs
[destr
];
219 raise_exception_ra(env
, EXCP_DIV0
, GETPC());
224 env
->cc_c
= 0; /* always cleared, even if overflow */
225 if (quot
!= (int16_t)quot
) {
227 /* nothing else is modified */
228 /* real 68040 keeps N and unset Z on overflow,
229 * whereas documentation says "undefined"
234 env
->dregs
[destr
] = deposit32(quot
, 16, 16, rem
);
235 env
->cc_z
= (int16_t)quot
;
236 env
->cc_n
= (int16_t)quot
;
240 void HELPER(divul
)(CPUM68KState
*env
, int numr
, int regr
, uint32_t den
)
242 uint32_t num
= env
->dregs
[numr
];
246 raise_exception_ra(env
, EXCP_DIV0
, GETPC());
256 if (m68k_feature(env
, M68K_FEATURE_CF_ISA_A
)) {
258 env
->dregs
[numr
] = quot
;
260 env
->dregs
[regr
] = rem
;
263 env
->dregs
[regr
] = rem
;
264 env
->dregs
[numr
] = quot
;
268 void HELPER(divsl
)(CPUM68KState
*env
, int numr
, int regr
, int32_t den
)
270 int32_t num
= env
->dregs
[numr
];
274 raise_exception_ra(env
, EXCP_DIV0
, GETPC());
284 if (m68k_feature(env
, M68K_FEATURE_CF_ISA_A
)) {
286 env
->dregs
[numr
] = quot
;
288 env
->dregs
[regr
] = rem
;
291 env
->dregs
[regr
] = rem
;
292 env
->dregs
[numr
] = quot
;
296 void HELPER(divull
)(CPUM68KState
*env
, int numr
, int regr
, uint32_t den
)
298 uint64_t num
= deposit64(env
->dregs
[numr
], 32, 32, env
->dregs
[regr
]);
303 raise_exception_ra(env
, EXCP_DIV0
, GETPC());
308 env
->cc_c
= 0; /* always cleared, even if overflow */
309 if (quot
> 0xffffffffULL
) {
311 /* real 68040 keeps N and unset Z on overflow,
312 * whereas documentation says "undefined"
322 * If Dq and Dr are the same, the quotient is returned.
323 * therefore we set Dq last.
326 env
->dregs
[regr
] = rem
;
327 env
->dregs
[numr
] = quot
;
330 void HELPER(divsll
)(CPUM68KState
*env
, int numr
, int regr
, int32_t den
)
332 int64_t num
= deposit64(env
->dregs
[numr
], 32, 32, env
->dregs
[regr
]);
337 raise_exception_ra(env
, EXCP_DIV0
, GETPC());
342 env
->cc_c
= 0; /* always cleared, even if overflow */
343 if (quot
!= (int32_t)quot
) {
345 /* real 68040 keeps N and unset Z on overflow,
346 * whereas documentation says "undefined"
356 * If Dq and Dr are the same, the quotient is returned.
357 * therefore we set Dq last.
360 env
->dregs
[regr
] = rem
;
361 env
->dregs
[numr
] = quot
;
364 void HELPER(cas2w
)(CPUM68KState
*env
, uint32_t regs
, uint32_t a1
, uint32_t a2
)
366 uint32_t Dc1
= extract32(regs
, 9, 3);
367 uint32_t Dc2
= extract32(regs
, 6, 3);
368 uint32_t Du1
= extract32(regs
, 3, 3);
369 uint32_t Du2
= extract32(regs
, 0, 3);
370 int16_t c1
= env
->dregs
[Dc1
];
371 int16_t c2
= env
->dregs
[Dc2
];
372 int16_t u1
= env
->dregs
[Du1
];
373 int16_t u2
= env
->dregs
[Du2
];
375 uintptr_t ra
= GETPC();
378 /* Tell the main loop we need to serialize this insn. */
379 cpu_loop_exit_atomic(ENV_GET_CPU(env
), ra
);
381 /* We're executing in a serial context -- no need to be atomic. */
382 l1
= cpu_lduw_data_ra(env
, a1
, ra
);
383 l2
= cpu_lduw_data_ra(env
, a2
, ra
);
384 if (l1
== c1
&& l2
== c2
) {
385 cpu_stw_data_ra(env
, a1
, u1
, ra
);
386 cpu_stw_data_ra(env
, a2
, u2
, ra
);
397 env
->cc_op
= CC_OP_CMPW
;
398 env
->dregs
[Dc1
] = deposit32(env
->dregs
[Dc1
], 0, 16, l1
);
399 env
->dregs
[Dc2
] = deposit32(env
->dregs
[Dc2
], 0, 16, l2
);
402 void HELPER(cas2l
)(CPUM68KState
*env
, uint32_t regs
, uint32_t a1
, uint32_t a2
)
404 uint32_t Dc1
= extract32(regs
, 9, 3);
405 uint32_t Dc2
= extract32(regs
, 6, 3);
406 uint32_t Du1
= extract32(regs
, 3, 3);
407 uint32_t Du2
= extract32(regs
, 0, 3);
408 uint32_t c1
= env
->dregs
[Dc1
];
409 uint32_t c2
= env
->dregs
[Dc2
];
410 uint32_t u1
= env
->dregs
[Du1
];
411 uint32_t u2
= env
->dregs
[Du2
];
413 uintptr_t ra
= GETPC();
414 #if defined(CONFIG_ATOMIC64) && !defined(CONFIG_USER_ONLY)
415 int mmu_idx
= cpu_mmu_index(env
, 0);
420 /* We're executing in a parallel context -- must be atomic. */
421 #ifdef CONFIG_ATOMIC64
423 if ((a1
& 7) == 0 && a2
== a1
+ 4) {
424 c
= deposit64(c2
, 32, 32, c1
);
425 u
= deposit64(u2
, 32, 32, u1
);
426 #ifdef CONFIG_USER_ONLY
427 l
= helper_atomic_cmpxchgq_be(env
, a1
, c
, u
);
429 oi
= make_memop_idx(MO_BEQ
, mmu_idx
);
430 l
= helper_atomic_cmpxchgq_be_mmu(env
, a1
, c
, u
, oi
, ra
);
434 } else if ((a2
& 7) == 0 && a1
== a2
+ 4) {
435 c
= deposit64(c1
, 32, 32, c2
);
436 u
= deposit64(u1
, 32, 32, u2
);
437 #ifdef CONFIG_USER_ONLY
438 l
= helper_atomic_cmpxchgq_be(env
, a2
, c
, u
);
440 oi
= make_memop_idx(MO_BEQ
, mmu_idx
);
441 l
= helper_atomic_cmpxchgq_be_mmu(env
, a2
, c
, u
, oi
, ra
);
448 /* Tell the main loop we need to serialize this insn. */
449 cpu_loop_exit_atomic(ENV_GET_CPU(env
), ra
);
452 /* We're executing in a serial context -- no need to be atomic. */
453 l1
= cpu_ldl_data_ra(env
, a1
, ra
);
454 l2
= cpu_ldl_data_ra(env
, a2
, ra
);
455 if (l1
== c1
&& l2
== c2
) {
456 cpu_stl_data_ra(env
, a1
, u1
, ra
);
457 cpu_stl_data_ra(env
, a2
, u2
, ra
);
468 env
->cc_op
= CC_OP_CMPL
;
469 env
->dregs
[Dc1
] = l1
;
470 env
->dregs
[Dc2
] = l2
;