4 * Copyright (c) 2007 CodeSourcery
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/helper-proto.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
25 #include "semihosting/semihost.h"
27 #if !defined(CONFIG_USER_ONLY)
29 static void cf_rte(CPUM68KState
*env
)
35 fmt
= cpu_ldl_mmuidx_ra(env
, sp
, MMU_KERNEL_IDX
, 0);
36 env
->pc
= cpu_ldl_mmuidx_ra(env
, sp
+ 4, MMU_KERNEL_IDX
, 0);
37 sp
|= (fmt
>> 28) & 3;
38 env
->aregs
[7] = sp
+ 8;
40 cpu_m68k_set_sr(env
, fmt
);
43 static void m68k_rte(CPUM68KState
*env
)
51 sr
= cpu_lduw_mmuidx_ra(env
, sp
, MMU_KERNEL_IDX
, 0);
53 env
->pc
= cpu_ldl_mmuidx_ra(env
, sp
, MMU_KERNEL_IDX
, 0);
55 if (m68k_feature(env
, M68K_FEATURE_EXCEPTION_FORMAT_VEC
)) {
56 /* all except 68000 */
57 fmt
= cpu_lduw_mmuidx_ra(env
, sp
, MMU_KERNEL_IDX
, 0);
64 cpu_m68k_set_sr(env
, sr
);
79 cpu_m68k_set_sr(env
, sr
);
82 static const char *m68k_exception_name(int index
)
86 return "Access Fault";
88 return "Address Error";
90 return "Illegal Instruction";
92 return "Divide by Zero";
96 return "FTRAPcc, TRAPcc, TRAPV";
98 return "Privilege Violation";
105 case EXCP_DEBEGBP
: /* 68020/030 only */
106 return "Copro Protocol Violation";
108 return "Format Error";
109 case EXCP_UNINITIALIZED
:
110 return "Uninitialized Interrupt";
112 return "Spurious Interrupt";
113 case EXCP_INT_LEVEL_1
:
114 return "Level 1 Interrupt";
115 case EXCP_INT_LEVEL_1
+ 1:
116 return "Level 2 Interrupt";
117 case EXCP_INT_LEVEL_1
+ 2:
118 return "Level 3 Interrupt";
119 case EXCP_INT_LEVEL_1
+ 3:
120 return "Level 4 Interrupt";
121 case EXCP_INT_LEVEL_1
+ 4:
122 return "Level 5 Interrupt";
123 case EXCP_INT_LEVEL_1
+ 5:
124 return "Level 6 Interrupt";
125 case EXCP_INT_LEVEL_1
+ 6:
126 return "Level 7 Interrupt";
147 case EXCP_TRAP0
+ 10:
149 case EXCP_TRAP0
+ 11:
151 case EXCP_TRAP0
+ 12:
153 case EXCP_TRAP0
+ 13:
155 case EXCP_TRAP0
+ 14:
157 case EXCP_TRAP0
+ 15:
160 return "FP Branch/Set on unordered condition";
162 return "FP Inexact Result";
164 return "FP Divide by Zero";
166 return "FP Underflow";
168 return "FP Operand Error";
170 return "FP Overflow";
172 return "FP Signaling NAN";
174 return "FP Unimplemented Data Type";
175 case EXCP_MMU_CONF
: /* 68030/68851 only */
176 return "MMU Configuration Error";
177 case EXCP_MMU_ILLEGAL
: /* 68851 only */
178 return "MMU Illegal Operation";
179 case EXCP_MMU_ACCESS
: /* 68851 only */
180 return "MMU Access Level Violation";
182 return "User Defined Vector";
187 static void cf_interrupt_all(CPUM68KState
*env
, int is_hw
)
189 CPUState
*cs
= env_cpu(env
);
200 switch (cs
->exception_index
) {
202 /* Return from an exception. */
206 if (semihosting_enabled((env
->sr
& SR_S
) == 0)
207 && (env
->pc
& 3) == 0
208 && cpu_lduw_code(env
, env
->pc
- 4) == 0x4e71
209 && cpu_ldl_code(env
, env
->pc
) == 0x4e7bf000) {
211 do_m68k_semihosting(env
, env
->dregs
[0]);
215 cs
->exception_index
= EXCP_HLT
;
221 vector
= cs
->exception_index
<< 2;
223 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
224 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
226 qemu_log("INT %6d: %s(%#x) pc=%08x sp=%08x sr=%04x\n",
227 ++count
, m68k_exception_name(cs
->exception_index
),
228 vector
, env
->pc
, env
->aregs
[7], sr
);
237 env
->sr
= (env
->sr
& ~SR_I
) | (env
->pending_level
<< SR_I_SHIFT
);
242 fmt
|= (sp
& 3) << 28;
244 /* ??? This could cause MMU faults. */
247 cpu_stl_mmuidx_ra(env
, sp
, retaddr
, MMU_KERNEL_IDX
, 0);
249 cpu_stl_mmuidx_ra(env
, sp
, fmt
, MMU_KERNEL_IDX
, 0);
251 /* Jump to vector. */
252 env
->pc
= cpu_ldl_mmuidx_ra(env
, env
->vbr
+ vector
, MMU_KERNEL_IDX
, 0);
255 static inline void do_stack_frame(CPUM68KState
*env
, uint32_t *sp
,
256 uint16_t format
, uint16_t sr
,
257 uint32_t addr
, uint32_t retaddr
)
259 if (m68k_feature(env
, M68K_FEATURE_EXCEPTION_FORMAT_VEC
)) {
260 /* all except 68000 */
261 CPUState
*cs
= env_cpu(env
);
265 cpu_stl_mmuidx_ra(env
, *sp
, env
->pc
, MMU_KERNEL_IDX
, 0);
267 cpu_stl_mmuidx_ra(env
, *sp
, addr
, MMU_KERNEL_IDX
, 0);
272 cpu_stl_mmuidx_ra(env
, *sp
, addr
, MMU_KERNEL_IDX
, 0);
276 cpu_stw_mmuidx_ra(env
, *sp
, (format
<< 12) + (cs
->exception_index
<< 2),
280 cpu_stl_mmuidx_ra(env
, *sp
, retaddr
, MMU_KERNEL_IDX
, 0);
282 cpu_stw_mmuidx_ra(env
, *sp
, sr
, MMU_KERNEL_IDX
, 0);
285 static void m68k_interrupt_all(CPUM68KState
*env
, int is_hw
)
287 CPUState
*cs
= env_cpu(env
);
293 switch (cs
->exception_index
) {
295 /* Return from an exception. */
301 vector
= cs
->exception_index
<< 2;
303 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
304 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
306 qemu_log("INT %6d: %s(%#x) pc=%08x sp=%08x sr=%04x\n",
307 ++count
, m68k_exception_name(cs
->exception_index
),
308 vector
, env
->pc
, env
->aregs
[7], sr
);
312 * MC68040UM/AD, chapter 9.3.10
315 /* "the processor first make an internal copy" */
317 /* "set the mode to supervisor" */
319 /* "suppress tracing" */
321 /* "sets the processor interrupt mask" */
323 sr
|= (env
->sr
& ~SR_I
) | (env
->pending_level
<< SR_I_SHIFT
);
325 cpu_m68k_set_sr(env
, sr
);
328 if (!m68k_feature(env
, M68K_FEATURE_UNALIGNED_DATA
)) {
332 switch (cs
->exception_index
) {
334 if (env
->mmu
.fault
) {
335 cpu_abort(cs
, "DOUBLE MMU FAULT\n");
337 env
->mmu
.fault
= true;
340 cpu_stl_mmuidx_ra(env
, sp
, 0, MMU_KERNEL_IDX
, 0);
343 cpu_stl_mmuidx_ra(env
, sp
, 0, MMU_KERNEL_IDX
, 0);
346 cpu_stl_mmuidx_ra(env
, sp
, 0, MMU_KERNEL_IDX
, 0);
347 /* write back 1 / push data 0 */
349 cpu_stl_mmuidx_ra(env
, sp
, 0, MMU_KERNEL_IDX
, 0);
350 /* write back 1 address */
352 cpu_stl_mmuidx_ra(env
, sp
, 0, MMU_KERNEL_IDX
, 0);
353 /* write back 2 data */
355 cpu_stl_mmuidx_ra(env
, sp
, 0, MMU_KERNEL_IDX
, 0);
356 /* write back 2 address */
358 cpu_stl_mmuidx_ra(env
, sp
, 0, MMU_KERNEL_IDX
, 0);
359 /* write back 3 data */
361 cpu_stl_mmuidx_ra(env
, sp
, 0, MMU_KERNEL_IDX
, 0);
362 /* write back 3 address */
364 cpu_stl_mmuidx_ra(env
, sp
, env
->mmu
.ar
, MMU_KERNEL_IDX
, 0);
367 cpu_stl_mmuidx_ra(env
, sp
, env
->mmu
.ar
, MMU_KERNEL_IDX
, 0);
368 /* write back 1 status */
370 cpu_stw_mmuidx_ra(env
, sp
, 0, MMU_KERNEL_IDX
, 0);
371 /* write back 2 status */
373 cpu_stw_mmuidx_ra(env
, sp
, 0, MMU_KERNEL_IDX
, 0);
374 /* write back 3 status */
376 cpu_stw_mmuidx_ra(env
, sp
, 0, MMU_KERNEL_IDX
, 0);
377 /* special status word */
379 cpu_stw_mmuidx_ra(env
, sp
, env
->mmu
.ssw
, MMU_KERNEL_IDX
, 0);
380 /* effective address */
382 cpu_stl_mmuidx_ra(env
, sp
, env
->mmu
.ar
, MMU_KERNEL_IDX
, 0);
384 do_stack_frame(env
, &sp
, 7, oldsr
, 0, env
->pc
);
385 env
->mmu
.fault
= false;
386 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
388 "ssw: %08x ea: %08x sfc: %d dfc: %d\n",
389 env
->mmu
.ssw
, env
->mmu
.ar
, env
->sfc
, env
->dfc
);
394 do_stack_frame(env
, &sp
, 0, oldsr
, 0, env
->pc
);
398 do_stack_frame(env
, &sp
, 2, oldsr
, 0, env
->pc
);
405 do_stack_frame(env
, &sp
, 2, oldsr
, env
->mmu
.ar
, env
->pc
);
408 case EXCP_SPURIOUS
... EXCP_INT_LEVEL_7
:
409 if (is_hw
&& (oldsr
& SR_M
)) {
410 do_stack_frame(env
, &sp
, 0, oldsr
, 0, env
->pc
);
413 cpu_m68k_set_sr(env
, sr
& ~SR_M
);
415 if (!m68k_feature(env
, M68K_FEATURE_UNALIGNED_DATA
)) {
418 do_stack_frame(env
, &sp
, 1, oldsr
, 0, env
->pc
);
424 do_stack_frame(env
, &sp
, 0, oldsr
, 0, env
->pc
);
429 /* Jump to vector. */
430 env
->pc
= cpu_ldl_mmuidx_ra(env
, env
->vbr
+ vector
, MMU_KERNEL_IDX
, 0);
433 static void do_interrupt_all(CPUM68KState
*env
, int is_hw
)
435 if (m68k_feature(env
, M68K_FEATURE_M68K
)) {
436 m68k_interrupt_all(env
, is_hw
);
439 cf_interrupt_all(env
, is_hw
);
442 void m68k_cpu_do_interrupt(CPUState
*cs
)
444 do_interrupt_all(cpu_env(cs
), 0);
447 static inline void do_interrupt_m68k_hardirq(CPUM68KState
*env
)
449 do_interrupt_all(env
, 1);
452 void m68k_cpu_transaction_failed(CPUState
*cs
, hwaddr physaddr
, vaddr addr
,
453 unsigned size
, MMUAccessType access_type
,
454 int mmu_idx
, MemTxAttrs attrs
,
455 MemTxResult response
, uintptr_t retaddr
)
457 CPUM68KState
*env
= cpu_env(cs
);
459 cpu_restore_state(cs
, retaddr
);
461 if (m68k_feature(env
, M68K_FEATURE_M68040
)) {
465 * According to the MC68040 users manual the ATC bit of the SSW is
466 * used to distinguish between ATC faults and physical bus errors.
467 * In the case of a bus error e.g. during nubus read from an empty
468 * slot this bit should not be set
470 if (response
!= MEMTX_DECODE_ERROR
) {
471 env
->mmu
.ssw
|= M68K_ATC_040
;
474 /* FIXME: manage MMU table access error */
475 env
->mmu
.ssw
&= ~M68K_TM_040
;
476 if (env
->sr
& SR_S
) { /* SUPERVISOR */
477 env
->mmu
.ssw
|= M68K_TM_040_SUPER
;
479 if (access_type
== MMU_INST_FETCH
) { /* instruction or data */
480 env
->mmu
.ssw
|= M68K_TM_040_CODE
;
482 env
->mmu
.ssw
|= M68K_TM_040_DATA
;
484 env
->mmu
.ssw
&= ~M68K_BA_SIZE_MASK
;
487 env
->mmu
.ssw
|= M68K_BA_SIZE_BYTE
;
490 env
->mmu
.ssw
|= M68K_BA_SIZE_WORD
;
493 env
->mmu
.ssw
|= M68K_BA_SIZE_LONG
;
497 if (access_type
!= MMU_DATA_STORE
) {
498 env
->mmu
.ssw
|= M68K_RW_040
;
503 cs
->exception_index
= EXCP_ACCESS
;
508 bool m68k_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
510 CPUM68KState
*env
= cpu_env(cs
);
512 if (interrupt_request
& CPU_INTERRUPT_HARD
513 && ((env
->sr
& SR_I
) >> SR_I_SHIFT
) < env
->pending_level
) {
515 * Real hardware gets the interrupt vector via an IACK cycle
516 * at this point. Current emulated hardware doesn't rely on
517 * this, so we provide/save the vector when the interrupt is
520 cs
->exception_index
= env
->pending_vector
;
521 do_interrupt_m68k_hardirq(env
);
527 #endif /* !CONFIG_USER_ONLY */
529 G_NORETURN
static void
530 raise_exception_ra(CPUM68KState
*env
, int tt
, uintptr_t raddr
)
532 CPUState
*cs
= env_cpu(env
);
534 cs
->exception_index
= tt
;
535 cpu_loop_exit_restore(cs
, raddr
);
538 G_NORETURN
static void raise_exception(CPUM68KState
*env
, int tt
)
540 raise_exception_ra(env
, tt
, 0);
543 void G_NORETURN
HELPER(raise_exception
)(CPUM68KState
*env
, uint32_t tt
)
545 raise_exception(env
, tt
);
548 G_NORETURN
static void
549 raise_exception_format2(CPUM68KState
*env
, int tt
, int ilen
, uintptr_t raddr
)
551 CPUState
*cs
= env_cpu(env
);
553 cs
->exception_index
= tt
;
555 /* Recover PC and CC_OP for the beginning of the insn. */
556 cpu_restore_state(cs
, raddr
);
558 /* Flags are current in env->cc_*, or are undefined. */
559 env
->cc_op
= CC_OP_FLAGS
;
562 * Remember original pc in mmu.ar, for the Format 2 stack frame.
563 * Adjust PC to end of the insn.
565 env
->mmu
.ar
= env
->pc
;
571 void HELPER(divuw
)(CPUM68KState
*env
, int destr
, uint32_t den
, int ilen
)
573 uint32_t num
= env
->dregs
[destr
];
576 env
->cc_c
= 0; /* always cleared, even if div0 */
579 raise_exception_format2(env
, EXCP_DIV0
, ilen
, GETPC());
587 * real 68040 keeps N and unset Z on overflow,
588 * whereas documentation says "undefined"
593 env
->dregs
[destr
] = deposit32(quot
, 16, 16, rem
);
594 env
->cc_z
= (int16_t)quot
;
595 env
->cc_n
= (int16_t)quot
;
599 void HELPER(divsw
)(CPUM68KState
*env
, int destr
, int32_t den
, int ilen
)
601 int32_t num
= env
->dregs
[destr
];
604 env
->cc_c
= 0; /* always cleared, even if overflow/div0 */
607 raise_exception_format2(env
, EXCP_DIV0
, ilen
, GETPC());
612 if (quot
!= (int16_t)quot
) {
614 /* nothing else is modified */
616 * real 68040 keeps N and unset Z on overflow,
617 * whereas documentation says "undefined"
622 env
->dregs
[destr
] = deposit32(quot
, 16, 16, rem
);
623 env
->cc_z
= (int16_t)quot
;
624 env
->cc_n
= (int16_t)quot
;
628 void HELPER(divul
)(CPUM68KState
*env
, int numr
, int regr
,
629 uint32_t den
, int ilen
)
631 uint32_t num
= env
->dregs
[numr
];
634 env
->cc_c
= 0; /* always cleared, even if div0 */
637 raise_exception_format2(env
, EXCP_DIV0
, ilen
, GETPC());
646 if (m68k_feature(env
, M68K_FEATURE_CF_ISA_A
)) {
648 env
->dregs
[numr
] = quot
;
650 env
->dregs
[regr
] = rem
;
653 env
->dregs
[regr
] = rem
;
654 env
->dregs
[numr
] = quot
;
658 void HELPER(divsl
)(CPUM68KState
*env
, int numr
, int regr
,
659 int32_t den
, int ilen
)
661 int32_t num
= env
->dregs
[numr
];
664 env
->cc_c
= 0; /* always cleared, even if overflow/div0 */
667 raise_exception_format2(env
, EXCP_DIV0
, ilen
, GETPC());
676 if (m68k_feature(env
, M68K_FEATURE_CF_ISA_A
)) {
678 env
->dregs
[numr
] = quot
;
680 env
->dregs
[regr
] = rem
;
683 env
->dregs
[regr
] = rem
;
684 env
->dregs
[numr
] = quot
;
688 void HELPER(divull
)(CPUM68KState
*env
, int numr
, int regr
,
689 uint32_t den
, int ilen
)
691 uint64_t num
= deposit64(env
->dregs
[numr
], 32, 32, env
->dregs
[regr
]);
695 env
->cc_c
= 0; /* always cleared, even if overflow/div0 */
698 raise_exception_format2(env
, EXCP_DIV0
, ilen
, GETPC());
703 if (quot
> 0xffffffffULL
) {
706 * real 68040 keeps N and unset Z on overflow,
707 * whereas documentation says "undefined"
717 * If Dq and Dr are the same, the quotient is returned.
718 * therefore we set Dq last.
721 env
->dregs
[regr
] = rem
;
722 env
->dregs
[numr
] = quot
;
725 void HELPER(divsll
)(CPUM68KState
*env
, int numr
, int regr
,
726 int32_t den
, int ilen
)
728 int64_t num
= deposit64(env
->dregs
[numr
], 32, 32, env
->dregs
[regr
]);
732 env
->cc_c
= 0; /* always cleared, even if overflow/div0 */
735 raise_exception_format2(env
, EXCP_DIV0
, ilen
, GETPC());
740 if (quot
!= (int32_t)quot
) {
743 * real 68040 keeps N and unset Z on overflow,
744 * whereas documentation says "undefined"
754 * If Dq and Dr are the same, the quotient is returned.
755 * therefore we set Dq last.
758 env
->dregs
[regr
] = rem
;
759 env
->dregs
[numr
] = quot
;
762 /* We're executing in a serial context -- no need to be atomic. */
763 void HELPER(cas2w
)(CPUM68KState
*env
, uint32_t regs
, uint32_t a1
, uint32_t a2
)
765 uint32_t Dc1
= extract32(regs
, 9, 3);
766 uint32_t Dc2
= extract32(regs
, 6, 3);
767 uint32_t Du1
= extract32(regs
, 3, 3);
768 uint32_t Du2
= extract32(regs
, 0, 3);
769 int16_t c1
= env
->dregs
[Dc1
];
770 int16_t c2
= env
->dregs
[Dc2
];
771 int16_t u1
= env
->dregs
[Du1
];
772 int16_t u2
= env
->dregs
[Du2
];
774 uintptr_t ra
= GETPC();
776 l1
= cpu_lduw_data_ra(env
, a1
, ra
);
777 l2
= cpu_lduw_data_ra(env
, a2
, ra
);
778 if (l1
== c1
&& l2
== c2
) {
779 cpu_stw_data_ra(env
, a1
, u1
, ra
);
780 cpu_stw_data_ra(env
, a2
, u2
, ra
);
790 env
->cc_op
= CC_OP_CMPW
;
791 env
->dregs
[Dc1
] = deposit32(env
->dregs
[Dc1
], 0, 16, l1
);
792 env
->dregs
[Dc2
] = deposit32(env
->dregs
[Dc2
], 0, 16, l2
);
795 static void do_cas2l(CPUM68KState
*env
, uint32_t regs
, uint32_t a1
, uint32_t a2
,
798 uint32_t Dc1
= extract32(regs
, 9, 3);
799 uint32_t Dc2
= extract32(regs
, 6, 3);
800 uint32_t Du1
= extract32(regs
, 3, 3);
801 uint32_t Du2
= extract32(regs
, 0, 3);
802 uint32_t c1
= env
->dregs
[Dc1
];
803 uint32_t c2
= env
->dregs
[Dc2
];
804 uint32_t u1
= env
->dregs
[Du1
];
805 uint32_t u2
= env
->dregs
[Du2
];
807 uintptr_t ra
= GETPC();
808 #if defined(CONFIG_ATOMIC64)
809 int mmu_idx
= cpu_mmu_index(env_cpu(env
), 0);
810 MemOpIdx oi
= make_memop_idx(MO_BEUQ
, mmu_idx
);
814 /* We're executing in a parallel context -- must be atomic. */
815 #ifdef CONFIG_ATOMIC64
817 if ((a1
& 7) == 0 && a2
== a1
+ 4) {
818 c
= deposit64(c2
, 32, 32, c1
);
819 u
= deposit64(u2
, 32, 32, u1
);
820 l
= cpu_atomic_cmpxchgq_be_mmu(env
, a1
, c
, u
, oi
, ra
);
823 } else if ((a2
& 7) == 0 && a1
== a2
+ 4) {
824 c
= deposit64(c1
, 32, 32, c2
);
825 u
= deposit64(u1
, 32, 32, u2
);
826 l
= cpu_atomic_cmpxchgq_be_mmu(env
, a2
, c
, u
, oi
, ra
);
832 /* Tell the main loop we need to serialize this insn. */
833 cpu_loop_exit_atomic(env_cpu(env
), ra
);
836 /* We're executing in a serial context -- no need to be atomic. */
837 l1
= cpu_ldl_data_ra(env
, a1
, ra
);
838 l2
= cpu_ldl_data_ra(env
, a2
, ra
);
839 if (l1
== c1
&& l2
== c2
) {
840 cpu_stl_data_ra(env
, a1
, u1
, ra
);
841 cpu_stl_data_ra(env
, a2
, u2
, ra
);
852 env
->cc_op
= CC_OP_CMPL
;
853 env
->dregs
[Dc1
] = l1
;
854 env
->dregs
[Dc2
] = l2
;
857 void HELPER(cas2l
)(CPUM68KState
*env
, uint32_t regs
, uint32_t a1
, uint32_t a2
)
859 do_cas2l(env
, regs
, a1
, a2
, false);
862 void HELPER(cas2l_parallel
)(CPUM68KState
*env
, uint32_t regs
, uint32_t a1
,
865 do_cas2l(env
, regs
, a1
, a2
, true);
875 static struct bf_data
bf_prep(uint32_t addr
, int32_t ofs
, uint32_t len
)
879 /* Bound length; map 0 to 32. */
880 len
= ((len
- 1) & 31) + 1;
882 /* Note that ofs is signed. */
891 * Compute the number of bytes required (minus one) to
892 * satisfy the bitfield.
894 blen
= (bofs
+ len
- 1) / 8;
897 * Canonicalize the bit offset for data loaded into a 64-bit big-endian
898 * word. For the cases where BLEN is not a power of 2, adjust ADDR so
899 * that we can use the next power of two sized load without crossing a
900 * page boundary, unless the field itself crosses the boundary.
920 bofs
+= 8 * (addr
& 3);
925 g_assert_not_reached();
928 return (struct bf_data
){
936 static uint64_t bf_load(CPUM68KState
*env
, uint32_t addr
, int blen
,
941 return cpu_ldub_data_ra(env
, addr
, ra
);
943 return cpu_lduw_data_ra(env
, addr
, ra
);
946 return cpu_ldl_data_ra(env
, addr
, ra
);
948 return cpu_ldq_data_ra(env
, addr
, ra
);
950 g_assert_not_reached();
954 static void bf_store(CPUM68KState
*env
, uint32_t addr
, int blen
,
955 uint64_t data
, uintptr_t ra
)
959 cpu_stb_data_ra(env
, addr
, data
, ra
);
962 cpu_stw_data_ra(env
, addr
, data
, ra
);
966 cpu_stl_data_ra(env
, addr
, data
, ra
);
969 cpu_stq_data_ra(env
, addr
, data
, ra
);
972 g_assert_not_reached();
976 uint32_t HELPER(bfexts_mem
)(CPUM68KState
*env
, uint32_t addr
,
977 int32_t ofs
, uint32_t len
)
979 uintptr_t ra
= GETPC();
980 struct bf_data d
= bf_prep(addr
, ofs
, len
);
981 uint64_t data
= bf_load(env
, d
.addr
, d
.blen
, ra
);
983 return (int64_t)(data
<< d
.bofs
) >> (64 - d
.len
);
986 uint64_t HELPER(bfextu_mem
)(CPUM68KState
*env
, uint32_t addr
,
987 int32_t ofs
, uint32_t len
)
989 uintptr_t ra
= GETPC();
990 struct bf_data d
= bf_prep(addr
, ofs
, len
);
991 uint64_t data
= bf_load(env
, d
.addr
, d
.blen
, ra
);
994 * Put CC_N at the top of the high word; put the zero-extended value
995 * at the bottom of the low word.
999 data
|= data
<< (64 - d
.len
);
1004 uint32_t HELPER(bfins_mem
)(CPUM68KState
*env
, uint32_t addr
, uint32_t val
,
1005 int32_t ofs
, uint32_t len
)
1007 uintptr_t ra
= GETPC();
1008 struct bf_data d
= bf_prep(addr
, ofs
, len
);
1009 uint64_t data
= bf_load(env
, d
.addr
, d
.blen
, ra
);
1010 uint64_t mask
= -1ull << (64 - d
.len
) >> d
.bofs
;
1012 data
= (data
& ~mask
) | (((uint64_t)val
<< (64 - d
.len
)) >> d
.bofs
);
1014 bf_store(env
, d
.addr
, d
.blen
, data
, ra
);
1016 /* The field at the top of the word is also CC_N for CC_OP_LOGIC. */
1017 return val
<< (32 - d
.len
);
1020 uint32_t HELPER(bfchg_mem
)(CPUM68KState
*env
, uint32_t addr
,
1021 int32_t ofs
, uint32_t len
)
1023 uintptr_t ra
= GETPC();
1024 struct bf_data d
= bf_prep(addr
, ofs
, len
);
1025 uint64_t data
= bf_load(env
, d
.addr
, d
.blen
, ra
);
1026 uint64_t mask
= -1ull << (64 - d
.len
) >> d
.bofs
;
1028 bf_store(env
, d
.addr
, d
.blen
, data
^ mask
, ra
);
1030 return ((data
& mask
) << d
.bofs
) >> 32;
1033 uint32_t HELPER(bfclr_mem
)(CPUM68KState
*env
, uint32_t addr
,
1034 int32_t ofs
, uint32_t len
)
1036 uintptr_t ra
= GETPC();
1037 struct bf_data d
= bf_prep(addr
, ofs
, len
);
1038 uint64_t data
= bf_load(env
, d
.addr
, d
.blen
, ra
);
1039 uint64_t mask
= -1ull << (64 - d
.len
) >> d
.bofs
;
1041 bf_store(env
, d
.addr
, d
.blen
, data
& ~mask
, ra
);
1043 return ((data
& mask
) << d
.bofs
) >> 32;
1046 uint32_t HELPER(bfset_mem
)(CPUM68KState
*env
, uint32_t addr
,
1047 int32_t ofs
, uint32_t len
)
1049 uintptr_t ra
= GETPC();
1050 struct bf_data d
= bf_prep(addr
, ofs
, len
);
1051 uint64_t data
= bf_load(env
, d
.addr
, d
.blen
, ra
);
1052 uint64_t mask
= -1ull << (64 - d
.len
) >> d
.bofs
;
1054 bf_store(env
, d
.addr
, d
.blen
, data
| mask
, ra
);
1056 return ((data
& mask
) << d
.bofs
) >> 32;
1059 uint32_t HELPER(bfffo_reg
)(uint32_t n
, uint32_t ofs
, uint32_t len
)
1061 return (n
? clz32(n
) : len
) + ofs
;
1064 uint64_t HELPER(bfffo_mem
)(CPUM68KState
*env
, uint32_t addr
,
1065 int32_t ofs
, uint32_t len
)
1067 uintptr_t ra
= GETPC();
1068 struct bf_data d
= bf_prep(addr
, ofs
, len
);
1069 uint64_t data
= bf_load(env
, d
.addr
, d
.blen
, ra
);
1070 uint64_t mask
= -1ull << (64 - d
.len
) >> d
.bofs
;
1071 uint64_t n
= (data
& mask
) << d
.bofs
;
1072 uint32_t ffo
= helper_bfffo_reg(n
>> 32, ofs
, d
.len
);
1075 * Return FFO in the low word and N in the high word.
1076 * Note that because of MASK and the shift, the low word
1082 void HELPER(chk
)(CPUM68KState
*env
, int32_t val
, int32_t ub
)
1086 * X: Not affected, C,V,Z: Undefined,
1087 * N: Set if val < 0; cleared if val > ub, undefined otherwise
1088 * We implement here values found from a real MC68040:
1089 * X,V,Z: Not affected
1090 * N: Set if val < 0; cleared if val >= 0
1091 * C: if 0 <= ub: set if val < 0 or val > ub, cleared otherwise
1092 * if 0 > ub: set if val > ub and val < 0, cleared otherwise
1095 env
->cc_c
= 0 <= ub
? val
< 0 || val
> ub
: val
> ub
&& val
< 0;
1097 if (val
< 0 || val
> ub
) {
1098 raise_exception_format2(env
, EXCP_CHK
, 2, GETPC());
1102 void HELPER(chk2
)(CPUM68KState
*env
, int32_t val
, int32_t lb
, int32_t ub
)
1106 * X: Not affected, N,V: Undefined,
1107 * Z: Set if val is equal to lb or ub
1108 * C: Set if val < lb or val > ub, cleared otherwise
1109 * We implement here values found from a real MC68040:
1110 * X,N,V: Not affected
1111 * Z: Set if val is equal to lb or ub
1112 * C: if lb <= ub: set if val < lb or val > ub, cleared otherwise
1113 * if lb > ub: set if val > ub and val < lb, cleared otherwise
1115 env
->cc_z
= val
!= lb
&& val
!= ub
;
1116 env
->cc_c
= lb
<= ub
? val
< lb
|| val
> ub
: val
> ub
&& val
< lb
;
1119 raise_exception_format2(env
, EXCP_CHK
, 4, GETPC());