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hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block
[qemu/ar7.git] / hw / arm / armsse.c
blob2366c49376dc6b1ab65f9e0c16c230dc098db451
1 /*
2 * Arm SSE (Subsystems for Embedded): IoTKit
3 *
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qemu/log.h"
14 #include "qemu/module.h"
15 #include "qemu/bitops.h"
16 #include "qapi/error.h"
17 #include "trace.h"
18 #include "hw/sysbus.h"
19 #include "migration/vmstate.h"
20 #include "hw/registerfields.h"
21 #include "hw/arm/armsse.h"
22 #include "hw/arm/armsse-version.h"
23 #include "hw/arm/boot.h"
24 #include "hw/irq.h"
25 #include "hw/qdev-clock.h"
26
27 /*
28 * The SSE-300 puts some devices in different places to the
29 * SSE-200 (and original IoTKit). We use an array of these structs
30 * to define how each variant lays out these devices. (Parts of the
31 * SoC that are the same for all variants aren't handled via these
32 * data structures.)
33 */
34
35 #define NO_IRQ -1
36 #define NO_PPC -1
37 /*
38 * Special values for ARMSSEDeviceInfo::irq to indicate that this
39 * device uses one of the inputs to the OR gate that feeds into the
40 * CPU NMI input.
41 */
42 #define NMI_0 10000
43 #define NMI_1 10001
44
45 typedef struct ARMSSEDeviceInfo {
46 const char *name; /* name to use for the QOM object; NULL terminates list */
47 const char *type; /* QOM type name */
48 unsigned int index; /* Which of the N devices of this type is this ? */
49 hwaddr addr;
50 hwaddr size; /* only needed for TYPE_UNIMPLEMENTED_DEVICE */
51 int ppc; /* Index of APB PPC this device is wired up to, or NO_PPC */
52 int ppc_port; /* Port number of this device on the PPC */
53 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */
54 bool slowclk; /* true if device uses the slow 32KHz clock */
55 } ARMSSEDeviceInfo;
56
57 struct ARMSSEInfo {
58 const char *name;
59 uint32_t sse_version;
60 int sram_banks;
61 int num_cpus;
62 uint32_t sys_version;
63 uint32_t iidr;
64 uint32_t cpuwait_rst;
65 bool has_mhus;
66 bool has_cachectrl;
67 bool has_cpusecctrl;
68 bool has_cpuid;
69 bool has_cpu_pwrctrl;
70 bool has_sse_counter;
71 Property *props;
72 const ARMSSEDeviceInfo *devinfo;
73 const bool *irq_is_common;
74 };
75
76 static Property iotkit_properties[] = {
77 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
78 MemoryRegion *),
79 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
80 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
81 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
82 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
83 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
84 DEFINE_PROP_END_OF_LIST()
85 };
86
87 static Property armsse_properties[] = {
88 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
89 MemoryRegion *),
90 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
91 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
92 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
93 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
94 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
95 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
96 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
97 DEFINE_PROP_END_OF_LIST()
98 };
99
100 static const ARMSSEDeviceInfo iotkit_devices[] = {
101 {
102 .name = "timer0",
103 .type = TYPE_CMSDK_APB_TIMER,
104 .index = 0,
105 .addr = 0x40000000,
106 .ppc = 0,
107 .ppc_port = 0,
108 .irq = 3,
109 },
110 {
111 .name = "timer1",
112 .type = TYPE_CMSDK_APB_TIMER,
113 .index = 1,
114 .addr = 0x40001000,
115 .ppc = 0,
116 .ppc_port = 1,
117 .irq = 4,
118 },
119 {
120 .name = "s32ktimer",
121 .type = TYPE_CMSDK_APB_TIMER,
122 .index = 2,
123 .addr = 0x4002f000,
124 .ppc = 1,
125 .ppc_port = 0,
126 .irq = 2,
127 .slowclk = true,
128 },
129 {
130 .name = "dualtimer",
131 .type = TYPE_CMSDK_APB_DUALTIMER,
132 .index = 0,
133 .addr = 0x40002000,
134 .ppc = 0,
135 .ppc_port = 2,
136 .irq = 5,
137 },
138 {
139 .name = "s32kwatchdog",
140 .type = TYPE_CMSDK_APB_WATCHDOG,
141 .index = 0,
142 .addr = 0x5002e000,
143 .ppc = NO_PPC,
144 .irq = NMI_0,
145 .slowclk = true,
146 },
147 {
148 .name = "nswatchdog",
149 .type = TYPE_CMSDK_APB_WATCHDOG,
150 .index = 1,
151 .addr = 0x40081000,
152 .ppc = NO_PPC,
153 .irq = 1,
154 },
155 {
156 .name = "swatchdog",
157 .type = TYPE_CMSDK_APB_WATCHDOG,
158 .index = 2,
159 .addr = 0x50081000,
160 .ppc = NO_PPC,
161 .irq = NMI_1,
162 },
163 {
164 .name = "armsse-sysinfo",
165 .type = TYPE_IOTKIT_SYSINFO,
166 .index = 0,
167 .addr = 0x40020000,
168 .ppc = NO_PPC,
169 .irq = NO_IRQ,
170 },
171 {
172 .name = "armsse-sysctl",
173 .type = TYPE_IOTKIT_SYSCTL,
174 .index = 0,
175 .addr = 0x50021000,
176 .ppc = NO_PPC,
177 .irq = NO_IRQ,
178 },
179 {
180 .name = NULL,
181 }
182 };
183
184 static const ARMSSEDeviceInfo sse200_devices[] = {
185 {
186 .name = "timer0",
187 .type = TYPE_CMSDK_APB_TIMER,
188 .index = 0,
189 .addr = 0x40000000,
190 .ppc = 0,
191 .ppc_port = 0,
192 .irq = 3,
193 },
194 {
195 .name = "timer1",
196 .type = TYPE_CMSDK_APB_TIMER,
197 .index = 1,
198 .addr = 0x40001000,
199 .ppc = 0,
200 .ppc_port = 1,
201 .irq = 4,
202 },
203 {
204 .name = "s32ktimer",
205 .type = TYPE_CMSDK_APB_TIMER,
206 .index = 2,
207 .addr = 0x4002f000,
208 .ppc = 1,
209 .ppc_port = 0,
210 .irq = 2,
211 .slowclk = true,
212 },
213 {
214 .name = "dualtimer",
215 .type = TYPE_CMSDK_APB_DUALTIMER,
216 .index = 0,
217 .addr = 0x40002000,
218 .ppc = 0,
219 .ppc_port = 2,
220 .irq = 5,
221 },
222 {
223 .name = "s32kwatchdog",
224 .type = TYPE_CMSDK_APB_WATCHDOG,
225 .index = 0,
226 .addr = 0x5002e000,
227 .ppc = NO_PPC,
228 .irq = NMI_0,
229 .slowclk = true,
230 },
231 {
232 .name = "nswatchdog",
233 .type = TYPE_CMSDK_APB_WATCHDOG,
234 .index = 1,
235 .addr = 0x40081000,
236 .ppc = NO_PPC,
237 .irq = 1,
238 },
239 {
240 .name = "swatchdog",
241 .type = TYPE_CMSDK_APB_WATCHDOG,
242 .index = 2,
243 .addr = 0x50081000,
244 .ppc = NO_PPC,
245 .irq = NMI_1,
246 },
247 {
248 .name = "armsse-sysinfo",
249 .type = TYPE_IOTKIT_SYSINFO,
250 .index = 0,
251 .addr = 0x40020000,
252 .ppc = NO_PPC,
253 .irq = NO_IRQ,
254 },
255 {
256 .name = "armsse-sysctl",
257 .type = TYPE_IOTKIT_SYSCTL,
258 .index = 0,
259 .addr = 0x50021000,
260 .ppc = NO_PPC,
261 .irq = NO_IRQ,
262 },
263 {
264 .name = "CPU0CORE_PPU",
265 .type = TYPE_UNIMPLEMENTED_DEVICE,
266 .index = 0,
267 .addr = 0x50023000,
268 .size = 0x1000,
269 .ppc = NO_PPC,
270 .irq = NO_IRQ,
271 },
272 {
273 .name = "CPU1CORE_PPU",
274 .type = TYPE_UNIMPLEMENTED_DEVICE,
275 .index = 1,
276 .addr = 0x50025000,
277 .size = 0x1000,
278 .ppc = NO_PPC,
279 .irq = NO_IRQ,
280 },
281 {
282 .name = "DBG_PPU",
283 .type = TYPE_UNIMPLEMENTED_DEVICE,
284 .index = 2,
285 .addr = 0x50029000,
286 .size = 0x1000,
287 .ppc = NO_PPC,
288 .irq = NO_IRQ,
289 },
290 {
291 .name = "RAM0_PPU",
292 .type = TYPE_UNIMPLEMENTED_DEVICE,
293 .index = 3,
294 .addr = 0x5002a000,
295 .size = 0x1000,
296 .ppc = NO_PPC,
297 .irq = NO_IRQ,
298 },
299 {
300 .name = "RAM1_PPU",
301 .type = TYPE_UNIMPLEMENTED_DEVICE,
302 .index = 4,
303 .addr = 0x5002b000,
304 .size = 0x1000,
305 .ppc = NO_PPC,
306 .irq = NO_IRQ,
307 },
308 {
309 .name = "RAM2_PPU",
310 .type = TYPE_UNIMPLEMENTED_DEVICE,
311 .index = 5,
312 .addr = 0x5002c000,
313 .size = 0x1000,
314 .ppc = NO_PPC,
315 .irq = NO_IRQ,
316 },
317 {
318 .name = "RAM3_PPU",
319 .type = TYPE_UNIMPLEMENTED_DEVICE,
320 .index = 6,
321 .addr = 0x5002d000,
322 .size = 0x1000,
323 .ppc = NO_PPC,
324 .irq = NO_IRQ,
325 },
326 {
327 .name = "SYS_PPU",
328 .type = TYPE_UNIMPLEMENTED_DEVICE,
329 .index = 7,
330 .addr = 0x50022000,
331 .size = 0x1000,
332 .ppc = NO_PPC,
333 .irq = NO_IRQ,
334 },
335 {
336 .name = NULL,
337 }
338 };
339
340 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */
341 static const bool sse200_irq_is_common[32] = {
342 [0 ... 5] = true,
343 /* 6, 7: per-CPU MHU interrupts */
344 [8 ... 12] = true,
345 /* 13: per-CPU icache interrupt */
346 /* 14: reserved */
347 [15 ... 20] = true,
348 /* 21: reserved */
349 [22 ... 26] = true,
350 /* 27: reserved */
351 /* 28, 29: per-CPU CTI interrupts */
352 /* 30, 31: reserved */
353 };
354
355 static const ARMSSEInfo armsse_variants[] = {
356 {
357 .name = TYPE_IOTKIT,
358 .sse_version = ARMSSE_IOTKIT,
359 .sram_banks = 1,
360 .num_cpus = 1,
361 .sys_version = 0x41743,
362 .iidr = 0,
363 .cpuwait_rst = 0,
364 .has_mhus = false,
365 .has_cachectrl = false,
366 .has_cpusecctrl = false,
367 .has_cpuid = false,
368 .has_cpu_pwrctrl = false,
369 .has_sse_counter = false,
370 .props = iotkit_properties,
371 .devinfo = iotkit_devices,
372 .irq_is_common = sse200_irq_is_common,
373 },
374 {
375 .name = TYPE_SSE200,
376 .sse_version = ARMSSE_SSE200,
377 .sram_banks = 4,
378 .num_cpus = 2,
379 .sys_version = 0x22041743,
380 .iidr = 0,
381 .cpuwait_rst = 2,
382 .has_mhus = true,
383 .has_cachectrl = true,
384 .has_cpusecctrl = true,
385 .has_cpuid = true,
386 .has_cpu_pwrctrl = false,
387 .has_sse_counter = false,
388 .props = armsse_properties,
389 .devinfo = sse200_devices,
390 .irq_is_common = sse200_irq_is_common,
391 },
392 };
393
394 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info)
395 {
396 /* Return the SYS_CONFIG value for this SSE */
397 uint32_t sys_config;
398
399 switch (info->sse_version) {
400 case ARMSSE_IOTKIT:
401 sys_config = 0;
402 sys_config = deposit32(sys_config, 0, 4, info->sram_banks);
403 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12);
404 break;
405 case ARMSSE_SSE200:
406 sys_config = 0;
407 sys_config = deposit32(sys_config, 0, 4, info->sram_banks);
408 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width);
409 sys_config = deposit32(sys_config, 24, 4, 2);
410 if (info->num_cpus > 1) {
411 sys_config = deposit32(sys_config, 10, 1, 1);
412 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1);
413 sys_config = deposit32(sys_config, 28, 4, 2);
414 }
415 break;
416 case ARMSSE_SSE300:
417 sys_config = 0;
418 sys_config = deposit32(sys_config, 0, 4, info->sram_banks);
419 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width);
420 sys_config = deposit32(sys_config, 16, 3, 3); /* CPU0 = Cortex-M55 */
421 break;
422 default:
423 g_assert_not_reached();
424 }
425 return sys_config;
426 }
427
428 /* Clock frequency in HZ of the 32KHz "slow clock" */
429 #define S32KCLK (32 * 1000)
430
431 /*
432 * Create an alias region in @container of @size bytes starting at @base
433 * which mirrors the memory starting at @orig.
434 */
435 static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *container,
436 const char *name, hwaddr base, hwaddr size, hwaddr orig)
437 {
438 memory_region_init_alias(mr, NULL, name, container, orig, size);
439 /* The alias is even lower priority than unimplemented_device regions */
440 memory_region_add_subregion_overlap(container, base, mr, -1500);
441 }
442
443 static void irq_status_forwarder(void *opaque, int n, int level)
444 {
445 qemu_irq destirq = opaque;
446
447 qemu_set_irq(destirq, level);
448 }
449
450 static void nsccfg_handler(void *opaque, int n, int level)
451 {
452 ARMSSE *s = ARM_SSE(opaque);
453
454 s->nsccfg = level;
455 }
456
457 static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum)
458 {
459 /* Each of the 4 AHB and 4 APB PPCs that might be present in a
460 * system using the ARMSSE has a collection of control lines which
461 * are provided by the security controller and which we want to
462 * expose as control lines on the ARMSSE device itself, so the
463 * code using the ARMSSE can wire them up to the PPCs.
464 */
465 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum];
466 DeviceState *armssedev = DEVICE(s);
467 DeviceState *dev_secctl = DEVICE(&s->secctl);
468 DeviceState *dev_splitter = DEVICE(splitter);
469 char *name;
470
471 name = g_strdup_printf("%s_nonsec", ppcname);
472 qdev_pass_gpios(dev_secctl, armssedev, name);
473 g_free(name);
474 name = g_strdup_printf("%s_ap", ppcname);
475 qdev_pass_gpios(dev_secctl, armssedev, name);
476 g_free(name);
477 name = g_strdup_printf("%s_irq_enable", ppcname);
478 qdev_pass_gpios(dev_secctl, armssedev, name);
479 g_free(name);
480 name = g_strdup_printf("%s_irq_clear", ppcname);
481 qdev_pass_gpios(dev_secctl, armssedev, name);
482 g_free(name);
483
484 /* irq_status is a little more tricky, because we need to
485 * split it so we can send it both to the security controller
486 * and to our OR gate for the NVIC interrupt line.
487 * Connect up the splitter's outputs, and create a GPIO input
488 * which will pass the line state to the input splitter.
489 */
490 name = g_strdup_printf("%s_irq_status", ppcname);
491 qdev_connect_gpio_out(dev_splitter, 0,
492 qdev_get_gpio_in_named(dev_secctl,
493 name, 0));
494 qdev_connect_gpio_out(dev_splitter, 1,
495 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum));
496 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0);
497 qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder,
498 s->irq_status_in[ppcnum], name, 1);
499 g_free(name);
500 }
501
502 static void armsse_forward_sec_resp_cfg(ARMSSE *s)
503 {
504 /* Forward the 3rd output from the splitter device as a
505 * named GPIO output of the armsse object.
506 */
507 DeviceState *dev = DEVICE(s);
508 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter);
509
510 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1);
511 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder,
512 s->sec_resp_cfg, 1);
513 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in);
514 }
515
516 static void armsse_mainclk_update(void *opaque, ClockEvent event)
517 {
518 ARMSSE *s = ARM_SSE(opaque);
519
520 /*
521 * Set system_clock_scale from our Clock input; this is what
522 * controls the tick rate of the CPU SysTick timer.
523 */
524 system_clock_scale = clock_ticks_to_ns(s->mainclk, 1);
525 }
526
527 static void armsse_init(Object *obj)
528 {
529 ARMSSE *s = ARM_SSE(obj);
530 ARMSSEClass *asc = ARM_SSE_GET_CLASS(obj);
531 const ARMSSEInfo *info = asc->info;
532 const ARMSSEDeviceInfo *devinfo;
533 int i;
534
535 assert(info->sram_banks <= MAX_SRAM_BANKS);
536 assert(info->num_cpus <= SSE_MAX_CPUS);
537
538 s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK",
539 armsse_mainclk_update, s, ClockUpdate);
540 s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0);
541
542 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX);
543
544 for (i = 0; i < info->num_cpus; i++) {
545 /*
546 * We put each CPU in its own cluster as they are logically
547 * distinct and may be configured differently.
548 */
549 char *name;
550
551 name = g_strdup_printf("cluster%d", i);
552 object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER);
553 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i);
554 g_free(name);
555
556 name = g_strdup_printf("armv7m%d", i);
557 object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i],
558 TYPE_ARMV7M);
559 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type",
560 ARM_CPU_TYPE_NAME("cortex-m33"));
561 g_free(name);
562 name = g_strdup_printf("arm-sse-cpu-container%d", i);
563 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX);
564 g_free(name);
565 if (i > 0) {
566 name = g_strdup_printf("arm-sse-container-alias%d", i);
567 memory_region_init_alias(&s->container_alias[i - 1], obj,
568 name, &s->container, 0, UINT64_MAX);
569 g_free(name);
570 }
571 }
572
573 for (devinfo = info->devinfo; devinfo->name; devinfo++) {
574 assert(devinfo->ppc == NO_PPC || devinfo->ppc < ARRAY_SIZE(s->apb_ppc));
575 if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) {
576 assert(devinfo->index < ARRAY_SIZE(s->timer));
577 object_initialize_child(obj, devinfo->name,
578 &s->timer[devinfo->index],
579 TYPE_CMSDK_APB_TIMER);
580 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) {
581 assert(devinfo->index == 0);
582 object_initialize_child(obj, devinfo->name, &s->dualtimer,
583 TYPE_CMSDK_APB_DUALTIMER);
584 } else if (!strcmp(devinfo->type, TYPE_SSE_TIMER)) {
585 assert(devinfo->index < ARRAY_SIZE(s->sse_timer));
586 object_initialize_child(obj, devinfo->name,
587 &s->sse_timer[devinfo->index],
588 TYPE_SSE_TIMER);
589 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) {
590 assert(devinfo->index < ARRAY_SIZE(s->cmsdk_watchdog));
591 object_initialize_child(obj, devinfo->name,
592 &s->cmsdk_watchdog[devinfo->index],
593 TYPE_CMSDK_APB_WATCHDOG);
594 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSINFO)) {
595 assert(devinfo->index == 0);
596 object_initialize_child(obj, devinfo->name, &s->sysinfo,
597 TYPE_IOTKIT_SYSINFO);
598 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSCTL)) {
599 assert(devinfo->index == 0);
600 object_initialize_child(obj, devinfo->name, &s->sysctl,
601 TYPE_IOTKIT_SYSCTL);
602 } else if (!strcmp(devinfo->type, TYPE_UNIMPLEMENTED_DEVICE)) {
603 assert(devinfo->index < ARRAY_SIZE(s->unimp));
604 object_initialize_child(obj, devinfo->name,
605 &s->unimp[devinfo->index],
606 TYPE_UNIMPLEMENTED_DEVICE);
607 } else {
608 g_assert_not_reached();
609 }
610 }
611
612 object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL);
613
614 for (i = 0; i < ARRAY_SIZE(s->apb_ppc); i++) {
615 g_autofree char *name = g_strdup_printf("apb-ppc%d", i);
616 object_initialize_child(obj, name, &s->apb_ppc[i], TYPE_TZ_PPC);
617 }
618
619 for (i = 0; i < info->sram_banks; i++) {
620 char *name = g_strdup_printf("mpc%d", i);
621 object_initialize_child(obj, name, &s->mpc[i], TYPE_TZ_MPC);
622 g_free(name);
623 }
624 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate,
625 TYPE_OR_IRQ);
626
627 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) {
628 char *name = g_strdup_printf("mpc-irq-splitter-%d", i);
629 SplitIRQ *splitter = &s->mpc_irq_splitter[i];
630
631 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ);
632 g_free(name);
633 }
634
635 if (info->has_mhus) {
636 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU);
637 object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU);
638 }
639 if (info->has_cachectrl) {
640 for (i = 0; i < info->num_cpus; i++) {
641 char *name = g_strdup_printf("cachectrl%d", i);
642
643 object_initialize_child(obj, name, &s->cachectrl[i],
644 TYPE_UNIMPLEMENTED_DEVICE);
645 g_free(name);
646 }
647 }
648 if (info->has_cpusecctrl) {
649 for (i = 0; i < info->num_cpus; i++) {
650 char *name = g_strdup_printf("cpusecctrl%d", i);
651
652 object_initialize_child(obj, name, &s->cpusecctrl[i],
653 TYPE_UNIMPLEMENTED_DEVICE);
654 g_free(name);
655 }
656 }
657 if (info->has_cpuid) {
658 for (i = 0; i < info->num_cpus; i++) {
659 char *name = g_strdup_printf("cpuid%d", i);
660
661 object_initialize_child(obj, name, &s->cpuid[i],
662 TYPE_ARMSSE_CPUID);
663 g_free(name);
664 }
665 }
666 if (info->has_cpu_pwrctrl) {
667 for (i = 0; i < info->num_cpus; i++) {
668 char *name = g_strdup_printf("cpu_pwrctrl%d", i);
669
670 object_initialize_child(obj, name, &s->cpu_pwrctrl[i],
671 TYPE_ARMSSE_CPU_PWRCTRL);
672 g_free(name);
673 }
674 }
675 if (info->has_sse_counter) {
676 object_initialize_child(obj, "sse-counter", &s->sse_counter,
677 TYPE_SSE_COUNTER);
678 }
679
680 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ);
681 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate,
682 TYPE_OR_IRQ);
683 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter,
684 TYPE_SPLIT_IRQ);
685 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) {
686 char *name = g_strdup_printf("ppc-irq-splitter-%d", i);
687 SplitIRQ *splitter = &s->ppc_irq_splitter[i];
688
689 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ);
690 g_free(name);
691 }
692 if (info->num_cpus > 1) {
693 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) {
694 if (info->irq_is_common[i]) {
695 char *name = g_strdup_printf("cpu-irq-splitter%d", i);
696 SplitIRQ *splitter = &s->cpu_irq_splitter[i];
697
698 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ);
699 g_free(name);
700 }
701 }
702 }
703 }
704
705 static void armsse_exp_irq(void *opaque, int n, int level)
706 {
707 qemu_irq *irqarray = opaque;
708
709 qemu_set_irq(irqarray[n], level);
710 }
711
712 static void armsse_mpcexp_status(void *opaque, int n, int level)
713 {
714 ARMSSE *s = ARM_SSE(opaque);
715 qemu_set_irq(s->mpcexp_status_in[n], level);
716 }
717
718 static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno)
719 {
720 /*
721 * Return a qemu_irq which can be used to signal IRQ n to
722 * all CPUs in the SSE.
723 */
724 ARMSSEClass *asc = ARM_SSE_GET_CLASS(s);
725 const ARMSSEInfo *info = asc->info;
726
727 assert(info->irq_is_common[irqno]);
728
729 if (info->num_cpus == 1) {
730 /* Only one CPU -- just connect directly to it */
731 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno);
732 } else {
733 /* Connect to the splitter which feeds all CPUs */
734 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0);
735 }
736 }
737
738 static void armsse_realize(DeviceState *dev, Error **errp)
739 {
740 ARMSSE *s = ARM_SSE(dev);
741 ARMSSEClass *asc = ARM_SSE_GET_CLASS(dev);
742 const ARMSSEInfo *info = asc->info;
743 const ARMSSEDeviceInfo *devinfo;
744 int i;
745 MemoryRegion *mr;
746 Error *err = NULL;
747 SysBusDevice *sbd_apb_ppc0;
748 SysBusDevice *sbd_secctl;
749 DeviceState *dev_apb_ppc0;
750 DeviceState *dev_apb_ppc1;
751 DeviceState *dev_secctl;
752 DeviceState *dev_splitter;
753 uint32_t addr_width_max;
754
755 if (!s->board_memory) {
756 error_setg(errp, "memory property was not set");
757 return;
758 }
759
760 if (!clock_has_source(s->mainclk)) {
761 error_setg(errp, "MAINCLK clock was not connected");
762 }
763 if (!clock_has_source(s->s32kclk)) {
764 error_setg(errp, "S32KCLK clock was not connected");
765 }
766
767 assert(info->num_cpus <= SSE_MAX_CPUS);
768
769 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
770 assert(is_power_of_2(info->sram_banks));
771 addr_width_max = 24 - ctz32(info->sram_banks);
772 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) {
773 error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d",
774 addr_width_max);
775 return;
776 }
777
778 /* Handling of which devices should be available only to secure
779 * code is usually done differently for M profile than for A profile.
780 * Instead of putting some devices only into the secure address space,
781 * devices exist in both address spaces but with hard-wired security
782 * permissions that will cause the CPU to fault for non-secure accesses.
783 *
784 * The ARMSSE has an IDAU (Implementation Defined Access Unit),
785 * which specifies hard-wired security permissions for different
786 * areas of the physical address space. For the ARMSSE IDAU, the
787 * top 4 bits of the physical address are the IDAU region ID, and
788 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS
789 * region, otherwise it is an S region.
790 *
791 * The various devices and RAMs are generally all mapped twice,
792 * once into a region that the IDAU defines as secure and once
793 * into a non-secure region. They sit behind either a Memory
794 * Protection Controller (for RAM) or a Peripheral Protection
795 * Controller (for devices), which allow a more fine grained
796 * configuration of whether non-secure accesses are permitted.
797 *
798 * (The other place that guest software can configure security
799 * permissions is in the architected SAU (Security Attribution
800 * Unit), which is entirely inside the CPU. The IDAU can upgrade
801 * the security attributes for a region to more restrictive than
802 * the SAU specifies, but cannot downgrade them.)
803 *
804 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff
805 * 0x20000000..0x2007ffff 32KB FPGA block RAM
806 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff
807 * 0x40000000..0x4000ffff base peripheral region 1
808 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE)
809 * 0x40020000..0x4002ffff system control element peripherals
810 * 0x40080000..0x400fffff base peripheral region 2
811 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff
812 */
813
814 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2);
815
816 for (i = 0; i < info->num_cpus; i++) {
817 DeviceState *cpudev = DEVICE(&s->armv7m[i]);
818 Object *cpuobj = OBJECT(&s->armv7m[i]);
819 int j;
820 char *gpioname;
821
822 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IRQS);
823 /*
824 * In real hardware the initial Secure VTOR is set from the INITSVTOR*
825 * registers in the IoT Kit System Control Register block. In QEMU
826 * we set the initial value here, and also the reset value of the
827 * sysctl register, from this object's QOM init-svtor property.
828 * If the guest changes the INITSVTOR* registers at runtime then the
829 * code in iotkit-sysctl.c will update the CPU init-svtor property
830 * (which will then take effect on the next CPU warm-reset).
831 *
832 * Note that typically a board using the SSE-200 will have a system
833 * control processor whose boot firmware initializes the INITSVTOR*
834 * registers before powering up the CPUs. QEMU doesn't emulate
835 * the control processor, so instead we behave in the way that the
836 * firmware does: the initial value should be set by the board code
837 * (using the init-svtor property on the ARMSSE object) to match
838 * whatever its firmware does.
839 */
840 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor);
841 /*
842 * CPUs start powered down if the corresponding bit in the CPUWAIT
843 * register is 1. In real hardware the CPUWAIT register reset value is
844 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and
845 * CPUWAIT1_RST parameters), but since all the boards we care about
846 * start CPU0 and leave CPU1 powered off, we hard-code that in
847 * info->cpuwait_rst for now. We can add QOM properties for this
848 * later if necessary.
849 */
850 if (extract32(info->cpuwait_rst, i, 1)) {
851 if (!object_property_set_bool(cpuobj, "start-powered-off", true,
852 errp)) {
853 return;
854 }
855 }
856 if (!s->cpu_fpu[i]) {
857 if (!object_property_set_bool(cpuobj, "vfp", false, errp)) {
858 return;
859 }
860 }
861 if (!s->cpu_dsp[i]) {
862 if (!object_property_set_bool(cpuobj, "dsp", false, errp)) {
863 return;
864 }
865 }
866
867 if (i > 0) {
868 memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
869 &s->container_alias[i - 1], -1);
870 } else {
871 memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
872 &s->container, -1);
873 }
874 object_property_set_link(cpuobj, "memory",
875 OBJECT(&s->cpu_container[i]), &error_abort);
876 object_property_set_link(cpuobj, "idau", OBJECT(s), &error_abort);
877 if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj), errp)) {
878 return;
879 }
880 /*
881 * The cluster must be realized after the armv7m container, as
882 * the container's CPU object is only created on realize, and the
883 * CPU must exist and have been parented into the cluster before
884 * the cluster is realized.
885 */
886 if (!qdev_realize(DEVICE(&s->cluster[i]), NULL, errp)) {
887 return;
888 }
889
890 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */
891 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq);
892 for (j = 0; j < s->exp_numirq; j++) {
893 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + NUM_SSE_IRQS);
894 }
895 if (i == 0) {
896 gpioname = g_strdup("EXP_IRQ");
897 } else {
898 gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i);
899 }
900 qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq,
901 s->exp_irqs[i],
902 gpioname, s->exp_numirq);
903 g_free(gpioname);
904 }
905
906 /* Wire up the splitters that connect common IRQs to all CPUs */
907 if (info->num_cpus > 1) {
908 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) {
909 if (info->irq_is_common[i]) {
910 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]);
911 DeviceState *devs = DEVICE(splitter);
912 int cpunum;
913
914 if (!object_property_set_int(splitter, "num-lines",
915 info->num_cpus, errp)) {
916 return;
917 }
918 if (!qdev_realize(DEVICE(splitter), NULL, errp)) {
919 return;
920 }
921 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) {
922 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]);
923
924 qdev_connect_gpio_out(devs, cpunum,
925 qdev_get_gpio_in(cpudev, i));
926 }
927 }
928 }
929 }
930
931 /* Set up the big aliases first */
932 make_alias(s, &s->alias1, &s->container, "alias 1",
933 0x10000000, 0x10000000, 0x00000000);
934 make_alias(s, &s->alias2, &s->container,
935 "alias 2", 0x30000000, 0x10000000, 0x20000000);
936 /* The 0x50000000..0x5fffffff region is not a pure alias: it has
937 * a few extra devices that only appear there (generally the
938 * control interfaces for the protection controllers).
939 * We implement this by mapping those devices over the top of this
940 * alias MR at a higher priority. Some of the devices in this range
941 * are per-CPU, so we must put this alias in the per-cpu containers.
942 */
943 for (i = 0; i < info->num_cpus; i++) {
944 make_alias(s, &s->alias3[i], &s->cpu_container[i],
945 "alias 3", 0x50000000, 0x10000000, 0x40000000);
946 }
947
948 /* Security controller */
949 object_property_set_int(OBJECT(&s->secctl), "sse-version",
950 info->sse_version, &error_abort);
951 if (!sysbus_realize(SYS_BUS_DEVICE(&s->secctl), errp)) {
952 return;
953 }
954 sbd_secctl = SYS_BUS_DEVICE(&s->secctl);
955 dev_secctl = DEVICE(&s->secctl);
956 sysbus_mmio_map(sbd_secctl, 0, 0x50080000);
957 sysbus_mmio_map(sbd_secctl, 1, 0x40080000);
958
959 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1);
960 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in);
961
962 /* The sec_resp_cfg output from the security controller must be split into
963 * multiple lines, one for each of the PPCs within the ARMSSE and one
964 * that will be an output from the ARMSSE to the system.
965 */
966 if (!object_property_set_int(OBJECT(&s->sec_resp_splitter),
967 "num-lines", 3, errp)) {
968 return;
969 }
970 if (!qdev_realize(DEVICE(&s->sec_resp_splitter), NULL, errp)) {
971 return;
972 }
973 dev_splitter = DEVICE(&s->sec_resp_splitter);
974 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0,
975 qdev_get_gpio_in(dev_splitter, 0));
976
977 /* Each SRAM bank lives behind its own Memory Protection Controller */
978 for (i = 0; i < info->sram_banks; i++) {
979 char *ramname = g_strdup_printf("armsse.sram%d", i);
980 SysBusDevice *sbd_mpc;
981 uint32_t sram_bank_size = 1 << s->sram_addr_width;
982
983 memory_region_init_ram(&s->sram[i], NULL, ramname,
984 sram_bank_size, &err);
985 g_free(ramname);
986 if (err) {
987 error_propagate(errp, err);
988 return;
989 }
990 object_property_set_link(OBJECT(&s->mpc[i]), "downstream",
991 OBJECT(&s->sram[i]), &error_abort);
992 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), errp)) {
993 return;
994 }
995 /* Map the upstream end of the MPC into the right place... */
996 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]);
997 memory_region_add_subregion(&s->container,
998 0x20000000 + i * sram_bank_size,
999 sysbus_mmio_get_region(sbd_mpc, 1));
1000 /* ...and its register interface */
1001 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000,
1002 sysbus_mmio_get_region(sbd_mpc, 0));
1003 }
1004
1005 /* We must OR together lines from the MPC splitters to go to the NVIC */
1006 if (!object_property_set_int(OBJECT(&s->mpc_irq_orgate), "num-lines",
1007 IOTS_NUM_EXP_MPC + info->sram_banks,
1008 errp)) {
1009 return;
1010 }
1011 if (!qdev_realize(DEVICE(&s->mpc_irq_orgate), NULL, errp)) {
1012 return;
1013 }
1014 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0,
1015 armsse_get_common_irq_in(s, 9));
1016
1017 /* This OR gate wires together outputs from the secure watchdogs to NMI */
1018 if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2,
1019 errp)) {
1020 return;
1021 }
1022 if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) {
1023 return;
1024 }
1025 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0,
1026 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0));
1027
1028 /* The SSE-300 has a System Counter / System Timestamp Generator */
1029 if (info->has_sse_counter) {
1030 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sse_counter);
1031
1032 qdev_connect_clock_in(DEVICE(sbd), "CLK", s->mainclk);
1033 if (!sysbus_realize(sbd, errp)) {
1034 return;
1035 }
1036 /*
1037 * The control frame is only in the Secure region;
1038 * the status frame is in the NS region (and visible in the
1039 * S region via the alias mapping).
1040 */
1041 memory_region_add_subregion(&s->container, 0x58100000,
1042 sysbus_mmio_get_region(sbd, 0));
1043 memory_region_add_subregion(&s->container, 0x48101000,
1044 sysbus_mmio_get_region(sbd, 1));
1045 }
1046
1047 /* Devices behind APB PPC0:
1048 * 0x40000000: timer0
1049 * 0x40001000: timer1
1050 * 0x40002000: dual timer
1051 * 0x40003000: MHU0 (SSE-200 only)
1052 * 0x40004000: MHU1 (SSE-200 only)
1053 * We must configure and realize each downstream device and connect
1054 * it to the appropriate PPC port; then we can realize the PPC and
1055 * map its upstream ends to the right place in the container.
1056 */
1057 for (devinfo = info->devinfo; devinfo->name; devinfo++) {
1058 SysBusDevice *sbd;
1059 qemu_irq irq;
1060
1061 if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) {
1062 sbd = SYS_BUS_DEVICE(&s->timer[devinfo->index]);
1063
1064 qdev_connect_clock_in(DEVICE(sbd), "pclk",
1065 devinfo->slowclk ? s->s32kclk : s->mainclk);
1066 if (!sysbus_realize(sbd, errp)) {
1067 return;
1068 }
1069 mr = sysbus_mmio_get_region(sbd, 0);
1070 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) {
1071 sbd = SYS_BUS_DEVICE(&s->dualtimer);
1072
1073 qdev_connect_clock_in(DEVICE(sbd), "TIMCLK", s->mainclk);
1074 if (!sysbus_realize(sbd, errp)) {
1075 return;
1076 }
1077 mr = sysbus_mmio_get_region(sbd, 0);
1078 } else if (!strcmp(devinfo->type, TYPE_SSE_TIMER)) {
1079 sbd = SYS_BUS_DEVICE(&s->sse_timer[devinfo->index]);
1080
1081 assert(info->has_sse_counter);
1082 object_property_set_link(OBJECT(sbd), "counter",
1083 OBJECT(&s->sse_counter), &error_abort);
1084 if (!sysbus_realize(sbd, errp)) {
1085 return;
1086 }
1087 mr = sysbus_mmio_get_region(sbd, 0);
1088 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) {
1089 sbd = SYS_BUS_DEVICE(&s->cmsdk_watchdog[devinfo->index]);
1090
1091 qdev_connect_clock_in(DEVICE(sbd), "WDOGCLK",
1092 devinfo->slowclk ? s->s32kclk : s->mainclk);
1093 if (!sysbus_realize(sbd, errp)) {
1094 return;
1095 }
1096 mr = sysbus_mmio_get_region(sbd, 0);
1097 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSINFO)) {
1098 sbd = SYS_BUS_DEVICE(&s->sysinfo);
1099
1100 object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION",
1101 info->sys_version, &error_abort);
1102 object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG",
1103 armsse_sys_config_value(s, info),
1104 &error_abort);
1105 object_property_set_int(OBJECT(&s->sysinfo), "sse-version",
1106 info->sse_version, &error_abort);
1107 object_property_set_int(OBJECT(&s->sysinfo), "IIDR",
1108 info->iidr, &error_abort);
1109 if (!sysbus_realize(sbd, errp)) {
1110 return;
1111 }
1112 mr = sysbus_mmio_get_region(sbd, 0);
1113 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSCTL)) {
1114 /* System control registers */
1115 sbd = SYS_BUS_DEVICE(&s->sysctl);
1116
1117 object_property_set_int(OBJECT(&s->sysctl), "sse-version",
1118 info->sse_version, &error_abort);
1119 object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST",
1120 info->cpuwait_rst, &error_abort);
1121 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST",
1122 s->init_svtor, &error_abort);
1123 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST",
1124 s->init_svtor, &error_abort);
1125 if (!sysbus_realize(sbd, errp)) {
1126 return;
1127 }
1128 mr = sysbus_mmio_get_region(sbd, 0);
1129 } else if (!strcmp(devinfo->type, TYPE_UNIMPLEMENTED_DEVICE)) {
1130 sbd = SYS_BUS_DEVICE(&s->unimp[devinfo->index]);
1131
1132 qdev_prop_set_string(DEVICE(sbd), "name", devinfo->name);
1133 qdev_prop_set_uint64(DEVICE(sbd), "size", devinfo->size);
1134 if (!sysbus_realize(sbd, errp)) {
1135 return;
1136 }
1137 mr = sysbus_mmio_get_region(sbd, 0);
1138 } else {
1139 g_assert_not_reached();
1140 }
1141
1142 switch (devinfo->irq) {
1143 case NO_IRQ:
1144 irq = NULL;
1145 break;
1146 case 0 ... NUM_SSE_IRQS - 1:
1147 irq = armsse_get_common_irq_in(s, devinfo->irq);
1148 break;
1149 case NMI_0:
1150 case NMI_1:
1151 irq = qdev_get_gpio_in(DEVICE(&s->nmi_orgate),
1152 devinfo->irq - NMI_0);
1153 break;
1154 default:
1155 g_assert_not_reached();
1156 }
1157
1158 if (irq) {
1159 sysbus_connect_irq(sbd, 0, irq);
1160 }
1161
1162 /*
1163 * Devices connected to a PPC are connected to the port here;
1164 * we will map the upstream end of that port to the right address
1165 * in the container later after the PPC has been realized.
1166 * Devices not connected to a PPC can be mapped immediately.
1167 */
1168 if (devinfo->ppc != NO_PPC) {
1169 TZPPC *ppc = &s->apb_ppc[devinfo->ppc];
1170 g_autofree char *portname = g_strdup_printf("port[%d]",
1171 devinfo->ppc_port);
1172 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr),
1173 &error_abort);
1174 } else {
1175 memory_region_add_subregion(&s->container, devinfo->addr, mr);
1176 }
1177 }
1178
1179 if (info->has_mhus) {
1180 /*
1181 * An SSE-200 with only one CPU should have only one MHU created,
1182 * with the region where the second MHU usually is being RAZ/WI.
1183 * We don't implement that SSE-200 config; if we want to support
1184 * it then this code needs to be enhanced to handle creating the
1185 * RAZ/WI region instead of the second MHU.
1186 */
1187 assert(info->num_cpus == ARRAY_SIZE(s->mhu));
1188
1189 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
1190 char *port;
1191 int cpunum;
1192 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]);
1193
1194 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), errp)) {
1195 return;
1196 }
1197 port = g_strdup_printf("port[%d]", i + 3);
1198 mr = sysbus_mmio_get_region(mhu_sbd, 0);
1199 object_property_set_link(OBJECT(&s->apb_ppc[0]), port, OBJECT(mr),
1200 &error_abort);
1201 g_free(port);
1202
1203 /*
1204 * Each MHU has an irq line for each CPU:
1205 * MHU 0 irq line 0 -> CPU 0 IRQ 6
1206 * MHU 0 irq line 1 -> CPU 1 IRQ 6
1207 * MHU 1 irq line 0 -> CPU 0 IRQ 7
1208 * MHU 1 irq line 1 -> CPU 1 IRQ 7
1209 */
1210 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) {
1211 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]);
1212
1213 sysbus_connect_irq(mhu_sbd, cpunum,
1214 qdev_get_gpio_in(cpudev, 6 + i));
1215 }
1216 }
1217 }
1218
1219 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[0]), errp)) {
1220 return;
1221 }
1222
1223 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc[0]);
1224 dev_apb_ppc0 = DEVICE(&s->apb_ppc[0]);
1225
1226 if (info->has_mhus) {
1227 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3);
1228 memory_region_add_subregion(&s->container, 0x40003000, mr);
1229 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4);
1230 memory_region_add_subregion(&s->container, 0x40004000, mr);
1231 }
1232 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) {
1233 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i,
1234 qdev_get_gpio_in_named(dev_apb_ppc0,
1235 "cfg_nonsec", i));
1236 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i,
1237 qdev_get_gpio_in_named(dev_apb_ppc0,
1238 "cfg_ap", i));
1239 }
1240 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0,
1241 qdev_get_gpio_in_named(dev_apb_ppc0,
1242 "irq_enable", 0));
1243 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0,
1244 qdev_get_gpio_in_named(dev_apb_ppc0,
1245 "irq_clear", 0));
1246 qdev_connect_gpio_out(dev_splitter, 0,
1247 qdev_get_gpio_in_named(dev_apb_ppc0,
1248 "cfg_sec_resp", 0));
1249
1250 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external
1251 * ones) are sent individually to the security controller, and also
1252 * ORed together to give a single combined PPC interrupt to the NVIC.
1253 */
1254 if (!object_property_set_int(OBJECT(&s->ppc_irq_orgate),
1255 "num-lines", NUM_PPCS, errp)) {
1256 return;
1257 }
1258 if (!qdev_realize(DEVICE(&s->ppc_irq_orgate), NULL, errp)) {
1259 return;
1260 }
1261 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0,
1262 armsse_get_common_irq_in(s, 10));
1263
1264 /*
1265 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias):
1266 * private per-CPU region (all these devices are SSE-200 only):
1267 * 0x50010000: L1 icache control registers
1268 * 0x50011000: CPUSECCTRL (CPU local security control registers)
1269 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block
1270 * The SSE-300 has an extra:
1271 * 0x40012000 and 0x50012000: CPU_PWRCTRL register block
1272 */
1273 if (info->has_cachectrl) {
1274 for (i = 0; i < info->num_cpus; i++) {
1275 char *name = g_strdup_printf("cachectrl%d", i);
1276 MemoryRegion *mr;
1277
1278 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name);
1279 g_free(name);
1280 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000);
1281 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cachectrl[i]), errp)) {
1282 return;
1283 }
1284
1285 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0);
1286 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr);
1287 }
1288 }
1289 if (info->has_cpusecctrl) {
1290 for (i = 0; i < info->num_cpus; i++) {
1291 char *name = g_strdup_printf("CPUSECCTRL%d", i);
1292 MemoryRegion *mr;
1293
1294 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name);
1295 g_free(name);
1296 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000);
1297 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpusecctrl[i]), errp)) {
1298 return;
1299 }
1300
1301 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0);
1302 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr);
1303 }
1304 }
1305 if (info->has_cpuid) {
1306 for (i = 0; i < info->num_cpus; i++) {
1307 MemoryRegion *mr;
1308
1309 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i);
1310 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpuid[i]), errp)) {
1311 return;
1312 }
1313
1314 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0);
1315 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr);
1316 }
1317 }
1318 if (info->has_cpu_pwrctrl) {
1319 for (i = 0; i < info->num_cpus; i++) {
1320 MemoryRegion *mr;
1321
1322 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), errp)) {
1323 return;
1324 }
1325
1326 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), 0);
1327 memory_region_add_subregion(&s->cpu_container[i], 0x40012000, mr);
1328 }
1329 }
1330
1331 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[1]), errp)) {
1332 return;
1333 }
1334
1335 dev_apb_ppc1 = DEVICE(&s->apb_ppc[1]);
1336 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0,
1337 qdev_get_gpio_in_named(dev_apb_ppc1,
1338 "cfg_nonsec", 0));
1339 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0,
1340 qdev_get_gpio_in_named(dev_apb_ppc1,
1341 "cfg_ap", 0));
1342 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0,
1343 qdev_get_gpio_in_named(dev_apb_ppc1,
1344 "irq_enable", 0));
1345 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0,
1346 qdev_get_gpio_in_named(dev_apb_ppc1,
1347 "irq_clear", 0));
1348 qdev_connect_gpio_out(dev_splitter, 1,
1349 qdev_get_gpio_in_named(dev_apb_ppc1,
1350 "cfg_sec_resp", 0));
1351
1352 /*
1353 * Now both PPCs are realized we can map the upstream ends of
1354 * ports which correspond to entries in the devinfo array.
1355 * The ports which are connected to non-devinfo devices have
1356 * already been mapped.
1357 */
1358 for (devinfo = info->devinfo; devinfo->name; devinfo++) {
1359 SysBusDevice *ppc_sbd;
1360
1361 if (devinfo->ppc == NO_PPC) {
1362 continue;
1363 }
1364 ppc_sbd = SYS_BUS_DEVICE(&s->apb_ppc[devinfo->ppc]);
1365 mr = sysbus_mmio_get_region(ppc_sbd, devinfo->ppc_port);
1366 memory_region_add_subregion(&s->container, devinfo->addr, mr);
1367 }
1368
1369 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) {
1370 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]);
1371
1372 if (!object_property_set_int(splitter, "num-lines", 2, errp)) {
1373 return;
1374 }
1375 if (!qdev_realize(DEVICE(splitter), NULL, errp)) {
1376 return;
1377 }
1378 }
1379
1380 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) {
1381 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i);
1382
1383 armsse_forward_ppc(s, ppcname, i);
1384 g_free(ppcname);
1385 }
1386
1387 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) {
1388 char *ppcname = g_strdup_printf("apb_ppcexp%d", i);
1389
1390 armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC);
1391 g_free(ppcname);
1392 }
1393
1394 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) {
1395 /* Wire up IRQ splitter for internal PPCs */
1396 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]);
1397 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status",
1398 i - NUM_EXTERNAL_PPCS);
1399 TZPPC *ppc = &s->apb_ppc[i - NUM_EXTERNAL_PPCS];
1400
1401 qdev_connect_gpio_out(devs, 0,
1402 qdev_get_gpio_in_named(dev_secctl, gpioname, 0));
1403 qdev_connect_gpio_out(devs, 1,
1404 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i));
1405 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0,
1406 qdev_get_gpio_in(devs, 0));
1407 g_free(gpioname);
1408 }
1409
1410 /* Wire up the splitters for the MPC IRQs */
1411 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) {
1412 SplitIRQ *splitter = &s->mpc_irq_splitter[i];
1413 DeviceState *dev_splitter = DEVICE(splitter);
1414
1415 if (!object_property_set_int(OBJECT(splitter), "num-lines", 2,
1416 errp)) {
1417 return;
1418 }
1419 if (!qdev_realize(DEVICE(splitter), NULL, errp)) {
1420 return;
1421 }
1422
1423 if (i < IOTS_NUM_EXP_MPC) {
1424 /* Splitter input is from GPIO input line */
1425 s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0);
1426 qdev_connect_gpio_out(dev_splitter, 0,
1427 qdev_get_gpio_in_named(dev_secctl,
1428 "mpcexp_status", i));
1429 } else {
1430 /* Splitter input is from our own MPC */
1431 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]),
1432 "irq", 0,
1433 qdev_get_gpio_in(dev_splitter, 0));
1434 qdev_connect_gpio_out(dev_splitter, 0,
1435 qdev_get_gpio_in_named(dev_secctl,
1436 "mpc_status",
1437 i - IOTS_NUM_EXP_MPC));
1438 }
1439
1440 qdev_connect_gpio_out(dev_splitter, 1,
1441 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i));
1442 }
1443 /* Create GPIO inputs which will pass the line state for our
1444 * mpcexp_irq inputs to the correct splitter devices.
1445 */
1446 qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status",
1447 IOTS_NUM_EXP_MPC);
1448
1449 armsse_forward_sec_resp_cfg(s);
1450
1451 /* Forward the MSC related signals */
1452 qdev_pass_gpios(dev_secctl, dev, "mscexp_status");
1453 qdev_pass_gpios(dev_secctl, dev, "mscexp_clear");
1454 qdev_pass_gpios(dev_secctl, dev, "mscexp_ns");
1455 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0,
1456 armsse_get_common_irq_in(s, 11));
1457
1458 /*
1459 * Expose our container region to the board model; this corresponds
1460 * to the AHB Slave Expansion ports which allow bus master devices
1461 * (eg DMA controllers) in the board model to make transactions into
1462 * devices in the ARMSSE.
1463 */
1464 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container);
1465
1466 /* Set initial system_clock_scale from MAINCLK */
1467 armsse_mainclk_update(s, ClockUpdate);
1468 }
1469
1470 static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
1471 int *iregion, bool *exempt, bool *ns, bool *nsc)
1472 {
1473 /*
1474 * For ARMSSE systems the IDAU responses are simple logical functions
1475 * of the address bits. The NSC attribute is guest-adjustable via the
1476 * NSCCFG register in the security controller.
1477 */
1478 ARMSSE *s = ARM_SSE(ii);
1479 int region = extract32(address, 28, 4);
1480
1481 *ns = !(region & 1);
1482 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2));
1483 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
1484 *exempt = (address & 0xeff00000) == 0xe0000000;
1485 *iregion = region;
1486 }
1487
1488 static const VMStateDescription armsse_vmstate = {
1489 .name = "iotkit",
1490 .version_id = 2,
1491 .minimum_version_id = 2,
1492 .fields = (VMStateField[]) {
1493 VMSTATE_CLOCK(mainclk, ARMSSE),
1494 VMSTATE_CLOCK(s32kclk, ARMSSE),
1495 VMSTATE_UINT32(nsccfg, ARMSSE),
1496 VMSTATE_END_OF_LIST()
1497 }
1498 };
1499
1500 static void armsse_reset(DeviceState *dev)
1501 {
1502 ARMSSE *s = ARM_SSE(dev);
1503
1504 s->nsccfg = 0;
1505 }
1506
1507 static void armsse_class_init(ObjectClass *klass, void *data)
1508 {
1509 DeviceClass *dc = DEVICE_CLASS(klass);
1510 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass);
1511 ARMSSEClass *asc = ARM_SSE_CLASS(klass);
1512 const ARMSSEInfo *info = data;
1513
1514 dc->realize = armsse_realize;
1515 dc->vmsd = &armsse_vmstate;
1516 device_class_set_props(dc, info->props);
1517 dc->reset = armsse_reset;
1518 iic->check = armsse_idau_check;
1519 asc->info = info;
1520 }
1521
1522 static const TypeInfo armsse_info = {
1523 .name = TYPE_ARM_SSE,
1524 .parent = TYPE_SYS_BUS_DEVICE,
1525 .instance_size = sizeof(ARMSSE),
1526 .class_size = sizeof(ARMSSEClass),
1527 .instance_init = armsse_init,
1528 .abstract = true,
1529 .interfaces = (InterfaceInfo[]) {
1530 { TYPE_IDAU_INTERFACE },
1531 { }
1532 }
1533 };
1534
1535 static void armsse_register_types(void)
1536 {
1537 int i;
1538
1539 type_register_static(&armsse_info);
1540
1541 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) {
1542 TypeInfo ti = {
1543 .name = armsse_variants[i].name,
1544 .parent = TYPE_ARM_SSE,
1545 .class_init = armsse_class_init,
1546 .class_data = (void *)&armsse_variants[i],
1547 };
1548 type_register(&ti);
1549 }
1550 }
1551
1552 type_init(armsse_register_types);
AR7 emulation for QEMU