| commit | 4668b441cb667619916d4bc6a204f3df06730dfb | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 19 Feb 2021 14:46:07 +0000 (19 14:46 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 8 Mar 2021 17:20:03 +0000 (8 17:20 +0000) | ||
| tree | 36bea8a85984bb1c4c58c8d3be76a695d768e993 | treesnapshot (tar.gz zip) |
| parent | f11de23158528c90b51c603c0cc3b2286e71d3fc | commitdiff |
hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block
Support SSE variants like the SSE-300 with an ARMSSE_CPU_PWRCTRL register
block. Because this block is per-CPU and does not clash with any of the
SSE-200 devices, we handle it with a has_cpu_pwrctrl flag like the
existing has_cachectrl, has_cpusectrl and has_cpuid, rather than
trying to add per-CPU-device support to the devinfo array handling code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-35-peter.maydell@linaro.org
Support SSE variants like the SSE-300 with an ARMSSE_CPU_PWRCTRL register
block. Because this block is per-CPU and does not clash with any of the
SSE-200 devices, we handle it with a has_cpu_pwrctrl flag like the
existing has_cachectrl, has_cpusectrl and has_cpuid, rather than
trying to add per-CPU-device support to the devinfo array handling code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-35-peter.maydell@linaro.org
| hw/arm/armsse.c | diffblobblamehistory | |
| include/hw/arm/armsse.h | diffblobblamehistory |