2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* This file contains implementation code for the RealView EB interrupt
11 * controller, MPCore distributed interrupt controller and ARMv7-M
12 * Nested Vectored Interrupt Controller.
13 * It is compiled in two ways:
14 * (1) as a standalone file to produce a sysbus device which is a GIC
15 * that can be used on the realview board and as one of the builtin
16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
17 * (2) by being directly #included into armv7m_nvic.c to produce the
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "gic_internal.h"
24 #include "qapi/error.h"
27 #include "qemu/module.h"
29 #include "sysemu/kvm.h"
31 /* #define DEBUG_GIC */
34 #define DEBUG_GIC_GATE 1
36 #define DEBUG_GIC_GATE 0
39 #define DPRINTF(fmt, ...) do { \
40 if (DEBUG_GIC_GATE) { \
41 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
45 static const uint8_t gic_id_11mpcore
[] = {
46 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
49 static const uint8_t gic_id_gicv1
[] = {
50 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
53 static const uint8_t gic_id_gicv2
[] = {
54 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
57 static inline int gic_get_current_cpu(GICState
*s
)
60 return current_cpu
->cpu_index
;
65 static inline int gic_get_current_vcpu(GICState
*s
)
67 return gic_get_current_cpu(s
) + GIC_NCPU
;
70 /* Return true if this GIC config has interrupt groups, which is
71 * true if we're a GICv2, or a GICv1 with the security extensions.
73 static inline bool gic_has_groups(GICState
*s
)
75 return s
->revision
== 2 || s
->security_extn
;
78 static inline bool gic_cpu_ns_access(GICState
*s
, int cpu
, MemTxAttrs attrs
)
80 return !gic_is_vcpu(cpu
) && s
->security_extn
&& !attrs
.secure
;
83 static inline void gic_get_best_irq(GICState
*s
, int cpu
,
84 int *best_irq
, int *best_prio
, int *group
)
92 for (irq
= 0; irq
< s
->num_irq
; irq
++) {
93 if (GIC_DIST_TEST_ENABLED(irq
, cm
) && gic_test_pending(s
, irq
, cm
) &&
94 (!GIC_DIST_TEST_ACTIVE(irq
, cm
)) &&
95 (irq
< GIC_INTERNAL
|| GIC_DIST_TARGET(irq
) & cm
)) {
96 if (GIC_DIST_GET_PRIORITY(irq
, cpu
) < *best_prio
) {
97 *best_prio
= GIC_DIST_GET_PRIORITY(irq
, cpu
);
103 if (*best_irq
< 1023) {
104 *group
= GIC_DIST_TEST_GROUP(*best_irq
, cm
);
108 static inline void gic_get_best_virq(GICState
*s
, int cpu
,
109 int *best_irq
, int *best_prio
, int *group
)
116 for (lr_idx
= 0; lr_idx
< s
->num_lrs
; lr_idx
++) {
117 uint32_t lr_entry
= s
->h_lr
[lr_idx
][cpu
];
118 int state
= GICH_LR_STATE(lr_entry
);
120 if (state
== GICH_LR_STATE_PENDING
) {
121 int prio
= GICH_LR_PRIORITY(lr_entry
);
123 if (prio
< *best_prio
) {
125 *best_irq
= GICH_LR_VIRT_ID(lr_entry
);
126 *group
= GICH_LR_GROUP(lr_entry
);
132 /* Return true if IRQ signaling is enabled for the given cpu and at least one
133 * of the given groups:
134 * - in the non-virt case, the distributor must be enabled for one of the
136 * - in the virt case, the virtual interface must be enabled.
137 * - in all cases, the (v)CPU interface must be enabled for one of the given
140 static inline bool gic_irq_signaling_enabled(GICState
*s
, int cpu
, bool virt
,
143 if (!virt
&& !(s
->ctlr
& group_mask
)) {
147 if (virt
&& !(s
->h_hcr
[cpu
] & R_GICH_HCR_EN_MASK
)) {
151 if (!(s
->cpu_ctlr
[cpu
] & group_mask
)) {
158 /* TODO: Many places that call this routine could be optimized. */
159 /* Update interrupt status after enabled or pending bits have been changed. */
160 static inline void gic_update_internal(GICState
*s
, bool virt
)
164 int irq_level
, fiq_level
;
167 qemu_irq
*irq_lines
= virt
? s
->parent_virq
: s
->parent_irq
;
168 qemu_irq
*fiq_lines
= virt
? s
->parent_vfiq
: s
->parent_fiq
;
170 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
171 cpu_iface
= virt
? (cpu
+ GIC_NCPU
) : cpu
;
173 s
->current_pending
[cpu_iface
] = 1023;
174 if (!gic_irq_signaling_enabled(s
, cpu
, virt
,
175 GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
)) {
176 qemu_irq_lower(irq_lines
[cpu
]);
177 qemu_irq_lower(fiq_lines
[cpu
]);
182 gic_get_best_virq(s
, cpu
, &best_irq
, &best_prio
, &group
);
184 gic_get_best_irq(s
, cpu
, &best_irq
, &best_prio
, &group
);
187 if (best_irq
!= 1023) {
188 trace_gic_update_bestirq(virt
? "vcpu" : "cpu", cpu
,
190 s
->priority_mask
[cpu_iface
],
191 s
->running_priority
[cpu_iface
]);
194 irq_level
= fiq_level
= 0;
196 if (best_prio
< s
->priority_mask
[cpu_iface
]) {
197 s
->current_pending
[cpu_iface
] = best_irq
;
198 if (best_prio
< s
->running_priority
[cpu_iface
]) {
199 if (gic_irq_signaling_enabled(s
, cpu
, virt
, 1 << group
)) {
201 s
->cpu_ctlr
[cpu_iface
] & GICC_CTLR_FIQ_EN
) {
202 DPRINTF("Raised pending FIQ %d (cpu %d)\n",
203 best_irq
, cpu_iface
);
205 trace_gic_update_set_irq(cpu
, virt
? "vfiq" : "fiq",
208 DPRINTF("Raised pending IRQ %d (cpu %d)\n",
209 best_irq
, cpu_iface
);
211 trace_gic_update_set_irq(cpu
, virt
? "virq" : "irq",
218 qemu_set_irq(irq_lines
[cpu
], irq_level
);
219 qemu_set_irq(fiq_lines
[cpu
], fiq_level
);
223 static void gic_update(GICState
*s
)
225 gic_update_internal(s
, false);
228 /* Return true if this LR is empty, i.e. the corresponding bit
231 static inline bool gic_lr_entry_is_free(uint32_t entry
)
233 return (GICH_LR_STATE(entry
) == GICH_LR_STATE_INVALID
)
234 && (GICH_LR_HW(entry
) || !GICH_LR_EOI(entry
));
237 /* Return true if this LR should trigger an EOI maintenance interrupt, i.e. the
238 * corrsponding bit in EISR is set.
240 static inline bool gic_lr_entry_is_eoi(uint32_t entry
)
242 return (GICH_LR_STATE(entry
) == GICH_LR_STATE_INVALID
)
243 && !GICH_LR_HW(entry
) && GICH_LR_EOI(entry
);
246 static inline void gic_extract_lr_info(GICState
*s
, int cpu
,
247 int *num_eoi
, int *num_valid
, int *num_pending
)
255 for (lr_idx
= 0; lr_idx
< s
->num_lrs
; lr_idx
++) {
256 uint32_t *entry
= &s
->h_lr
[lr_idx
][cpu
];
258 if (gic_lr_entry_is_eoi(*entry
)) {
262 if (GICH_LR_STATE(*entry
) != GICH_LR_STATE_INVALID
) {
266 if (GICH_LR_STATE(*entry
) == GICH_LR_STATE_PENDING
) {
272 static void gic_compute_misr(GICState
*s
, int cpu
)
275 int vcpu
= cpu
+ GIC_NCPU
;
277 int num_eoi
, num_valid
, num_pending
;
279 gic_extract_lr_info(s
, cpu
, &num_eoi
, &num_valid
, &num_pending
);
283 value
|= R_GICH_MISR_EOI_MASK
;
286 /* U: true if only 0 or 1 LR entry is valid */
287 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_UIE_MASK
) && (num_valid
< 2)) {
288 value
|= R_GICH_MISR_U_MASK
;
291 /* LRENP: EOICount is not 0 */
292 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_LRENPIE_MASK
) &&
293 ((s
->h_hcr
[cpu
] & R_GICH_HCR_EOICount_MASK
) != 0)) {
294 value
|= R_GICH_MISR_LRENP_MASK
;
297 /* NP: no pending interrupts */
298 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_NPIE_MASK
) && (num_pending
== 0)) {
299 value
|= R_GICH_MISR_NP_MASK
;
302 /* VGrp0E: group0 virq signaling enabled */
303 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP0EIE_MASK
) &&
304 (s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP0
)) {
305 value
|= R_GICH_MISR_VGrp0E_MASK
;
308 /* VGrp0D: group0 virq signaling disabled */
309 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP0DIE_MASK
) &&
310 !(s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP0
)) {
311 value
|= R_GICH_MISR_VGrp0D_MASK
;
314 /* VGrp1E: group1 virq signaling enabled */
315 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP1EIE_MASK
) &&
316 (s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP1
)) {
317 value
|= R_GICH_MISR_VGrp1E_MASK
;
320 /* VGrp1D: group1 virq signaling disabled */
321 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP1DIE_MASK
) &&
322 !(s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP1
)) {
323 value
|= R_GICH_MISR_VGrp1D_MASK
;
326 s
->h_misr
[cpu
] = value
;
329 static void gic_update_maintenance(GICState
*s
)
334 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
335 gic_compute_misr(s
, cpu
);
336 maint_level
= (s
->h_hcr
[cpu
] & R_GICH_HCR_EN_MASK
) && s
->h_misr
[cpu
];
338 trace_gic_update_maintenance_irq(cpu
, maint_level
);
339 qemu_set_irq(s
->maintenance_irq
[cpu
], maint_level
);
343 static void gic_update_virt(GICState
*s
)
345 gic_update_internal(s
, true);
346 gic_update_maintenance(s
);
349 static void gic_set_irq_11mpcore(GICState
*s
, int irq
, int level
,
353 GIC_DIST_SET_LEVEL(irq
, cm
);
354 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
) || GIC_DIST_TEST_ENABLED(irq
, cm
)) {
355 DPRINTF("Set %d pending mask %x\n", irq
, target
);
356 GIC_DIST_SET_PENDING(irq
, target
);
359 GIC_DIST_CLEAR_LEVEL(irq
, cm
);
363 static void gic_set_irq_generic(GICState
*s
, int irq
, int level
,
367 GIC_DIST_SET_LEVEL(irq
, cm
);
368 DPRINTF("Set %d pending mask %x\n", irq
, target
);
369 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
)) {
370 GIC_DIST_SET_PENDING(irq
, target
);
373 GIC_DIST_CLEAR_LEVEL(irq
, cm
);
377 /* Process a change in an external IRQ input. */
378 static void gic_set_irq(void *opaque
, int irq
, int level
)
380 /* Meaning of the 'irq' parameter:
381 * [0..N-1] : external interrupts
382 * [N..N+31] : PPI (internal) interrupts for CPU 0
383 * [N+32..N+63] : PPI (internal interrupts for CPU 1
386 GICState
*s
= (GICState
*)opaque
;
388 if (irq
< (s
->num_irq
- GIC_INTERNAL
)) {
389 /* The first external input line is internal interrupt 32. */
392 target
= GIC_DIST_TARGET(irq
);
395 irq
-= (s
->num_irq
- GIC_INTERNAL
);
396 cpu
= irq
/ GIC_INTERNAL
;
402 assert(irq
>= GIC_NR_SGIS
);
404 if (level
== GIC_DIST_TEST_LEVEL(irq
, cm
)) {
408 if (s
->revision
== REV_11MPCORE
) {
409 gic_set_irq_11mpcore(s
, irq
, level
, cm
, target
);
411 gic_set_irq_generic(s
, irq
, level
, cm
, target
);
413 trace_gic_set_irq(irq
, level
, cm
, target
);
418 static uint16_t gic_get_current_pending_irq(GICState
*s
, int cpu
,
421 uint16_t pending_irq
= s
->current_pending
[cpu
];
423 if (pending_irq
< GIC_MAXIRQ
&& gic_has_groups(s
)) {
424 int group
= gic_test_group(s
, pending_irq
, cpu
);
426 /* On a GIC without the security extensions, reading this register
427 * behaves in the same way as a secure access to a GIC with them.
429 bool secure
= !gic_cpu_ns_access(s
, cpu
, attrs
);
431 if (group
== 0 && !secure
) {
432 /* Group0 interrupts hidden from Non-secure access */
435 if (group
== 1 && secure
&& !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_ACK_CTL
)) {
436 /* Group1 interrupts only seen by Secure access if
445 static int gic_get_group_priority(GICState
*s
, int cpu
, int irq
)
447 /* Return the group priority of the specified interrupt
448 * (which is the top bits of its priority, with the number
449 * of bits masked determined by the applicable binary point register).
454 if (gic_has_groups(s
) &&
455 !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) &&
456 gic_test_group(s
, irq
, cpu
)) {
457 bpr
= s
->abpr
[cpu
] - 1;
463 /* a BPR of 0 means the group priority bits are [7:1];
464 * a BPR of 1 means they are [7:2], and so on down to
465 * a BPR of 7 meaning no group priority bits at all.
467 mask
= ~0U << ((bpr
& 7) + 1);
469 return gic_get_priority(s
, irq
, cpu
) & mask
;
472 static void gic_activate_irq(GICState
*s
, int cpu
, int irq
)
474 /* Set the appropriate Active Priority Register bit for this IRQ,
475 * and update the running priority.
477 int prio
= gic_get_group_priority(s
, cpu
, irq
);
478 int min_bpr
= gic_is_vcpu(cpu
) ? GIC_VIRT_MIN_BPR
: GIC_MIN_BPR
;
479 int preemption_level
= prio
>> (min_bpr
+ 1);
480 int regno
= preemption_level
/ 32;
481 int bitno
= preemption_level
% 32;
482 uint32_t *papr
= NULL
;
484 if (gic_is_vcpu(cpu
)) {
486 papr
= &s
->h_apr
[gic_get_vcpu_real_id(cpu
)];
487 } else if (gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
)) {
488 papr
= &s
->nsapr
[regno
][cpu
];
490 papr
= &s
->apr
[regno
][cpu
];
493 *papr
|= (1 << bitno
);
495 s
->running_priority
[cpu
] = prio
;
496 gic_set_active(s
, irq
, cpu
);
499 static int gic_get_prio_from_apr_bits(GICState
*s
, int cpu
)
501 /* Recalculate the current running priority for this CPU based
502 * on the set bits in the Active Priority Registers.
506 if (gic_is_vcpu(cpu
)) {
507 uint32_t apr
= s
->h_apr
[gic_get_vcpu_real_id(cpu
)];
509 return ctz32(apr
) << (GIC_VIRT_MIN_BPR
+ 1);
515 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
516 uint32_t apr
= s
->apr
[i
][cpu
] | s
->nsapr
[i
][cpu
];
520 return (i
* 32 + ctz32(apr
)) << (GIC_MIN_BPR
+ 1);
525 static void gic_drop_prio(GICState
*s
, int cpu
, int group
)
527 /* Drop the priority of the currently active interrupt in the
530 * Note that we can guarantee (because of the requirement to nest
531 * GICC_IAR reads [which activate an interrupt and raise priority]
532 * with GICC_EOIR writes [which drop the priority for the interrupt])
533 * that the interrupt we're being called for is the highest priority
534 * active interrupt, meaning that it has the lowest set bit in the
537 * If the guest does not honour the ordering constraints then the
538 * behaviour of the GIC is UNPREDICTABLE, which for us means that
539 * the values of the APR registers might become incorrect and the
540 * running priority will be wrong, so interrupts that should preempt
541 * might not do so, and interrupts that should not preempt might do so.
543 if (gic_is_vcpu(cpu
)) {
544 int rcpu
= gic_get_vcpu_real_id(cpu
);
546 if (s
->h_apr
[rcpu
]) {
547 /* Clear lowest set bit */
548 s
->h_apr
[rcpu
] &= s
->h_apr
[rcpu
] - 1;
553 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
554 uint32_t *papr
= group
? &s
->nsapr
[i
][cpu
] : &s
->apr
[i
][cpu
];
558 /* Clear lowest set bit */
564 s
->running_priority
[cpu
] = gic_get_prio_from_apr_bits(s
, cpu
);
567 static inline uint32_t gic_clear_pending_sgi(GICState
*s
, int irq
, int cpu
)
572 if (!gic_is_vcpu(cpu
)) {
573 /* Lookup the source CPU for the SGI and clear this in the
574 * sgi_pending map. Return the src and clear the overall pending
575 * state on this CPU if the SGI is not pending from any CPUs.
577 assert(s
->sgi_pending
[irq
][cpu
] != 0);
578 src
= ctz32(s
->sgi_pending
[irq
][cpu
]);
579 s
->sgi_pending
[irq
][cpu
] &= ~(1 << src
);
580 if (s
->sgi_pending
[irq
][cpu
] == 0) {
581 gic_clear_pending(s
, irq
, cpu
);
583 ret
= irq
| ((src
& 0x7) << 10);
585 uint32_t *lr_entry
= gic_get_lr_entry(s
, irq
, cpu
);
586 src
= GICH_LR_CPUID(*lr_entry
);
588 gic_clear_pending(s
, irq
, cpu
);
589 ret
= irq
| (src
<< 10);
595 uint32_t gic_acknowledge_irq(GICState
*s
, int cpu
, MemTxAttrs attrs
)
599 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
600 * for the case where this GIC supports grouping and the pending interrupt
601 * is in the wrong group.
603 irq
= gic_get_current_pending_irq(s
, cpu
, attrs
);
604 trace_gic_acknowledge_irq(gic_is_vcpu(cpu
) ? "vcpu" : "cpu",
605 gic_get_vcpu_real_id(cpu
), irq
);
607 if (irq
>= GIC_MAXIRQ
) {
608 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq
);
612 if (gic_get_priority(s
, irq
, cpu
) >= s
->running_priority
[cpu
]) {
613 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq
);
617 gic_activate_irq(s
, cpu
, irq
);
619 if (s
->revision
== REV_11MPCORE
) {
620 /* Clear pending flags for both level and edge triggered interrupts.
621 * Level triggered IRQs will be reasserted once they become inactive.
623 gic_clear_pending(s
, irq
, cpu
);
626 if (irq
< GIC_NR_SGIS
) {
627 ret
= gic_clear_pending_sgi(s
, irq
, cpu
);
629 gic_clear_pending(s
, irq
, cpu
);
634 if (gic_is_vcpu(cpu
)) {
639 DPRINTF("ACK %d\n", irq
);
643 void gic_dist_set_priority(GICState
*s
, int cpu
, int irq
, uint8_t val
,
646 if (s
->security_extn
&& !attrs
.secure
) {
647 if (!GIC_DIST_TEST_GROUP(irq
, (1 << cpu
))) {
648 return; /* Ignore Non-secure access of Group0 IRQ */
650 val
= 0x80 | (val
>> 1); /* Non-secure view */
653 if (irq
< GIC_INTERNAL
) {
654 s
->priority1
[irq
][cpu
] = val
;
656 s
->priority2
[(irq
) - GIC_INTERNAL
] = val
;
660 static uint32_t gic_dist_get_priority(GICState
*s
, int cpu
, int irq
,
663 uint32_t prio
= GIC_DIST_GET_PRIORITY(irq
, cpu
);
665 if (s
->security_extn
&& !attrs
.secure
) {
666 if (!GIC_DIST_TEST_GROUP(irq
, (1 << cpu
))) {
667 return 0; /* Non-secure access cannot read priority of Group0 IRQ */
669 prio
= (prio
<< 1) & 0xff; /* Non-secure view */
674 static void gic_set_priority_mask(GICState
*s
, int cpu
, uint8_t pmask
,
677 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
678 if (s
->priority_mask
[cpu
] & 0x80) {
679 /* Priority Mask in upper half */
680 pmask
= 0x80 | (pmask
>> 1);
682 /* Non-secure write ignored if priority mask is in lower half */
686 s
->priority_mask
[cpu
] = pmask
;
689 static uint32_t gic_get_priority_mask(GICState
*s
, int cpu
, MemTxAttrs attrs
)
691 uint32_t pmask
= s
->priority_mask
[cpu
];
693 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
695 /* Priority Mask in upper half, return Non-secure view */
696 pmask
= (pmask
<< 1) & 0xff;
698 /* Priority Mask in lower half, RAZ */
705 static uint32_t gic_get_cpu_control(GICState
*s
, int cpu
, MemTxAttrs attrs
)
707 uint32_t ret
= s
->cpu_ctlr
[cpu
];
709 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
710 /* Construct the NS banked view of GICC_CTLR from the correct
711 * bits of the S banked view. We don't need to move the bypass
712 * control bits because we don't implement that (IMPDEF) part
713 * of the GIC architecture.
715 ret
= (ret
& (GICC_CTLR_EN_GRP1
| GICC_CTLR_EOIMODE_NS
)) >> 1;
720 static void gic_set_cpu_control(GICState
*s
, int cpu
, uint32_t value
,
725 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
726 /* The NS view can only write certain bits in the register;
727 * the rest are unchanged
729 mask
= GICC_CTLR_EN_GRP1
;
730 if (s
->revision
== 2) {
731 mask
|= GICC_CTLR_EOIMODE_NS
;
733 s
->cpu_ctlr
[cpu
] &= ~mask
;
734 s
->cpu_ctlr
[cpu
] |= (value
<< 1) & mask
;
736 if (s
->revision
== 2) {
737 mask
= s
->security_extn
? GICC_CTLR_V2_S_MASK
: GICC_CTLR_V2_MASK
;
739 mask
= s
->security_extn
? GICC_CTLR_V1_S_MASK
: GICC_CTLR_V1_MASK
;
741 s
->cpu_ctlr
[cpu
] = value
& mask
;
743 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, "
744 "Group1 Interrupts %sabled\n", cpu
,
745 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP0
) ? "En" : "Dis",
746 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP1
) ? "En" : "Dis");
749 static uint8_t gic_get_running_priority(GICState
*s
, int cpu
, MemTxAttrs attrs
)
751 if ((s
->revision
!= REV_11MPCORE
) && (s
->running_priority
[cpu
] > 0xff)) {
756 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
757 if (s
->running_priority
[cpu
] & 0x80) {
758 /* Running priority in upper half of range: return the Non-secure
759 * view of the priority.
761 return s
->running_priority
[cpu
] << 1;
763 /* Running priority in lower half of range: RAZ */
767 return s
->running_priority
[cpu
];
771 /* Return true if we should split priority drop and interrupt deactivation,
772 * ie whether the relevant EOIMode bit is set.
774 static bool gic_eoi_split(GICState
*s
, int cpu
, MemTxAttrs attrs
)
776 if (s
->revision
!= 2) {
777 /* Before GICv2 prio-drop and deactivate are not separable */
780 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
781 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE_NS
;
783 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE
;
786 static void gic_deactivate_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
790 if (irq
>= GIC_MAXIRQ
|| (!gic_is_vcpu(cpu
) && irq
>= s
->num_irq
)) {
792 * This handles two cases:
793 * 1. If software writes the ID of a spurious interrupt [ie 1023]
794 * to the GICC_DIR, the GIC ignores that write.
795 * 2. If software writes the number of a non-existent interrupt
796 * this must be a subcase of "value written is not an active interrupt"
797 * and so this is UNPREDICTABLE. We choose to ignore it. For vCPUs,
798 * all IRQs potentially exist, so this limit does not apply.
803 if (!gic_eoi_split(s
, cpu
, attrs
)) {
804 /* This is UNPREDICTABLE; we choose to ignore it */
805 qemu_log_mask(LOG_GUEST_ERROR
,
806 "gic_deactivate_irq: GICC_DIR write when EOIMode clear");
810 if (gic_is_vcpu(cpu
) && !gic_virq_is_valid(s
, irq
, cpu
)) {
811 /* This vIRQ does not have an LR entry which is either active or
812 * pending and active. Increment EOICount and ignore the write.
814 int rcpu
= gic_get_vcpu_real_id(cpu
);
815 s
->h_hcr
[rcpu
] += 1 << R_GICH_HCR_EOICount_SHIFT
;
817 /* Update the virtual interface in case a maintenance interrupt should
824 group
= gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
);
826 if (gic_cpu_ns_access(s
, cpu
, attrs
) && !group
) {
827 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq
);
831 gic_clear_active(s
, irq
, cpu
);
834 static void gic_complete_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
839 DPRINTF("EOI %d\n", irq
);
840 if (gic_is_vcpu(cpu
)) {
841 /* The call to gic_prio_drop() will clear a bit in GICH_APR iff the
842 * running prio is < 0x100.
844 bool prio_drop
= s
->running_priority
[cpu
] < 0x100;
846 if (irq
>= GIC_MAXIRQ
) {
847 /* Ignore spurious interrupt */
851 gic_drop_prio(s
, cpu
, 0);
853 if (!gic_eoi_split(s
, cpu
, attrs
)) {
854 bool valid
= gic_virq_is_valid(s
, irq
, cpu
);
855 if (prio_drop
&& !valid
) {
856 /* We are in a situation where:
857 * - V_CTRL.EOIMode is false (no EOI split),
858 * - The call to gic_drop_prio() cleared a bit in GICH_APR,
859 * - This vIRQ does not have an LR entry which is either
860 * active or pending and active.
861 * In that case, we must increment EOICount.
863 int rcpu
= gic_get_vcpu_real_id(cpu
);
864 s
->h_hcr
[rcpu
] += 1 << R_GICH_HCR_EOICount_SHIFT
;
866 gic_clear_active(s
, irq
, cpu
);
874 if (irq
>= s
->num_irq
) {
875 /* This handles two cases:
876 * 1. If software writes the ID of a spurious interrupt [ie 1023]
877 * to the GICC_EOIR, the GIC ignores that write.
878 * 2. If software writes the number of a non-existent interrupt
879 * this must be a subcase of "value written does not match the last
880 * valid interrupt value read from the Interrupt Acknowledge
881 * register" and so this is UNPREDICTABLE. We choose to ignore it.
885 if (s
->running_priority
[cpu
] == 0x100) {
886 return; /* No active IRQ. */
889 if (s
->revision
== REV_11MPCORE
) {
890 /* Mark level triggered interrupts as pending if they are still
892 if (!GIC_DIST_TEST_EDGE_TRIGGER(irq
) && GIC_DIST_TEST_ENABLED(irq
, cm
)
893 && GIC_DIST_TEST_LEVEL(irq
, cm
)
894 && (GIC_DIST_TARGET(irq
) & cm
) != 0) {
895 DPRINTF("Set %d pending mask %x\n", irq
, cm
);
896 GIC_DIST_SET_PENDING(irq
, cm
);
900 group
= gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
);
902 if (gic_cpu_ns_access(s
, cpu
, attrs
) && !group
) {
903 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq
);
907 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1
908 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1,
909 * i.e. go ahead and complete the irq anyway.
912 gic_drop_prio(s
, cpu
, group
);
914 /* In GICv2 the guest can choose to split priority-drop and deactivate */
915 if (!gic_eoi_split(s
, cpu
, attrs
)) {
916 gic_clear_active(s
, irq
, cpu
);
921 static uint32_t gic_dist_readb(void *opaque
, hwaddr offset
, MemTxAttrs attrs
)
923 GICState
*s
= (GICState
*)opaque
;
931 cpu
= gic_get_current_cpu(s
);
933 if (offset
< 0x100) {
934 if (offset
== 0) { /* GICD_CTLR */
935 if (s
->security_extn
&& !attrs
.secure
) {
936 /* The NS bank of this register is just an alias of the
937 * EnableGrp1 bit in the S bank version.
939 return extract32(s
->ctlr
, 1, 1);
945 /* Interrupt Controller Type Register */
946 return ((s
->num_irq
/ 32) - 1)
947 | ((s
->num_cpu
- 1) << 5)
948 | (s
->security_extn
<< 10);
951 if (offset
>= 0x80) {
952 /* Interrupt Group Registers: these RAZ/WI if this is an NS
953 * access to a GIC with the security extensions, or if the GIC
954 * doesn't have groups at all.
957 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
958 /* Every byte offset holds 8 group status bits */
959 irq
= (offset
- 0x080) * 8;
960 if (irq
>= s
->num_irq
) {
963 for (i
= 0; i
< 8; i
++) {
964 if (GIC_DIST_TEST_GROUP(irq
+ i
, cm
)) {
972 } else if (offset
< 0x200) {
973 /* Interrupt Set/Clear Enable. */
975 irq
= (offset
- 0x100) * 8;
977 irq
= (offset
- 0x180) * 8;
978 if (irq
>= s
->num_irq
)
981 for (i
= 0; i
< 8; i
++) {
982 if (s
->security_extn
&& !attrs
.secure
&&
983 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
984 continue; /* Ignore Non-secure access of Group0 IRQ */
987 if (GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
991 } else if (offset
< 0x300) {
992 /* Interrupt Set/Clear Pending. */
994 irq
= (offset
- 0x200) * 8;
996 irq
= (offset
- 0x280) * 8;
997 if (irq
>= s
->num_irq
)
1000 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
1001 for (i
= 0; i
< 8; i
++) {
1002 if (s
->security_extn
&& !attrs
.secure
&&
1003 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1004 continue; /* Ignore Non-secure access of Group0 IRQ */
1007 if (gic_test_pending(s
, irq
+ i
, mask
)) {
1011 } else if (offset
< 0x400) {
1012 /* Interrupt Set/Clear Active. */
1013 if (offset
< 0x380) {
1014 irq
= (offset
- 0x300) * 8;
1015 } else if (s
->revision
== 2) {
1016 irq
= (offset
- 0x380) * 8;
1021 if (irq
>= s
->num_irq
)
1024 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
1025 for (i
= 0; i
< 8; i
++) {
1026 if (s
->security_extn
&& !attrs
.secure
&&
1027 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1028 continue; /* Ignore Non-secure access of Group0 IRQ */
1031 if (GIC_DIST_TEST_ACTIVE(irq
+ i
, mask
)) {
1035 } else if (offset
< 0x800) {
1036 /* Interrupt Priority. */
1037 irq
= (offset
- 0x400);
1038 if (irq
>= s
->num_irq
)
1040 res
= gic_dist_get_priority(s
, cpu
, irq
, attrs
);
1041 } else if (offset
< 0xc00) {
1042 /* Interrupt CPU Target. */
1043 if (s
->num_cpu
== 1 && s
->revision
!= REV_11MPCORE
) {
1044 /* For uniprocessor GICs these RAZ/WI */
1047 irq
= (offset
- 0x800);
1048 if (irq
>= s
->num_irq
) {
1051 if (irq
< 29 && s
->revision
== REV_11MPCORE
) {
1053 } else if (irq
< GIC_INTERNAL
) {
1056 res
= GIC_DIST_TARGET(irq
);
1059 } else if (offset
< 0xf00) {
1060 /* Interrupt Configuration. */
1061 irq
= (offset
- 0xc00) * 4;
1062 if (irq
>= s
->num_irq
)
1065 for (i
= 0; i
< 4; i
++) {
1066 if (s
->security_extn
&& !attrs
.secure
&&
1067 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1068 continue; /* Ignore Non-secure access of Group0 IRQ */
1071 if (GIC_DIST_TEST_MODEL(irq
+ i
)) {
1072 res
|= (1 << (i
* 2));
1074 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
+ i
)) {
1075 res
|= (2 << (i
* 2));
1078 } else if (offset
< 0xf10) {
1080 } else if (offset
< 0xf30) {
1081 if (s
->revision
== REV_11MPCORE
) {
1085 if (offset
< 0xf20) {
1086 /* GICD_CPENDSGIRn */
1087 irq
= (offset
- 0xf10);
1089 irq
= (offset
- 0xf20);
1090 /* GICD_SPENDSGIRn */
1093 if (s
->security_extn
&& !attrs
.secure
&&
1094 !GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
1095 res
= 0; /* Ignore Non-secure access of Group0 IRQ */
1097 res
= s
->sgi_pending
[irq
][cpu
];
1099 } else if (offset
< 0xfd0) {
1101 } else if (offset
< 0x1000) {
1105 switch (s
->revision
) {
1107 res
= gic_id_11mpcore
[(offset
- 0xfd0) >> 2];
1110 res
= gic_id_gicv1
[(offset
- 0xfd0) >> 2];
1113 res
= gic_id_gicv2
[(offset
- 0xfd0) >> 2];
1120 g_assert_not_reached();
1124 qemu_log_mask(LOG_GUEST_ERROR
,
1125 "gic_dist_readb: Bad offset %x\n", (int)offset
);
1129 static MemTxResult
gic_dist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
1130 unsigned size
, MemTxAttrs attrs
)
1134 *data
= gic_dist_readb(opaque
, offset
, attrs
);
1137 *data
= gic_dist_readb(opaque
, offset
, attrs
);
1138 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
1141 *data
= gic_dist_readb(opaque
, offset
, attrs
);
1142 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
1143 *data
|= gic_dist_readb(opaque
, offset
+ 2, attrs
) << 16;
1144 *data
|= gic_dist_readb(opaque
, offset
+ 3, attrs
) << 24;
1150 trace_gic_dist_read(offset
, size
, *data
);
1154 static void gic_dist_writeb(void *opaque
, hwaddr offset
,
1155 uint32_t value
, MemTxAttrs attrs
)
1157 GICState
*s
= (GICState
*)opaque
;
1162 cpu
= gic_get_current_cpu(s
);
1163 if (offset
< 0x100) {
1165 if (s
->security_extn
&& !attrs
.secure
) {
1166 /* NS version is just an alias of the S version's bit 1 */
1167 s
->ctlr
= deposit32(s
->ctlr
, 1, 1, value
);
1168 } else if (gic_has_groups(s
)) {
1169 s
->ctlr
= value
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
);
1171 s
->ctlr
= value
& GICD_CTLR_EN_GRP0
;
1173 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n",
1174 s
->ctlr
& GICD_CTLR_EN_GRP0
? "En" : "Dis",
1175 s
->ctlr
& GICD_CTLR_EN_GRP1
? "En" : "Dis");
1176 } else if (offset
< 4) {
1178 } else if (offset
>= 0x80) {
1179 /* Interrupt Group Registers: RAZ/WI for NS access to secure
1180 * GIC, or for GICs without groups.
1182 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
1183 /* Every byte offset holds 8 group status bits */
1184 irq
= (offset
- 0x80) * 8;
1185 if (irq
>= s
->num_irq
) {
1188 for (i
= 0; i
< 8; i
++) {
1189 /* Group bits are banked for private interrupts */
1190 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
1191 if (value
& (1 << i
)) {
1192 /* Group1 (Non-secure) */
1193 GIC_DIST_SET_GROUP(irq
+ i
, cm
);
1195 /* Group0 (Secure) */
1196 GIC_DIST_CLEAR_GROUP(irq
+ i
, cm
);
1203 } else if (offset
< 0x180) {
1204 /* Interrupt Set Enable. */
1205 irq
= (offset
- 0x100) * 8;
1206 if (irq
>= s
->num_irq
)
1208 if (irq
< GIC_NR_SGIS
) {
1212 for (i
= 0; i
< 8; i
++) {
1213 if (value
& (1 << i
)) {
1215 (irq
< GIC_INTERNAL
) ? (1 << cpu
)
1216 : GIC_DIST_TARGET(irq
+ i
);
1217 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
1219 if (s
->security_extn
&& !attrs
.secure
&&
1220 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1221 continue; /* Ignore Non-secure access of Group0 IRQ */
1224 if (!GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
1225 DPRINTF("Enabled IRQ %d\n", irq
+ i
);
1226 trace_gic_enable_irq(irq
+ i
);
1228 GIC_DIST_SET_ENABLED(irq
+ i
, cm
);
1229 /* If a raised level triggered IRQ enabled then mark
1231 if (GIC_DIST_TEST_LEVEL(irq
+ i
, mask
)
1232 && !GIC_DIST_TEST_EDGE_TRIGGER(irq
+ i
)) {
1233 DPRINTF("Set %d pending mask %x\n", irq
+ i
, mask
);
1234 GIC_DIST_SET_PENDING(irq
+ i
, mask
);
1238 } else if (offset
< 0x200) {
1239 /* Interrupt Clear Enable. */
1240 irq
= (offset
- 0x180) * 8;
1241 if (irq
>= s
->num_irq
)
1243 if (irq
< GIC_NR_SGIS
) {
1247 for (i
= 0; i
< 8; i
++) {
1248 if (value
& (1 << i
)) {
1249 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
1251 if (s
->security_extn
&& !attrs
.secure
&&
1252 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1253 continue; /* Ignore Non-secure access of Group0 IRQ */
1256 if (GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
1257 DPRINTF("Disabled IRQ %d\n", irq
+ i
);
1258 trace_gic_disable_irq(irq
+ i
);
1260 GIC_DIST_CLEAR_ENABLED(irq
+ i
, cm
);
1263 } else if (offset
< 0x280) {
1264 /* Interrupt Set Pending. */
1265 irq
= (offset
- 0x200) * 8;
1266 if (irq
>= s
->num_irq
)
1268 if (irq
< GIC_NR_SGIS
) {
1272 for (i
= 0; i
< 8; i
++) {
1273 if (value
& (1 << i
)) {
1274 if (s
->security_extn
&& !attrs
.secure
&&
1275 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1276 continue; /* Ignore Non-secure access of Group0 IRQ */
1279 GIC_DIST_SET_PENDING(irq
+ i
, GIC_DIST_TARGET(irq
+ i
));
1282 } else if (offset
< 0x300) {
1283 /* Interrupt Clear Pending. */
1284 irq
= (offset
- 0x280) * 8;
1285 if (irq
>= s
->num_irq
)
1287 if (irq
< GIC_NR_SGIS
) {
1291 for (i
= 0; i
< 8; i
++) {
1292 if (s
->security_extn
&& !attrs
.secure
&&
1293 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1294 continue; /* Ignore Non-secure access of Group0 IRQ */
1297 /* ??? This currently clears the pending bit for all CPUs, even
1298 for per-CPU interrupts. It's unclear whether this is the
1300 if (value
& (1 << i
)) {
1301 GIC_DIST_CLEAR_PENDING(irq
+ i
, ALL_CPU_MASK
);
1304 } else if (offset
< 0x380) {
1305 /* Interrupt Set Active. */
1306 if (s
->revision
!= 2) {
1310 irq
= (offset
- 0x300) * 8;
1311 if (irq
>= s
->num_irq
) {
1315 /* This register is banked per-cpu for PPIs */
1316 int cm
= irq
< GIC_INTERNAL
? (1 << cpu
) : ALL_CPU_MASK
;
1318 for (i
= 0; i
< 8; i
++) {
1319 if (s
->security_extn
&& !attrs
.secure
&&
1320 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1321 continue; /* Ignore Non-secure access of Group0 IRQ */
1324 if (value
& (1 << i
)) {
1325 GIC_DIST_SET_ACTIVE(irq
+ i
, cm
);
1328 } else if (offset
< 0x400) {
1329 /* Interrupt Clear Active. */
1330 if (s
->revision
!= 2) {
1334 irq
= (offset
- 0x380) * 8;
1335 if (irq
>= s
->num_irq
) {
1339 /* This register is banked per-cpu for PPIs */
1340 int cm
= irq
< GIC_INTERNAL
? (1 << cpu
) : ALL_CPU_MASK
;
1342 for (i
= 0; i
< 8; i
++) {
1343 if (s
->security_extn
&& !attrs
.secure
&&
1344 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1345 continue; /* Ignore Non-secure access of Group0 IRQ */
1348 if (value
& (1 << i
)) {
1349 GIC_DIST_CLEAR_ACTIVE(irq
+ i
, cm
);
1352 } else if (offset
< 0x800) {
1353 /* Interrupt Priority. */
1354 irq
= (offset
- 0x400);
1355 if (irq
>= s
->num_irq
)
1357 gic_dist_set_priority(s
, cpu
, irq
, value
, attrs
);
1358 } else if (offset
< 0xc00) {
1359 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
1360 * annoying exception of the 11MPCore's GIC.
1362 if (s
->num_cpu
!= 1 || s
->revision
== REV_11MPCORE
) {
1363 irq
= (offset
- 0x800);
1364 if (irq
>= s
->num_irq
) {
1367 if (irq
< 29 && s
->revision
== REV_11MPCORE
) {
1369 } else if (irq
< GIC_INTERNAL
) {
1370 value
= ALL_CPU_MASK
;
1372 s
->irq_target
[irq
] = value
& ALL_CPU_MASK
;
1374 } else if (offset
< 0xf00) {
1375 /* Interrupt Configuration. */
1376 irq
= (offset
- 0xc00) * 4;
1377 if (irq
>= s
->num_irq
)
1379 if (irq
< GIC_NR_SGIS
)
1381 for (i
= 0; i
< 4; i
++) {
1382 if (s
->security_extn
&& !attrs
.secure
&&
1383 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1384 continue; /* Ignore Non-secure access of Group0 IRQ */
1387 if (s
->revision
== REV_11MPCORE
) {
1388 if (value
& (1 << (i
* 2))) {
1389 GIC_DIST_SET_MODEL(irq
+ i
);
1391 GIC_DIST_CLEAR_MODEL(irq
+ i
);
1394 if (value
& (2 << (i
* 2))) {
1395 GIC_DIST_SET_EDGE_TRIGGER(irq
+ i
);
1397 GIC_DIST_CLEAR_EDGE_TRIGGER(irq
+ i
);
1400 } else if (offset
< 0xf10) {
1401 /* 0xf00 is only handled for 32-bit writes. */
1403 } else if (offset
< 0xf20) {
1404 /* GICD_CPENDSGIRn */
1405 if (s
->revision
== REV_11MPCORE
) {
1408 irq
= (offset
- 0xf10);
1410 if (!s
->security_extn
|| attrs
.secure
||
1411 GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
1412 s
->sgi_pending
[irq
][cpu
] &= ~value
;
1413 if (s
->sgi_pending
[irq
][cpu
] == 0) {
1414 GIC_DIST_CLEAR_PENDING(irq
, 1 << cpu
);
1417 } else if (offset
< 0xf30) {
1418 /* GICD_SPENDSGIRn */
1419 if (s
->revision
== REV_11MPCORE
) {
1422 irq
= (offset
- 0xf20);
1424 if (!s
->security_extn
|| attrs
.secure
||
1425 GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
1426 GIC_DIST_SET_PENDING(irq
, 1 << cpu
);
1427 s
->sgi_pending
[irq
][cpu
] |= value
;
1435 qemu_log_mask(LOG_GUEST_ERROR
,
1436 "gic_dist_writeb: Bad offset %x\n", (int)offset
);
1439 static void gic_dist_writew(void *opaque
, hwaddr offset
,
1440 uint32_t value
, MemTxAttrs attrs
)
1442 gic_dist_writeb(opaque
, offset
, value
& 0xff, attrs
);
1443 gic_dist_writeb(opaque
, offset
+ 1, value
>> 8, attrs
);
1446 static void gic_dist_writel(void *opaque
, hwaddr offset
,
1447 uint32_t value
, MemTxAttrs attrs
)
1449 GICState
*s
= (GICState
*)opaque
;
1450 if (offset
== 0xf00) {
1456 cpu
= gic_get_current_cpu(s
);
1457 irq
= value
& 0x3ff;
1458 switch ((value
>> 24) & 3) {
1460 mask
= (value
>> 16) & ALL_CPU_MASK
;
1463 mask
= ALL_CPU_MASK
^ (1 << cpu
);
1469 DPRINTF("Bad Soft Int target filter\n");
1470 mask
= ALL_CPU_MASK
;
1473 GIC_DIST_SET_PENDING(irq
, mask
);
1474 target_cpu
= ctz32(mask
);
1475 while (target_cpu
< GIC_NCPU
) {
1476 s
->sgi_pending
[irq
][target_cpu
] |= (1 << cpu
);
1477 mask
&= ~(1 << target_cpu
);
1478 target_cpu
= ctz32(mask
);
1483 gic_dist_writew(opaque
, offset
, value
& 0xffff, attrs
);
1484 gic_dist_writew(opaque
, offset
+ 2, value
>> 16, attrs
);
1487 static MemTxResult
gic_dist_write(void *opaque
, hwaddr offset
, uint64_t data
,
1488 unsigned size
, MemTxAttrs attrs
)
1490 trace_gic_dist_write(offset
, size
, data
);
1494 gic_dist_writeb(opaque
, offset
, data
, attrs
);
1497 gic_dist_writew(opaque
, offset
, data
, attrs
);
1500 gic_dist_writel(opaque
, offset
, data
, attrs
);
1507 static inline uint32_t gic_apr_ns_view(GICState
*s
, int cpu
, int regno
)
1509 /* Return the Nonsecure view of GICC_APR<regno>. This is the
1510 * second half of GICC_NSAPR.
1512 switch (GIC_MIN_BPR
) {
1515 return s
->nsapr
[regno
+ 2][cpu
];
1520 return s
->nsapr
[regno
+ 1][cpu
];
1525 return extract32(s
->nsapr
[0][cpu
], 16, 16);
1530 return extract32(s
->nsapr
[0][cpu
], 8, 8);
1534 g_assert_not_reached();
1539 static inline void gic_apr_write_ns_view(GICState
*s
, int cpu
, int regno
,
1542 /* Write the Nonsecure view of GICC_APR<regno>. */
1543 switch (GIC_MIN_BPR
) {
1546 s
->nsapr
[regno
+ 2][cpu
] = value
;
1551 s
->nsapr
[regno
+ 1][cpu
] = value
;
1556 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 16, 16, value
);
1561 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 8, 8, value
);
1565 g_assert_not_reached();
1569 static MemTxResult
gic_cpu_read(GICState
*s
, int cpu
, int offset
,
1570 uint64_t *data
, MemTxAttrs attrs
)
1573 case 0x00: /* Control */
1574 *data
= gic_get_cpu_control(s
, cpu
, attrs
);
1576 case 0x04: /* Priority mask */
1577 *data
= gic_get_priority_mask(s
, cpu
, attrs
);
1579 case 0x08: /* Binary Point */
1580 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1581 if (s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) {
1582 /* NS view of BPR when CBPR is 1 */
1583 *data
= MIN(s
->bpr
[cpu
] + 1, 7);
1585 /* BPR is banked. Non-secure copy stored in ABPR. */
1586 *data
= s
->abpr
[cpu
];
1589 *data
= s
->bpr
[cpu
];
1592 case 0x0c: /* Acknowledge */
1593 *data
= gic_acknowledge_irq(s
, cpu
, attrs
);
1595 case 0x14: /* Running Priority */
1596 *data
= gic_get_running_priority(s
, cpu
, attrs
);
1598 case 0x18: /* Highest Pending Interrupt */
1599 *data
= gic_get_current_pending_irq(s
, cpu
, attrs
);
1601 case 0x1c: /* Aliased Binary Point */
1602 /* GIC v2, no security: ABPR
1603 * GIC v1, no security: not implemented (RAZ/WI)
1604 * With security extensions, secure access: ABPR (alias of NS BPR)
1605 * With security extensions, nonsecure access: RAZ/WI
1607 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1610 *data
= s
->abpr
[cpu
];
1613 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1615 int regno
= (offset
- 0xd0) / 4;
1616 int nr_aprs
= gic_is_vcpu(cpu
) ? GIC_VIRT_NR_APRS
: GIC_NR_APRS
;
1618 if (regno
>= nr_aprs
|| s
->revision
!= 2) {
1620 } else if (gic_is_vcpu(cpu
)) {
1621 *data
= s
->h_apr
[gic_get_vcpu_real_id(cpu
)];
1622 } else if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1623 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1624 *data
= gic_apr_ns_view(s
, regno
, cpu
);
1626 *data
= s
->apr
[regno
][cpu
];
1630 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1632 int regno
= (offset
- 0xe0) / 4;
1634 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2 || !gic_has_groups(s
) ||
1635 gic_cpu_ns_access(s
, cpu
, attrs
) || gic_is_vcpu(cpu
)) {
1638 *data
= s
->nsapr
[regno
][cpu
];
1643 qemu_log_mask(LOG_GUEST_ERROR
,
1644 "gic_cpu_read: Bad offset %x\n", (int)offset
);
1649 trace_gic_cpu_read(gic_is_vcpu(cpu
) ? "vcpu" : "cpu",
1650 gic_get_vcpu_real_id(cpu
), offset
, *data
);
1654 static MemTxResult
gic_cpu_write(GICState
*s
, int cpu
, int offset
,
1655 uint32_t value
, MemTxAttrs attrs
)
1657 trace_gic_cpu_write(gic_is_vcpu(cpu
) ? "vcpu" : "cpu",
1658 gic_get_vcpu_real_id(cpu
), offset
, value
);
1661 case 0x00: /* Control */
1662 gic_set_cpu_control(s
, cpu
, value
, attrs
);
1664 case 0x04: /* Priority mask */
1665 gic_set_priority_mask(s
, cpu
, value
, attrs
);
1667 case 0x08: /* Binary Point */
1668 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1669 if (s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) {
1670 /* WI when CBPR is 1 */
1673 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1676 int min_bpr
= gic_is_vcpu(cpu
) ? GIC_VIRT_MIN_BPR
: GIC_MIN_BPR
;
1677 s
->bpr
[cpu
] = MAX(value
& 0x7, min_bpr
);
1680 case 0x10: /* End Of Interrupt */
1681 gic_complete_irq(s
, cpu
, value
& 0x3ff, attrs
);
1683 case 0x1c: /* Aliased Binary Point */
1684 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1685 /* unimplemented, or NS access: RAZ/WI */
1688 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1691 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1693 int regno
= (offset
- 0xd0) / 4;
1694 int nr_aprs
= gic_is_vcpu(cpu
) ? GIC_VIRT_NR_APRS
: GIC_NR_APRS
;
1696 if (regno
>= nr_aprs
|| s
->revision
!= 2) {
1699 if (gic_is_vcpu(cpu
)) {
1700 s
->h_apr
[gic_get_vcpu_real_id(cpu
)] = value
;
1701 } else if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1702 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1703 gic_apr_write_ns_view(s
, regno
, cpu
, value
);
1705 s
->apr
[regno
][cpu
] = value
;
1709 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1711 int regno
= (offset
- 0xe0) / 4;
1713 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1716 if (gic_is_vcpu(cpu
)) {
1719 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1722 s
->nsapr
[regno
][cpu
] = value
;
1727 gic_deactivate_irq(s
, cpu
, value
& 0x3ff, attrs
);
1730 qemu_log_mask(LOG_GUEST_ERROR
,
1731 "gic_cpu_write: Bad offset %x\n", (int)offset
);
1735 if (gic_is_vcpu(cpu
)) {
1744 /* Wrappers to read/write the GIC CPU interface for the current CPU */
1745 static MemTxResult
gic_thiscpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1746 unsigned size
, MemTxAttrs attrs
)
1748 GICState
*s
= (GICState
*)opaque
;
1749 return gic_cpu_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1752 static MemTxResult
gic_thiscpu_write(void *opaque
, hwaddr addr
,
1753 uint64_t value
, unsigned size
,
1756 GICState
*s
= (GICState
*)opaque
;
1757 return gic_cpu_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1760 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
1761 * These just decode the opaque pointer into GICState* + cpu id.
1763 static MemTxResult
gic_do_cpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1764 unsigned size
, MemTxAttrs attrs
)
1766 GICState
**backref
= (GICState
**)opaque
;
1767 GICState
*s
= *backref
;
1768 int id
= (backref
- s
->backref
);
1769 return gic_cpu_read(s
, id
, addr
, data
, attrs
);
1772 static MemTxResult
gic_do_cpu_write(void *opaque
, hwaddr addr
,
1773 uint64_t value
, unsigned size
,
1776 GICState
**backref
= (GICState
**)opaque
;
1777 GICState
*s
= *backref
;
1778 int id
= (backref
- s
->backref
);
1779 return gic_cpu_write(s
, id
, addr
, value
, attrs
);
1782 static MemTxResult
gic_thisvcpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1783 unsigned size
, MemTxAttrs attrs
)
1785 GICState
*s
= (GICState
*)opaque
;
1787 return gic_cpu_read(s
, gic_get_current_vcpu(s
), addr
, data
, attrs
);
1790 static MemTxResult
gic_thisvcpu_write(void *opaque
, hwaddr addr
,
1791 uint64_t value
, unsigned size
,
1794 GICState
*s
= (GICState
*)opaque
;
1796 return gic_cpu_write(s
, gic_get_current_vcpu(s
), addr
, value
, attrs
);
1799 static uint32_t gic_compute_eisr(GICState
*s
, int cpu
, int lr_start
)
1804 for (lr_idx
= lr_start
; lr_idx
< s
->num_lrs
; lr_idx
++) {
1805 uint32_t *entry
= &s
->h_lr
[lr_idx
][cpu
];
1806 ret
= deposit32(ret
, lr_idx
- lr_start
, 1,
1807 gic_lr_entry_is_eoi(*entry
));
1813 static uint32_t gic_compute_elrsr(GICState
*s
, int cpu
, int lr_start
)
1818 for (lr_idx
= lr_start
; lr_idx
< s
->num_lrs
; lr_idx
++) {
1819 uint32_t *entry
= &s
->h_lr
[lr_idx
][cpu
];
1820 ret
= deposit32(ret
, lr_idx
- lr_start
, 1,
1821 gic_lr_entry_is_free(*entry
));
1827 static void gic_vmcr_write(GICState
*s
, uint32_t value
, MemTxAttrs attrs
)
1829 int vcpu
= gic_get_current_vcpu(s
);
1835 ctlr
= FIELD_EX32(value
, GICH_VMCR
, VMCCtlr
);
1836 abpr
= FIELD_EX32(value
, GICH_VMCR
, VMABP
);
1837 bpr
= FIELD_EX32(value
, GICH_VMCR
, VMBP
);
1838 prio_mask
= FIELD_EX32(value
, GICH_VMCR
, VMPriMask
) << 3;
1840 gic_set_cpu_control(s
, vcpu
, ctlr
, attrs
);
1841 s
->abpr
[vcpu
] = MAX(abpr
, GIC_VIRT_MIN_ABPR
);
1842 s
->bpr
[vcpu
] = MAX(bpr
, GIC_VIRT_MIN_BPR
);
1843 gic_set_priority_mask(s
, vcpu
, prio_mask
, attrs
);
1846 static MemTxResult
gic_hyp_read(void *opaque
, int cpu
, hwaddr addr
,
1847 uint64_t *data
, MemTxAttrs attrs
)
1849 GICState
*s
= ARM_GIC(opaque
);
1850 int vcpu
= cpu
+ GIC_NCPU
;
1853 case A_GICH_HCR
: /* Hypervisor Control */
1854 *data
= s
->h_hcr
[cpu
];
1857 case A_GICH_VTR
: /* VGIC Type */
1858 *data
= FIELD_DP32(0, GICH_VTR
, ListRegs
, s
->num_lrs
- 1);
1859 *data
= FIELD_DP32(*data
, GICH_VTR
, PREbits
,
1860 GIC_VIRT_MAX_GROUP_PRIO_BITS
- 1);
1861 *data
= FIELD_DP32(*data
, GICH_VTR
, PRIbits
,
1862 (7 - GIC_VIRT_MIN_BPR
) - 1);
1865 case A_GICH_VMCR
: /* Virtual Machine Control */
1866 *data
= FIELD_DP32(0, GICH_VMCR
, VMCCtlr
,
1867 extract32(s
->cpu_ctlr
[vcpu
], 0, 10));
1868 *data
= FIELD_DP32(*data
, GICH_VMCR
, VMABP
, s
->abpr
[vcpu
]);
1869 *data
= FIELD_DP32(*data
, GICH_VMCR
, VMBP
, s
->bpr
[vcpu
]);
1870 *data
= FIELD_DP32(*data
, GICH_VMCR
, VMPriMask
,
1871 extract32(s
->priority_mask
[vcpu
], 3, 5));
1874 case A_GICH_MISR
: /* Maintenance Interrupt Status */
1875 *data
= s
->h_misr
[cpu
];
1878 case A_GICH_EISR0
: /* End of Interrupt Status 0 and 1 */
1880 *data
= gic_compute_eisr(s
, cpu
, (addr
- A_GICH_EISR0
) * 8);
1883 case A_GICH_ELRSR0
: /* Empty List Status 0 and 1 */
1885 *data
= gic_compute_elrsr(s
, cpu
, (addr
- A_GICH_ELRSR0
) * 8);
1888 case A_GICH_APR
: /* Active Priorities */
1889 *data
= s
->h_apr
[cpu
];
1892 case A_GICH_LR0
... A_GICH_LR63
: /* List Registers */
1894 int lr_idx
= (addr
- A_GICH_LR0
) / 4;
1896 if (lr_idx
> s
->num_lrs
) {
1899 *data
= s
->h_lr
[lr_idx
][cpu
];
1905 qemu_log_mask(LOG_GUEST_ERROR
,
1906 "gic_hyp_read: Bad offset %" HWADDR_PRIx
"\n", addr
);
1910 trace_gic_hyp_read(addr
, *data
);
1914 static MemTxResult
gic_hyp_write(void *opaque
, int cpu
, hwaddr addr
,
1915 uint64_t value
, MemTxAttrs attrs
)
1917 GICState
*s
= ARM_GIC(opaque
);
1918 int vcpu
= cpu
+ GIC_NCPU
;
1920 trace_gic_hyp_write(addr
, value
);
1923 case A_GICH_HCR
: /* Hypervisor Control */
1924 s
->h_hcr
[cpu
] = value
& GICH_HCR_MASK
;
1927 case A_GICH_VMCR
: /* Virtual Machine Control */
1928 gic_vmcr_write(s
, value
, attrs
);
1931 case A_GICH_APR
: /* Active Priorities */
1932 s
->h_apr
[cpu
] = value
;
1933 s
->running_priority
[vcpu
] = gic_get_prio_from_apr_bits(s
, vcpu
);
1936 case A_GICH_LR0
... A_GICH_LR63
: /* List Registers */
1938 int lr_idx
= (addr
- A_GICH_LR0
) / 4;
1940 if (lr_idx
> s
->num_lrs
) {
1944 s
->h_lr
[lr_idx
][cpu
] = value
& GICH_LR_MASK
;
1945 trace_gic_lr_entry(cpu
, lr_idx
, s
->h_lr
[lr_idx
][cpu
]);
1950 qemu_log_mask(LOG_GUEST_ERROR
,
1951 "gic_hyp_write: Bad offset %" HWADDR_PRIx
"\n", addr
);
1959 static MemTxResult
gic_thiscpu_hyp_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1960 unsigned size
, MemTxAttrs attrs
)
1962 GICState
*s
= (GICState
*)opaque
;
1964 return gic_hyp_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1967 static MemTxResult
gic_thiscpu_hyp_write(void *opaque
, hwaddr addr
,
1968 uint64_t value
, unsigned size
,
1971 GICState
*s
= (GICState
*)opaque
;
1973 return gic_hyp_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1976 static MemTxResult
gic_do_hyp_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1977 unsigned size
, MemTxAttrs attrs
)
1979 GICState
**backref
= (GICState
**)opaque
;
1980 GICState
*s
= *backref
;
1981 int id
= (backref
- s
->backref
);
1983 return gic_hyp_read(s
, id
, addr
, data
, attrs
);
1986 static MemTxResult
gic_do_hyp_write(void *opaque
, hwaddr addr
,
1987 uint64_t value
, unsigned size
,
1990 GICState
**backref
= (GICState
**)opaque
;
1991 GICState
*s
= *backref
;
1992 int id
= (backref
- s
->backref
);
1994 return gic_hyp_write(s
, id
+ GIC_NCPU
, addr
, value
, attrs
);
1998 static const MemoryRegionOps gic_ops
[2] = {
2000 .read_with_attrs
= gic_dist_read
,
2001 .write_with_attrs
= gic_dist_write
,
2002 .endianness
= DEVICE_NATIVE_ENDIAN
,
2005 .read_with_attrs
= gic_thiscpu_read
,
2006 .write_with_attrs
= gic_thiscpu_write
,
2007 .endianness
= DEVICE_NATIVE_ENDIAN
,
2011 static const MemoryRegionOps gic_cpu_ops
= {
2012 .read_with_attrs
= gic_do_cpu_read
,
2013 .write_with_attrs
= gic_do_cpu_write
,
2014 .endianness
= DEVICE_NATIVE_ENDIAN
,
2017 static const MemoryRegionOps gic_virt_ops
[2] = {
2019 .read_with_attrs
= gic_thiscpu_hyp_read
,
2020 .write_with_attrs
= gic_thiscpu_hyp_write
,
2021 .endianness
= DEVICE_NATIVE_ENDIAN
,
2024 .read_with_attrs
= gic_thisvcpu_read
,
2025 .write_with_attrs
= gic_thisvcpu_write
,
2026 .endianness
= DEVICE_NATIVE_ENDIAN
,
2030 static const MemoryRegionOps gic_viface_ops
= {
2031 .read_with_attrs
= gic_do_hyp_read
,
2032 .write_with_attrs
= gic_do_hyp_write
,
2033 .endianness
= DEVICE_NATIVE_ENDIAN
,
2036 static void arm_gic_realize(DeviceState
*dev
, Error
**errp
)
2038 /* Device instance realize function for the GIC sysbus device */
2040 GICState
*s
= ARM_GIC(dev
);
2041 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
2042 ARMGICClass
*agc
= ARM_GIC_GET_CLASS(s
);
2043 Error
*local_err
= NULL
;
2045 agc
->parent_realize(dev
, &local_err
);
2047 error_propagate(errp
, local_err
);
2051 if (kvm_enabled() && !kvm_arm_supports_user_irq()) {
2052 error_setg(errp
, "KVM with user space irqchip only works when the "
2053 "host kernel supports KVM_CAP_ARM_USER_IRQ");
2057 /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if
2058 * enabled, virtualization extensions related interfaces (main virtual
2059 * interface (s->vifaceiomem[0]) and virtual CPU interface).
2061 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
, gic_virt_ops
);
2063 /* Extra core-specific regions for the CPU interfaces. This is
2064 * necessary for "franken-GIC" implementations, for example on
2066 * NB that the memory region size of 0x100 applies for the 11MPCore
2067 * and also cores following the GIC v1 spec (ie A9).
2068 * GIC v2 defines a larger memory region (0x1000) so this will need
2069 * to be extended when we implement A15.
2071 for (i
= 0; i
< s
->num_cpu
; i
++) {
2073 memory_region_init_io(&s
->cpuiomem
[i
+1], OBJECT(s
), &gic_cpu_ops
,
2074 &s
->backref
[i
], "gic_cpu", 0x100);
2075 sysbus_init_mmio(sbd
, &s
->cpuiomem
[i
+1]);
2078 /* Extra core-specific regions for virtual interfaces. This is required by
2079 * the GICv2 specification.
2082 for (i
= 0; i
< s
->num_cpu
; i
++) {
2083 memory_region_init_io(&s
->vifaceiomem
[i
+ 1], OBJECT(s
),
2084 &gic_viface_ops
, &s
->backref
[i
],
2085 "gic_viface", 0x200);
2086 sysbus_init_mmio(sbd
, &s
->vifaceiomem
[i
+ 1]);
2092 static void arm_gic_class_init(ObjectClass
*klass
, void *data
)
2094 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2095 ARMGICClass
*agc
= ARM_GIC_CLASS(klass
);
2097 device_class_set_parent_realize(dc
, arm_gic_realize
, &agc
->parent_realize
);
2100 static const TypeInfo arm_gic_info
= {
2101 .name
= TYPE_ARM_GIC
,
2102 .parent
= TYPE_ARM_GIC_COMMON
,
2103 .instance_size
= sizeof(GICState
),
2104 .class_init
= arm_gic_class_init
,
2105 .class_size
= sizeof(ARMGICClass
),
2108 static void arm_gic_register_types(void)
2110 type_register_static(&arm_gic_info
);
2113 type_init(arm_gic_register_types
)