2 * APIC support - common bits of emulated and KVM kernel model
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 * Copyright (c) 2011 Jan Kiszka, Siemens AG
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qemu/module.h"
24 #include "qapi/error.h"
26 #include "qapi/visitor.h"
27 #include "hw/i386/apic.h"
28 #include "hw/i386/apic_internal.h"
30 #include "sysemu/hax.h"
31 #include "sysemu/kvm.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/sysbus.h"
34 #include "migration/vmstate.h"
36 static int apic_irq_delivered
;
37 bool apic_report_tpr_access
;
39 void cpu_set_apic_base(DeviceState
*dev
, uint64_t val
)
41 trace_cpu_set_apic_base(val
);
44 APICCommonState
*s
= APIC_COMMON(dev
);
45 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
46 /* switching to x2APIC, reset possibly modified xAPIC ID */
47 if (!(s
->apicbase
& MSR_IA32_APICBASE_EXTD
) &&
48 (val
& MSR_IA32_APICBASE_EXTD
)) {
49 s
->id
= s
->initial_apic_id
;
51 info
->set_base(s
, val
);
55 uint64_t cpu_get_apic_base(DeviceState
*dev
)
58 APICCommonState
*s
= APIC_COMMON(dev
);
59 trace_cpu_get_apic_base((uint64_t)s
->apicbase
);
62 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP
);
63 return MSR_IA32_APICBASE_BSP
;
67 void cpu_set_apic_tpr(DeviceState
*dev
, uint8_t val
)
70 APICCommonClass
*info
;
77 info
= APIC_COMMON_GET_CLASS(s
);
79 info
->set_tpr(s
, val
);
82 uint8_t cpu_get_apic_tpr(DeviceState
*dev
)
85 APICCommonClass
*info
;
92 info
= APIC_COMMON_GET_CLASS(s
);
94 return info
->get_tpr(s
);
97 void apic_enable_tpr_access_reporting(DeviceState
*dev
, bool enable
)
99 APICCommonState
*s
= APIC_COMMON(dev
);
100 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
102 apic_report_tpr_access
= enable
;
103 if (info
->enable_tpr_reporting
) {
104 info
->enable_tpr_reporting(s
, enable
);
108 void apic_enable_vapic(DeviceState
*dev
, hwaddr paddr
)
110 APICCommonState
*s
= APIC_COMMON(dev
);
111 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
113 s
->vapic_paddr
= paddr
;
114 info
->vapic_base_update(s
);
117 void apic_handle_tpr_access_report(DeviceState
*dev
, target_ulong ip
,
120 APICCommonState
*s
= APIC_COMMON(dev
);
122 vapic_report_tpr_access(s
->vapic
, CPU(s
->cpu
), ip
, access
);
125 void apic_report_irq_delivered(int delivered
)
127 apic_irq_delivered
+= delivered
;
129 trace_apic_report_irq_delivered(apic_irq_delivered
);
132 void apic_reset_irq_delivered(void)
134 /* Copy this into a local variable to encourage gcc to emit a plain
135 * register for a sys/sdt.h marker. For details on this workaround, see:
136 * https://sourceware.org/bugzilla/show_bug.cgi?id=13296
138 volatile int a_i_d
= apic_irq_delivered
;
139 trace_apic_reset_irq_delivered(a_i_d
);
141 apic_irq_delivered
= 0;
144 int apic_get_irq_delivered(void)
146 trace_apic_get_irq_delivered(apic_irq_delivered
);
148 return apic_irq_delivered
;
151 void apic_deliver_nmi(DeviceState
*dev
)
153 APICCommonState
*s
= APIC_COMMON(dev
);
154 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
156 info
->external_nmi(s
);
159 bool apic_next_timer(APICCommonState
*s
, int64_t current_time
)
163 /* We need to store the timer state separately to support APIC
164 * implementations that maintain a non-QEMU timer, e.g. inside the
165 * host kernel. This open-coded state allows us to migrate between
167 s
->timer_expiry
= -1;
169 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_MASKED
) {
173 d
= (current_time
- s
->initial_count_load_time
) >> s
->count_shift
;
175 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
176 if (!s
->initial_count
) {
179 d
= ((d
/ ((uint64_t)s
->initial_count
+ 1)) + 1) *
180 ((uint64_t)s
->initial_count
+ 1);
182 if (d
>= s
->initial_count
) {
185 d
= (uint64_t)s
->initial_count
+ 1;
187 s
->next_time
= s
->initial_count_load_time
+ (d
<< s
->count_shift
);
188 s
->timer_expiry
= s
->next_time
;
192 void apic_init_reset(DeviceState
*dev
)
195 APICCommonClass
*info
;
201 s
= APIC_COMMON(dev
);
203 s
->spurious_vec
= 0xff;
206 memset(s
->isr
, 0, sizeof(s
->isr
));
207 memset(s
->tmr
, 0, sizeof(s
->tmr
));
208 memset(s
->irr
, 0, sizeof(s
->irr
));
209 for (i
= 0; i
< APIC_LVT_NB
; i
++) {
210 s
->lvt
[i
] = APIC_LVT_MASKED
;
213 memset(s
->icr
, 0, sizeof(s
->icr
));
216 s
->initial_count
= 0;
217 s
->initial_count_load_time
= 0;
219 s
->wait_for_sipi
= !cpu_is_bsp(s
->cpu
);
224 s
->timer_expiry
= -1;
226 info
= APIC_COMMON_GET_CLASS(s
);
232 void apic_designate_bsp(DeviceState
*dev
, bool bsp
)
238 APICCommonState
*s
= APIC_COMMON(dev
);
240 s
->apicbase
|= MSR_IA32_APICBASE_BSP
;
242 s
->apicbase
&= ~MSR_IA32_APICBASE_BSP
;
246 static void apic_reset_common(DeviceState
*dev
)
248 APICCommonState
*s
= APIC_COMMON(dev
);
249 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
252 bsp
= s
->apicbase
& MSR_IA32_APICBASE_BSP
;
253 s
->apicbase
= APIC_DEFAULT_ADDRESS
| bsp
| MSR_IA32_APICBASE_ENABLE
;
254 s
->id
= s
->initial_apic_id
;
256 apic_reset_irq_delivered();
259 info
->vapic_base_update(s
);
261 apic_init_reset(dev
);
264 static const VMStateDescription vmstate_apic_common
;
266 static void apic_common_realize(DeviceState
*dev
, Error
**errp
)
268 APICCommonState
*s
= APIC_COMMON(dev
);
269 APICCommonClass
*info
;
270 static DeviceState
*vapic
;
271 uint32_t instance_id
= s
->initial_apic_id
;
273 /* Normally initial APIC ID should be no more than hundreds */
274 assert(instance_id
!= VMSTATE_INSTANCE_ID_ANY
);
276 info
= APIC_COMMON_GET_CLASS(s
);
277 info
->realize(dev
, errp
);
279 /* Note: We need at least 1M to map the VAPIC option ROM */
280 if (!vapic
&& s
->vapic_control
& VAPIC_ENABLE_MASK
&&
281 !hax_enabled() && ram_size
>= 1024 * 1024) {
282 vapic
= sysbus_create_simple("kvmvapic", -1, NULL
);
285 if (apic_report_tpr_access
&& info
->enable_tpr_reporting
) {
286 info
->enable_tpr_reporting(s
, true);
289 if (s
->legacy_instance_id
) {
290 instance_id
= VMSTATE_INSTANCE_ID_ANY
;
292 vmstate_register_with_alias_id(NULL
, instance_id
, &vmstate_apic_common
,
296 static void apic_common_unrealize(DeviceState
*dev
, Error
**errp
)
298 APICCommonState
*s
= APIC_COMMON(dev
);
299 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
301 vmstate_unregister(NULL
, &vmstate_apic_common
, s
);
302 info
->unrealize(dev
, errp
);
304 if (apic_report_tpr_access
&& info
->enable_tpr_reporting
) {
305 info
->enable_tpr_reporting(s
, false);
309 static int apic_pre_load(void *opaque
)
311 APICCommonState
*s
= APIC_COMMON(opaque
);
313 /* The default is !cpu_is_bsp(s->cpu), but the common value is 0
314 * so that's what apic_common_sipi_needed checks for. Reset to
315 * the value that is assumed when the apic_sipi subsection is
318 s
->wait_for_sipi
= 0;
322 static int apic_dispatch_pre_save(void *opaque
)
324 APICCommonState
*s
= APIC_COMMON(opaque
);
325 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
327 if (info
->pre_save
) {
334 static int apic_dispatch_post_load(void *opaque
, int version_id
)
336 APICCommonState
*s
= APIC_COMMON(opaque
);
337 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
339 if (info
->post_load
) {
345 static bool apic_common_sipi_needed(void *opaque
)
347 APICCommonState
*s
= APIC_COMMON(opaque
);
348 return s
->wait_for_sipi
!= 0;
351 static const VMStateDescription vmstate_apic_common_sipi
= {
354 .minimum_version_id
= 1,
355 .needed
= apic_common_sipi_needed
,
356 .fields
= (VMStateField
[]) {
357 VMSTATE_INT32(sipi_vector
, APICCommonState
),
358 VMSTATE_INT32(wait_for_sipi
, APICCommonState
),
359 VMSTATE_END_OF_LIST()
363 static const VMStateDescription vmstate_apic_common
= {
366 .minimum_version_id
= 3,
367 .pre_load
= apic_pre_load
,
368 .pre_save
= apic_dispatch_pre_save
,
369 .post_load
= apic_dispatch_post_load
,
370 .fields
= (VMStateField
[]) {
371 VMSTATE_UINT32(apicbase
, APICCommonState
),
372 VMSTATE_UINT8(id
, APICCommonState
),
373 VMSTATE_UINT8(arb_id
, APICCommonState
),
374 VMSTATE_UINT8(tpr
, APICCommonState
),
375 VMSTATE_UINT32(spurious_vec
, APICCommonState
),
376 VMSTATE_UINT8(log_dest
, APICCommonState
),
377 VMSTATE_UINT8(dest_mode
, APICCommonState
),
378 VMSTATE_UINT32_ARRAY(isr
, APICCommonState
, 8),
379 VMSTATE_UINT32_ARRAY(tmr
, APICCommonState
, 8),
380 VMSTATE_UINT32_ARRAY(irr
, APICCommonState
, 8),
381 VMSTATE_UINT32_ARRAY(lvt
, APICCommonState
, APIC_LVT_NB
),
382 VMSTATE_UINT32(esr
, APICCommonState
),
383 VMSTATE_UINT32_ARRAY(icr
, APICCommonState
, 2),
384 VMSTATE_UINT32(divide_conf
, APICCommonState
),
385 VMSTATE_INT32(count_shift
, APICCommonState
),
386 VMSTATE_UINT32(initial_count
, APICCommonState
),
387 VMSTATE_INT64(initial_count_load_time
, APICCommonState
),
388 VMSTATE_INT64(next_time
, APICCommonState
),
389 VMSTATE_INT64(timer_expiry
,
390 APICCommonState
), /* open-coded timer state */
391 VMSTATE_END_OF_LIST()
393 .subsections
= (const VMStateDescription
*[]) {
394 &vmstate_apic_common_sipi
,
399 static Property apic_properties_common
[] = {
400 DEFINE_PROP_UINT8("version", APICCommonState
, version
, 0x14),
401 DEFINE_PROP_BIT("vapic", APICCommonState
, vapic_control
, VAPIC_ENABLE_BIT
,
403 DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState
, legacy_instance_id
,
405 DEFINE_PROP_END_OF_LIST(),
408 static void apic_common_get_id(Object
*obj
, Visitor
*v
, const char *name
,
409 void *opaque
, Error
**errp
)
411 APICCommonState
*s
= APIC_COMMON(obj
);
414 value
= s
->apicbase
& MSR_IA32_APICBASE_EXTD
? s
->initial_apic_id
: s
->id
;
415 visit_type_uint32(v
, name
, &value
, errp
);
418 static void apic_common_set_id(Object
*obj
, Visitor
*v
, const char *name
,
419 void *opaque
, Error
**errp
)
421 APICCommonState
*s
= APIC_COMMON(obj
);
422 DeviceState
*dev
= DEVICE(obj
);
423 Error
*local_err
= NULL
;
427 qdev_prop_set_after_realize(dev
, name
, errp
);
431 visit_type_uint32(v
, name
, &value
, &local_err
);
433 error_propagate(errp
, local_err
);
437 s
->initial_apic_id
= value
;
438 s
->id
= (uint8_t)value
;
441 static void apic_common_initfn(Object
*obj
)
443 APICCommonState
*s
= APIC_COMMON(obj
);
445 s
->id
= s
->initial_apic_id
= -1;
446 object_property_add(obj
, "id", "uint32",
448 apic_common_set_id
, NULL
, NULL
, NULL
);
451 static void apic_common_class_init(ObjectClass
*klass
, void *data
)
453 DeviceClass
*dc
= DEVICE_CLASS(klass
);
455 dc
->reset
= apic_reset_common
;
456 dc
->props
= apic_properties_common
;
457 dc
->realize
= apic_common_realize
;
458 dc
->unrealize
= apic_common_unrealize
;
460 * Reason: APIC and CPU need to be wired up by
461 * x86_cpu_apic_create()
463 dc
->user_creatable
= false;
466 static const TypeInfo apic_common_type
= {
467 .name
= TYPE_APIC_COMMON
,
468 .parent
= TYPE_DEVICE
,
469 .instance_size
= sizeof(APICCommonState
),
470 .instance_init
= apic_common_initfn
,
471 .class_size
= sizeof(APICCommonClass
),
472 .class_init
= apic_common_class_init
,
476 static void apic_common_register_types(void)
478 type_register_static(&apic_common_type
);
481 type_init(apic_common_register_types
)