hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block
[qemu/ar7.git] / tcg / mips / tcg-target-con-str.h
blobe4b2965c7247c752330880c437673276dc6c8c26
1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Define MIPS target-specific operand constraints.
4 * Copyright (c) 2021 Linaro
5 */
7 /*
8 * Define constraint letters for register sets:
9 * REGS(letter, register_mask)
11 REGS('r', ALL_GENERAL_REGS)
12 REGS('L', ALL_QLOAD_REGS)
13 REGS('S', ALL_QSTORE_REGS)
16 * Define constraint letters for constants:
17 * CONST(letter, TCG_CT_CONST_* bit set)
19 CONST('I', TCG_CT_CONST_U16)
20 CONST('J', TCG_CT_CONST_S16)
21 CONST('K', TCG_CT_CONST_P2M1)
22 CONST('N', TCG_CT_CONST_N16)
23 CONST('W', TCG_CT_CONST_WSZ)
24 CONST('Z', TCG_CT_CONST_ZERO)