target/riscv/csr.c

   1 /*
   2  * RISC-V Control and Status Registers.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/log.h"
  22 #include "cpu.h"
  23 #include "qemu/main-loop.h"
  24 #include "exec/exec-all.h"
  25
  26 /* CSR function table public API */
  27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
  28 {
  29     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
  30 }
  31
  32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
  33 {
  34     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
  35 }
  36
  37 /* Predicates */
  38 static int fs(CPURISCVState *env, int csrno)
  39 {
  40 #if !defined(CONFIG_USER_ONLY)
  41     /* loose check condition for fcsr in vector extension */
  42     if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
  43         return 0;
  44     }
  45     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
  46         return -RISCV_EXCP_ILLEGAL_INST;
  47     }
  48 #endif
  49     return 0;
  50 }
  51
  52 static int vs(CPURISCVState *env, int csrno)
  53 {
  54     if (env->misa & RVV) {
  55         return 0;
  56     }
  57     return -RISCV_EXCP_ILLEGAL_INST;
  58 }
  59
  60 static int ctr(CPURISCVState *env, int csrno)
  61 {
  62 #if !defined(CONFIG_USER_ONLY)
  63     CPUState *cs = env_cpu(env);
  64     RISCVCPU *cpu = RISCV_CPU(cs);
  65
  66     if (!cpu->cfg.ext_counters) {
  67         /* The Counters extensions is not enabled */
  68         return -RISCV_EXCP_ILLEGAL_INST;
  69     }
  70
  71     if (riscv_cpu_virt_enabled(env)) {
  72         switch (csrno) {
  73         case CSR_CYCLE:
  74             if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
  75                 get_field(env->mcounteren, HCOUNTEREN_CY)) {
  76                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  77             }
  78             break;
  79         case CSR_TIME:
  80             if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
  81                 get_field(env->mcounteren, HCOUNTEREN_TM)) {
  82                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  83             }
  84             break;
  85         case CSR_INSTRET:
  86             if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
  87                 get_field(env->mcounteren, HCOUNTEREN_IR)) {
  88                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  89             }
  90             break;
  91         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
  92             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
  93                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
  94                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  95             }
  96             break;
  97         }
  98         if (riscv_cpu_is_32bit(env)) {
  99             switch (csrno) {
 100             case CSR_CYCLEH:
 101                 if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
 102                     get_field(env->mcounteren, HCOUNTEREN_CY)) {
 103                     return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 104                 }
 105                 break;
 106             case CSR_TIMEH:
 107                 if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
 108                     get_field(env->mcounteren, HCOUNTEREN_TM)) {
 109                     return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 110                 }
 111                 break;
 112             case CSR_INSTRETH:
 113                 if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
 114                     get_field(env->mcounteren, HCOUNTEREN_IR)) {
 115                     return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 116                 }
 117                 break;
 118             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
 119                 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
 120                     get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
 121                     return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 122                 }
 123                 break;
 124             }
 125         }
 126     }
 127 #endif
 128     return 0;
 129 }
 130
 131 static int ctr32(CPURISCVState *env, int csrno)
 132 {
 133     if (!riscv_cpu_is_32bit(env)) {
 134         return -RISCV_EXCP_ILLEGAL_INST;
 135     }
 136
 137     return ctr(env, csrno);
 138 }
 139
 140 #if !defined(CONFIG_USER_ONLY)
 141 static int any(CPURISCVState *env, int csrno)
 142 {
 143     return 0;
 144 }
 145
 146 static int any32(CPURISCVState *env, int csrno)
 147 {
 148     if (!riscv_cpu_is_32bit(env)) {
 149         return -RISCV_EXCP_ILLEGAL_INST;
 150     }
 151
 152     return any(env, csrno);
 153
 154 }
 155
 156 static int smode(CPURISCVState *env, int csrno)
 157 {
 158     return -!riscv_has_ext(env, RVS);
 159 }
 160
 161 static int hmode(CPURISCVState *env, int csrno)
 162 {
 163     if (riscv_has_ext(env, RVS) &&
 164         riscv_has_ext(env, RVH)) {
 165         /* Hypervisor extension is supported */
 166         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 167             env->priv == PRV_M) {
 168             return 0;
 169         } else {
 170             return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 171         }
 172     }
 173
 174     return -RISCV_EXCP_ILLEGAL_INST;
 175 }
 176
 177 static int hmode32(CPURISCVState *env, int csrno)
 178 {
 179     if (!riscv_cpu_is_32bit(env)) {
 180         return 0;
 181     }
 182
 183     return hmode(env, csrno);
 184
 185 }
 186
 187 static int pmp(CPURISCVState *env, int csrno)
 188 {
 189     return -!riscv_feature(env, RISCV_FEATURE_PMP);
 190 }
 191 #endif
 192
 193 /* User Floating-Point CSRs */
 194 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
 195 {
 196 #if !defined(CONFIG_USER_ONLY)
 197     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 198         return -RISCV_EXCP_ILLEGAL_INST;
 199     }
 200 #endif
 201     *val = riscv_cpu_get_fflags(env);
 202     return 0;
 203 }
 204
 205 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
 206 {
 207 #if !defined(CONFIG_USER_ONLY)
 208     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 209         return -RISCV_EXCP_ILLEGAL_INST;
 210     }
 211     env->mstatus |= MSTATUS_FS;
 212 #endif
 213     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
 214     return 0;
 215 }
 216
 217 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
 218 {
 219 #if !defined(CONFIG_USER_ONLY)
 220     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 221         return -RISCV_EXCP_ILLEGAL_INST;
 222     }
 223 #endif
 224     *val = env->frm;
 225     return 0;
 226 }
 227
 228 static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
 229 {
 230 #if !defined(CONFIG_USER_ONLY)
 231     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 232         return -RISCV_EXCP_ILLEGAL_INST;
 233     }
 234     env->mstatus |= MSTATUS_FS;
 235 #endif
 236     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
 237     return 0;
 238 }
 239
 240 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
 241 {
 242 #if !defined(CONFIG_USER_ONLY)
 243     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 244         return -RISCV_EXCP_ILLEGAL_INST;
 245     }
 246 #endif
 247     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
 248         | (env->frm << FSR_RD_SHIFT);
 249     if (vs(env, csrno) >= 0) {
 250         *val |= (env->vxrm << FSR_VXRM_SHIFT)
 251                 | (env->vxsat << FSR_VXSAT_SHIFT);
 252     }
 253     return 0;
 254 }
 255
 256 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
 257 {
 258 #if !defined(CONFIG_USER_ONLY)
 259     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 260         return -RISCV_EXCP_ILLEGAL_INST;
 261     }
 262     env->mstatus |= MSTATUS_FS;
 263 #endif
 264     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 265     if (vs(env, csrno) >= 0) {
 266         env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
 267         env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
 268     }
 269     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
 270     return 0;
 271 }
 272
 273 static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
 274 {
 275     *val = env->vtype;
 276     return 0;
 277 }
 278
 279 static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
 280 {
 281     *val = env->vl;
 282     return 0;
 283 }
 284
 285 static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
 286 {
 287     *val = env->vxrm;
 288     return 0;
 289 }
 290
 291 static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
 292 {
 293     env->vxrm = val;
 294     return 0;
 295 }
 296
 297 static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
 298 {
 299     *val = env->vxsat;
 300     return 0;
 301 }
 302
 303 static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
 304 {
 305     env->vxsat = val;
 306     return 0;
 307 }
 308
 309 static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
 310 {
 311     *val = env->vstart;
 312     return 0;
 313 }
 314
 315 static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
 316 {
 317     env->vstart = val;
 318     return 0;
 319 }
 320
 321 /* User Timers and Counters */
 322 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
 323 {
 324 #if !defined(CONFIG_USER_ONLY)
 325     if (icount_enabled()) {
 326         *val = icount_get();
 327     } else {
 328         *val = cpu_get_host_ticks();
 329     }
 330 #else
 331     *val = cpu_get_host_ticks();
 332 #endif
 333     return 0;
 334 }
 335
 336 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
 337 {
 338 #if !defined(CONFIG_USER_ONLY)
 339     if (icount_enabled()) {
 340         *val = icount_get() >> 32;
 341     } else {
 342         *val = cpu_get_host_ticks() >> 32;
 343     }
 344 #else
 345     *val = cpu_get_host_ticks() >> 32;
 346 #endif
 347     return 0;
 348 }
 349
 350 #if defined(CONFIG_USER_ONLY)
 351 static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
 352 {
 353     *val = cpu_get_host_ticks();
 354     return 0;
 355 }
 356
 357 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
 358 {
 359     *val = cpu_get_host_ticks() >> 32;
 360     return 0;
 361 }
 362
 363 #else /* CONFIG_USER_ONLY */
 364
 365 static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
 366 {
 367     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 368
 369     if (!env->rdtime_fn) {
 370         return -RISCV_EXCP_ILLEGAL_INST;
 371     }
 372
 373     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
 374     return 0;
 375 }
 376
 377 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
 378 {
 379     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 380
 381     if (!env->rdtime_fn) {
 382         return -RISCV_EXCP_ILLEGAL_INST;
 383     }
 384
 385     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
 386     return 0;
 387 }
 388
 389 /* Machine constants */
 390
 391 #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
 392 #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
 393 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
 394
 395 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
 396                                            VS_MODE_INTERRUPTS;
 397 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
 398                                      VS_MODE_INTERRUPTS;
 399 static const target_ulong delegable_excps =
 400     (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) |
 401     (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) |
 402     (1ULL << (RISCV_EXCP_ILLEGAL_INST)) |
 403     (1ULL << (RISCV_EXCP_BREAKPOINT)) |
 404     (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) |
 405     (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) |
 406     (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) |
 407     (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) |
 408     (1ULL << (RISCV_EXCP_U_ECALL)) |
 409     (1ULL << (RISCV_EXCP_S_ECALL)) |
 410     (1ULL << (RISCV_EXCP_VS_ECALL)) |
 411     (1ULL << (RISCV_EXCP_M_ECALL)) |
 412     (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) |
 413     (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) |
 414     (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) |
 415     (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
 416     (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
 417     (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
 418     (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
 419 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
 420     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
 421     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
 422 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
 423 static const target_ulong hip_writable_mask = MIP_VSSIP;
 424 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 425 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 426
 427 static const char valid_vm_1_10_32[16] = {
 428     [VM_1_10_MBARE] = 1,
 429     [VM_1_10_SV32] = 1
 430 };
 431
 432 static const char valid_vm_1_10_64[16] = {
 433     [VM_1_10_MBARE] = 1,
 434     [VM_1_10_SV39] = 1,
 435     [VM_1_10_SV48] = 1,
 436     [VM_1_10_SV57] = 1
 437 };
 438
 439 /* Machine Information Registers */
 440 static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
 441 {
 442     return *val = 0;
 443 }
 444
 445 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val)
 446 {
 447     *val = env->mhartid;
 448     return 0;
 449 }
 450
 451 /* Machine Trap Setup */
 452 static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
 453 {
 454     *val = env->mstatus;
 455     return 0;
 456 }
 457
 458 static int validate_vm(CPURISCVState *env, target_ulong vm)
 459 {
 460     if (riscv_cpu_is_32bit(env)) {
 461         return valid_vm_1_10_32[vm & 0xf];
 462     } else {
 463         return valid_vm_1_10_64[vm & 0xf];
 464     }
 465 }
 466
 467 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
 468 {
 469     uint64_t mstatus = env->mstatus;
 470     uint64_t mask = 0;
 471     int dirty;
 472
 473     /* flush tlb on mstatus fields that affect VM */
 474     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
 475             MSTATUS_MPRV | MSTATUS_SUM)) {
 476         tlb_flush(env_cpu(env));
 477     }
 478     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
 479         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
 480         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
 481         MSTATUS_TW;
 482
 483     if (!riscv_cpu_is_32bit(env)) {
 484         /*
 485          * RV32: MPV and GVA are not in mstatus. The current plan is to
 486          * add them to mstatush. For now, we just don't support it.
 487          */
 488         mask |= MSTATUS_MPV | MSTATUS_GVA;
 489     }
 490
 491     mstatus = (mstatus & ~mask) | (val & mask);
 492
 493     dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
 494             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
 495     mstatus = set_field(mstatus, MSTATUS_SD, dirty);
 496     env->mstatus = mstatus;
 497
 498     return 0;
 499 }
 500
 501 static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
 502 {
 503     *val = env->mstatus >> 32;
 504     return 0;
 505 }
 506
 507 static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
 508 {
 509     uint64_t valh = (uint64_t)val << 32;
 510     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
 511
 512     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
 513         tlb_flush(env_cpu(env));
 514     }
 515
 516     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
 517
 518     return 0;
 519 }
 520
 521 static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
 522 {
 523     *val = env->misa;
 524     return 0;
 525 }
 526
 527 static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
 528 {
 529     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
 530         /* drop write to misa */
 531         return 0;
 532     }
 533
 534     /* 'I' or 'E' must be present */
 535     if (!(val & (RVI | RVE))) {
 536         /* It is not, drop write to misa */
 537         return 0;
 538     }
 539
 540     /* 'E' excludes all other extensions */
 541     if (val & RVE) {
 542         /* when we support 'E' we can do "val = RVE;" however
 543          * for now we just drop writes if 'E' is present.
 544          */
 545         return 0;
 546     }
 547
 548     /* Mask extensions that are not supported by this hart */
 549     val &= env->misa_mask;
 550
 551     /* Mask extensions that are not supported by QEMU */
 552     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 553
 554     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
 555     if ((val & RVD) && !(val & RVF)) {
 556         val &= ~RVD;
 557     }
 558
 559     /* Suppress 'C' if next instruction is not aligned
 560      * TODO: this should check next_pc
 561      */
 562     if ((val & RVC) && (GETPC() & ~3) != 0) {
 563         val &= ~RVC;
 564     }
 565
 566     /* misa.MXL writes are not supported by QEMU */
 567     val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
 568
 569     /* flush translation cache */
 570     if (val != env->misa) {
 571         tb_flush(env_cpu(env));
 572     }
 573
 574     env->misa = val;
 575
 576     return 0;
 577 }
 578
 579 static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
 580 {
 581     *val = env->medeleg;
 582     return 0;
 583 }
 584
 585 static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val)
 586 {
 587     env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
 588     return 0;
 589 }
 590
 591 static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
 592 {
 593     *val = env->mideleg;
 594     return 0;
 595 }
 596
 597 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
 598 {
 599     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
 600     if (riscv_has_ext(env, RVH)) {
 601         env->mideleg |= VS_MODE_INTERRUPTS;
 602     }
 603     return 0;
 604 }
 605
 606 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)
 607 {
 608     *val = env->mie;
 609     return 0;
 610 }
 611
 612 static int write_mie(CPURISCVState *env, int csrno, target_ulong val)
 613 {
 614     env->mie = (env->mie & ~all_ints) | (val & all_ints);
 615     return 0;
 616 }
 617
 618 static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
 619 {
 620     *val = env->mtvec;
 621     return 0;
 622 }
 623
 624 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
 625 {
 626     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
 627     if ((val & 3) < 2) {
 628         env->mtvec = val;
 629     } else {
 630         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
 631     }
 632     return 0;
 633 }
 634
 635 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
 636 {
 637     *val = env->mcounteren;
 638     return 0;
 639 }
 640
 641 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
 642 {
 643     env->mcounteren = val;
 644     return 0;
 645 }
 646
 647 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 648 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
 649 {
 650     if (env->priv_ver < PRIV_VERSION_1_11_0) {
 651         return -RISCV_EXCP_ILLEGAL_INST;
 652     }
 653     *val = env->mcounteren;
 654     return 0;
 655 }
 656
 657 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 658 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
 659 {
 660     if (env->priv_ver < PRIV_VERSION_1_11_0) {
 661         return -RISCV_EXCP_ILLEGAL_INST;
 662     }
 663     env->mcounteren = val;
 664     return 0;
 665 }
 666
 667 /* Machine Trap Handling */
 668 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
 669 {
 670     *val = env->mscratch;
 671     return 0;
 672 }
 673
 674 static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val)
 675 {
 676     env->mscratch = val;
 677     return 0;
 678 }
 679
 680 static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val)
 681 {
 682     *val = env->mepc;
 683     return 0;
 684 }
 685
 686 static int write_mepc(CPURISCVState *env, int csrno, target_ulong val)
 687 {
 688     env->mepc = val;
 689     return 0;
 690 }
 691
 692 static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val)
 693 {
 694     *val = env->mcause;
 695     return 0;
 696 }
 697
 698 static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
 699 {
 700     env->mcause = val;
 701     return 0;
 702 }
 703
 704 static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
 705 {
 706     *val = env->mbadaddr;
 707     return 0;
 708 }
 709
 710 static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
 711 {
 712     env->mbadaddr = val;
 713     return 0;
 714 }
 715
 716 static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 717                    target_ulong new_value, target_ulong write_mask)
 718 {
 719     RISCVCPU *cpu = env_archcpu(env);
 720     /* Allow software control of delegable interrupts not claimed by hardware */
 721     target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
 722     uint32_t old_mip;
 723
 724     if (mask) {
 725         old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
 726     } else {
 727         old_mip = env->mip;
 728     }
 729
 730     if (ret_value) {
 731         *ret_value = old_mip;
 732     }
 733
 734     return 0;
 735 }
 736
 737 /* Supervisor Trap Setup */
 738 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
 739 {
 740     target_ulong mask = (sstatus_v1_10_mask);
 741     *val = env->mstatus & mask;
 742     return 0;
 743 }
 744
 745 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
 746 {
 747     target_ulong mask = (sstatus_v1_10_mask);
 748     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
 749     return write_mstatus(env, CSR_MSTATUS, newval);
 750 }
 751
 752 static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
 753 {
 754     /* Shift the VS bits to their S bit location in vsie */
 755     *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
 756     return 0;
 757 }
 758
 759 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
 760 {
 761     if (riscv_cpu_virt_enabled(env)) {
 762         read_vsie(env, CSR_VSIE, val);
 763     } else {
 764         *val = env->mie & env->mideleg;
 765     }
 766     return 0;
 767 }
 768
 769 static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
 770 {
 771     /* Shift the S bits to their VS bit location in mie */
 772     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
 773                           ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
 774     return write_mie(env, CSR_MIE, newval);
 775 }
 776
 777 static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
 778 {
 779     if (riscv_cpu_virt_enabled(env)) {
 780         write_vsie(env, CSR_VSIE, val);
 781     } else {
 782         target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
 783                               (val & S_MODE_INTERRUPTS);
 784         write_mie(env, CSR_MIE, newval);
 785     }
 786
 787     return 0;
 788 }
 789
 790 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
 791 {
 792     *val = env->stvec;
 793     return 0;
 794 }
 795
 796 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
 797 {
 798     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
 799     if ((val & 3) < 2) {
 800         env->stvec = val;
 801     } else {
 802         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
 803     }
 804     return 0;
 805 }
 806
 807 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
 808 {
 809     *val = env->scounteren;
 810     return 0;
 811 }
 812
 813 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
 814 {
 815     env->scounteren = val;
 816     return 0;
 817 }
 818
 819 /* Supervisor Trap Handling */
 820 static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val)
 821 {
 822     *val = env->sscratch;
 823     return 0;
 824 }
 825
 826 static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val)
 827 {
 828     env->sscratch = val;
 829     return 0;
 830 }
 831
 832 static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val)
 833 {
 834     *val = env->sepc;
 835     return 0;
 836 }
 837
 838 static int write_sepc(CPURISCVState *env, int csrno, target_ulong val)
 839 {
 840     env->sepc = val;
 841     return 0;
 842 }
 843
 844 static int read_scause(CPURISCVState *env, int csrno, target_ulong *val)
 845 {
 846     *val = env->scause;
 847     return 0;
 848 }
 849
 850 static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
 851 {
 852     env->scause = val;
 853     return 0;
 854 }
 855
 856 static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
 857 {
 858     *val = env->sbadaddr;
 859     return 0;
 860 }
 861
 862 static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
 863 {
 864     env->sbadaddr = val;
 865     return 0;
 866 }
 867
 868 static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 869                     target_ulong new_value, target_ulong write_mask)
 870 {
 871     /* Shift the S bits to their VS bit location in mip */
 872     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
 873                       (write_mask << 1) & vsip_writable_mask & env->hideleg);
 874     *ret_value &= VS_MODE_INTERRUPTS;
 875     /* Shift the VS bits to their S bit location in vsip */
 876     *ret_value >>= 1;
 877     return ret;
 878 }
 879
 880 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 881                    target_ulong new_value, target_ulong write_mask)
 882 {
 883     int ret;
 884
 885     if (riscv_cpu_virt_enabled(env)) {
 886         ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
 887     } else {
 888         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
 889                       write_mask & env->mideleg & sip_writable_mask);
 890     }
 891
 892     *ret_value &= env->mideleg;
 893     return ret;
 894 }
 895
 896 /* Supervisor Protection and Translation */
 897 static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
 898 {
 899     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
 900         *val = 0;
 901         return 0;
 902     }
 903
 904     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
 905         return -RISCV_EXCP_ILLEGAL_INST;
 906     } else {
 907         *val = env->satp;
 908     }
 909
 910     return 0;
 911 }
 912
 913 static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
 914 {
 915     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
 916         return 0;
 917     }
 918     if (validate_vm(env, get_field(val, SATP_MODE)) &&
 919         ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
 920     {
 921         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
 922             return -RISCV_EXCP_ILLEGAL_INST;
 923         } else {
 924             if ((val ^ env->satp) & SATP_ASID) {
 925                 tlb_flush(env_cpu(env));
 926             }
 927             env->satp = val;
 928         }
 929     }
 930     return 0;
 931 }
 932
 933 /* Hypervisor Extensions */
 934 static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
 935 {
 936     *val = env->hstatus;
 937     if (!riscv_cpu_is_32bit(env)) {
 938         /* We only support 64-bit VSXL */
 939         *val = set_field(*val, HSTATUS_VSXL, 2);
 940     }
 941     /* We only support little endian */
 942     *val = set_field(*val, HSTATUS_VSBE, 0);
 943     return 0;
 944 }
 945
 946 static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
 947 {
 948     env->hstatus = val;
 949     if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
 950         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
 951     }
 952     if (get_field(val, HSTATUS_VSBE) != 0) {
 953         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
 954     }
 955     return 0;
 956 }
 957
 958 static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
 959 {
 960     *val = env->hedeleg;
 961     return 0;
 962 }
 963
 964 static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
 965 {
 966     env->hedeleg = val;
 967     return 0;
 968 }
 969
 970 static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
 971 {
 972     *val = env->hideleg;
 973     return 0;
 974 }
 975
 976 static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
 977 {
 978     env->hideleg = val;
 979     return 0;
 980 }
 981
 982 static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 983                    target_ulong new_value, target_ulong write_mask)
 984 {
 985     int ret = rmw_mip(env, 0, ret_value, new_value,
 986                       write_mask & hvip_writable_mask);
 987
 988     *ret_value &= hvip_writable_mask;
 989
 990     return ret;
 991 }
 992
 993 static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 994                    target_ulong new_value, target_ulong write_mask)
 995 {
 996     int ret = rmw_mip(env, 0, ret_value, new_value,
 997                       write_mask & hip_writable_mask);
 998
 999     *ret_value &= hip_writable_mask;
1000
1001     return ret;
1002 }
1003
1004 static int read_hie(CPURISCVState *env, int csrno, target_ulong *val)
1005 {
1006     *val = env->mie & VS_MODE_INTERRUPTS;
1007     return 0;
1008 }
1009
1010 static int write_hie(CPURISCVState *env, int csrno, target_ulong val)
1011 {
1012     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
1013     return write_mie(env, CSR_MIE, newval);
1014 }
1015
1016 static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val)
1017 {
1018     *val = env->hcounteren;
1019     return 0;
1020 }
1021
1022 static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
1023 {
1024     env->hcounteren = val;
1025     return 0;
1026 }
1027
1028 static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
1029 {
1030     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1031     return 0;
1032 }
1033
1034 static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
1035 {
1036     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1037     return 0;
1038 }
1039
1040 static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
1041 {
1042     *val = env->htval;
1043     return 0;
1044 }
1045
1046 static int write_htval(CPURISCVState *env, int csrno, target_ulong val)
1047 {
1048     env->htval = val;
1049     return 0;
1050 }
1051
1052 static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
1053 {
1054     *val = env->htinst;
1055     return 0;
1056 }
1057
1058 static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
1059 {
1060     return 0;
1061 }
1062
1063 static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
1064 {
1065     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1066     return 0;
1067 }
1068
1069 static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
1070 {
1071     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1072     return 0;
1073 }
1074
1075 static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
1076 {
1077     *val = env->hgatp;
1078     return 0;
1079 }
1080
1081 static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
1082 {
1083     env->hgatp = val;
1084     return 0;
1085 }
1086
1087 static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
1088 {
1089     if (!env->rdtime_fn) {
1090         return -RISCV_EXCP_ILLEGAL_INST;
1091     }
1092
1093     *val = env->htimedelta;
1094     return 0;
1095 }
1096
1097 static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
1098 {
1099     if (!env->rdtime_fn) {
1100         return -RISCV_EXCP_ILLEGAL_INST;
1101     }
1102
1103     if (riscv_cpu_is_32bit(env)) {
1104         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1105     } else {
1106         env->htimedelta = val;
1107     }
1108     return 0;
1109 }
1110
1111 static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
1112 {
1113     if (!env->rdtime_fn) {
1114         return -RISCV_EXCP_ILLEGAL_INST;
1115     }
1116
1117     *val = env->htimedelta >> 32;
1118     return 0;
1119 }
1120
1121 static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
1122 {
1123     if (!env->rdtime_fn) {
1124         return -RISCV_EXCP_ILLEGAL_INST;
1125     }
1126
1127     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1128     return 0;
1129 }
1130
1131 /* Virtual CSR Registers */
1132 static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
1133 {
1134     *val = env->vsstatus;
1135     return 0;
1136 }
1137
1138 static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
1139 {
1140     uint64_t mask = (target_ulong)-1;
1141     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1142     return 0;
1143 }
1144
1145 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1146 {
1147     *val = env->vstvec;
1148     return 0;
1149 }
1150
1151 static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val)
1152 {
1153     env->vstvec = val;
1154     return 0;
1155 }
1156
1157 static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val)
1158 {
1159     *val = env->vsscratch;
1160     return 0;
1161 }
1162
1163 static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val)
1164 {
1165     env->vsscratch = val;
1166     return 0;
1167 }
1168
1169 static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val)
1170 {
1171     *val = env->vsepc;
1172     return 0;
1173 }
1174
1175 static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val)
1176 {
1177     env->vsepc = val;
1178     return 0;
1179 }
1180
1181 static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val)
1182 {
1183     *val = env->vscause;
1184     return 0;
1185 }
1186
1187 static int write_vscause(CPURISCVState *env, int csrno, target_ulong val)
1188 {
1189     env->vscause = val;
1190     return 0;
1191 }
1192
1193 static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val)
1194 {
1195     *val = env->vstval;
1196     return 0;
1197 }
1198
1199 static int write_vstval(CPURISCVState *env, int csrno, target_ulong val)
1200 {
1201     env->vstval = val;
1202     return 0;
1203 }
1204
1205 static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val)
1206 {
1207     *val = env->vsatp;
1208     return 0;
1209 }
1210
1211 static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val)
1212 {
1213     env->vsatp = val;
1214     return 0;
1215 }
1216
1217 static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
1218 {
1219     *val = env->mtval2;
1220     return 0;
1221 }
1222
1223 static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
1224 {
1225     env->mtval2 = val;
1226     return 0;
1227 }
1228
1229 static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
1230 {
1231     *val = env->mtinst;
1232     return 0;
1233 }
1234
1235 static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
1236 {
1237     env->mtinst = val;
1238     return 0;
1239 }
1240
1241 /* Physical Memory Protection */
1242 static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
1243 {
1244     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1245     return 0;
1246 }
1247
1248 static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val)
1249 {
1250     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1251     return 0;
1252 }
1253
1254 static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val)
1255 {
1256     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1257     return 0;
1258 }
1259
1260 static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
1261 {
1262     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1263     return 0;
1264 }
1265
1266 #endif
1267
1268 /*
1269  * riscv_csrrw - read and/or update control and status register
1270  *
1271  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
1272  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
1273  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
1274  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
1275  */
1276
1277 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
1278                 target_ulong new_value, target_ulong write_mask)
1279 {
1280     int ret;
1281     target_ulong old_value;
1282     RISCVCPU *cpu = env_archcpu(env);
1283
1284     /* check privileges and return -1 if check fails */
1285 #if !defined(CONFIG_USER_ONLY)
1286     int effective_priv = env->priv;
1287     int read_only = get_field(csrno, 0xC00) == 3;
1288
1289     if (riscv_has_ext(env, RVH) &&
1290         env->priv == PRV_S &&
1291         !riscv_cpu_virt_enabled(env)) {
1292         /*
1293          * We are in S mode without virtualisation, therefore we are in HS Mode.
1294          * Add 1 to the effective privledge level to allow us to access the
1295          * Hypervisor CSRs.
1296          */
1297         effective_priv++;
1298     }
1299
1300     if ((write_mask && read_only) ||
1301         (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
1302         return -RISCV_EXCP_ILLEGAL_INST;
1303     }
1304 #endif
1305
1306     /* ensure the CSR extension is enabled. */
1307     if (!cpu->cfg.ext_icsr) {
1308         return -RISCV_EXCP_ILLEGAL_INST;
1309     }
1310
1311     /* check predicate */
1312     if (!csr_ops[csrno].predicate) {
1313         return -RISCV_EXCP_ILLEGAL_INST;
1314     }
1315     ret = csr_ops[csrno].predicate(env, csrno);
1316     if (ret < 0) {
1317         return ret;
1318     }
1319
1320     /* execute combined read/write operation if it exists */
1321     if (csr_ops[csrno].op) {
1322         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1323     }
1324
1325     /* if no accessor exists then return failure */
1326     if (!csr_ops[csrno].read) {
1327         return -RISCV_EXCP_ILLEGAL_INST;
1328     }
1329
1330     /* read old value */
1331     ret = csr_ops[csrno].read(env, csrno, &old_value);
1332     if (ret < 0) {
1333         return ret;
1334     }
1335
1336     /* write value if writable and write mask set, otherwise drop writes */
1337     if (write_mask) {
1338         new_value = (old_value & ~write_mask) | (new_value & write_mask);
1339         if (csr_ops[csrno].write) {
1340             ret = csr_ops[csrno].write(env, csrno, new_value);
1341             if (ret < 0) {
1342                 return ret;
1343             }
1344         }
1345     }
1346
1347     /* return old value */
1348     if (ret_value) {
1349         *ret_value = old_value;
1350     }
1351
1352     return 0;
1353 }
1354
1355 /*
1356  * Debugger support.  If not in user mode, set env->debugger before the
1357  * riscv_csrrw call and clear it after the call.
1358  */
1359 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
1360                 target_ulong new_value, target_ulong write_mask)
1361 {
1362     int ret;
1363 #if !defined(CONFIG_USER_ONLY)
1364     env->debugger = true;
1365 #endif
1366     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
1367 #if !defined(CONFIG_USER_ONLY)
1368     env->debugger = false;
1369 #endif
1370     return ret;
1371 }
1372
1373 /* Control and Status Register function table */
1374 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
1375     /* User Floating-Point CSRs */
1376     [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
1377     [CSR_FRM]      = { "frm",      fs,     read_frm,     write_frm    },
1378     [CSR_FCSR]     = { "fcsr",     fs,     read_fcsr,    write_fcsr   },
1379     /* Vector CSRs */
1380     [CSR_VSTART]   = { "vstart",   vs,     read_vstart,  write_vstart },
1381     [CSR_VXSAT]    = { "vxsat",    vs,     read_vxsat,   write_vxsat  },
1382     [CSR_VXRM]     = { "vxrm",     vs,     read_vxrm,    write_vxrm   },
1383     [CSR_VL]       = { "vl",       vs,     read_vl                    },
1384     [CSR_VTYPE]    = { "vtype",    vs,     read_vtype                 },
1385     /* User Timers and Counters */
1386     [CSR_CYCLE]    = { "cycle",    ctr,    read_instret  },
1387     [CSR_INSTRET]  = { "instret",  ctr,    read_instret  },
1388     [CSR_CYCLEH]   = { "cycleh",   ctr32,  read_instreth },
1389     [CSR_INSTRETH] = { "instreth", ctr32,  read_instreth },
1390
1391     /*
1392      * In privileged mode, the monitor will have to emulate TIME CSRs only if
1393      * rdtime callback is not provided by machine/platform emulation.
1394      */
1395     [CSR_TIME]  = { "time",  ctr,   read_time  },
1396     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
1397
1398 #if !defined(CONFIG_USER_ONLY)
1399     /* Machine Timers and Counters */
1400     [CSR_MCYCLE]    = { "mcycle",    any,   read_instret  },
1401     [CSR_MINSTRET]  = { "minstret",  any,   read_instret  },
1402     [CSR_MCYCLEH]   = { "mcycleh",   any32, read_instreth },
1403     [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
1404
1405     /* Machine Information Registers */
1406     [CSR_MVENDORID] = { "mvendorid", any,   read_zero    },
1407     [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
1408     [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
1409     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
1410
1411     /* Machine Trap Setup */
1412     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus     },
1413     [CSR_MISA]        = { "misa",       any,   read_misa,        write_misa        },
1414     [CSR_MIDELEG]     = { "mideleg",    any,   read_mideleg,     write_mideleg     },
1415     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg,     write_medeleg     },
1416     [CSR_MIE]         = { "mie",        any,   read_mie,         write_mie         },
1417     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,       write_mtvec       },
1418     [CSR_MCOUNTEREN]  = { "mcounteren", any,   read_mcounteren,  write_mcounteren  },
1419
1420     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
1421
1422     [CSR_MSCOUNTEREN] = { "msounteren", any,   read_mscounteren, write_mscounteren },
1423
1424     /* Machine Trap Handling */
1425     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch, write_mscratch },
1426     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
1427     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
1428     [CSR_MBADADDR] = { "mbadaddr", any,  read_mbadaddr, write_mbadaddr },
1429     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
1430
1431     /* Supervisor Trap Setup */
1432     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus    },
1433     [CSR_SIE]        = { "sie",        smode, read_sie,        write_sie        },
1434     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec      },
1435     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
1436
1437     /* Supervisor Trap Handling */
1438     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
1439     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
1440     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
1441     [CSR_SBADADDR] = { "sbadaddr", smode, read_sbadaddr, write_sbadaddr },
1442     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
1443
1444     /* Supervisor Protection and Translation */
1445     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
1446
1447     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus,     write_hstatus     },
1448     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg,     write_hedeleg     },
1449     [CSR_HIDELEG]     = { "hideleg",     hmode,   read_hideleg,     write_hideleg     },
1450     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL,     rmw_hvip          },
1451     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
1452     [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
1453     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
1454     [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,       write_hgeie       },
1455     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
1456     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
1457     [CSR_HGEIP]       = { "hgeip",       hmode,   read_hgeip,       write_hgeip       },
1458     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
1459     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
1460     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
1461
1462     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,    write_vsstatus    },
1463     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL,    rmw_vsip          },
1464     [CSR_VSIE]        = { "vsie",        hmode,   read_vsie,        write_vsie        },
1465     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,      write_vstvec      },
1466     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,   write_vsscratch   },
1467     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,       write_vsepc       },
1468     [CSR_VSCAUSE]     = { "vscause",     hmode,   read_vscause,     write_vscause     },
1469     [CSR_VSTVAL]      = { "vstval",      hmode,   read_vstval,      write_vstval      },
1470     [CSR_VSATP]       = { "vsatp",       hmode,   read_vsatp,       write_vsatp       },
1471
1472     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
1473     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
1474
1475     /* Physical Memory Protection */
1476     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
1477     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
1478     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
1479     [CSR_PMPCFG3]    = { "pmpcfg3",   pmp, read_pmpcfg,  write_pmpcfg  },
1480     [CSR_PMPADDR0]   = { "pmpaddr0",  pmp, read_pmpaddr, write_pmpaddr },
1481     [CSR_PMPADDR1]   = { "pmpaddr1",  pmp, read_pmpaddr, write_pmpaddr },
1482     [CSR_PMPADDR2]   = { "pmpaddr2",  pmp, read_pmpaddr, write_pmpaddr },
1483     [CSR_PMPADDR3]   = { "pmpaddr3",  pmp, read_pmpaddr, write_pmpaddr },
1484     [CSR_PMPADDR4]   = { "pmpaddr4",  pmp, read_pmpaddr, write_pmpaddr },
1485     [CSR_PMPADDR5]   = { "pmpaddr5",  pmp, read_pmpaddr, write_pmpaddr },
1486     [CSR_PMPADDR6]   = { "pmpaddr6",  pmp, read_pmpaddr, write_pmpaddr },
1487     [CSR_PMPADDR7]   = { "pmpaddr7",  pmp, read_pmpaddr, write_pmpaddr },
1488     [CSR_PMPADDR8]   = { "pmpaddr8",  pmp, read_pmpaddr, write_pmpaddr },
1489     [CSR_PMPADDR9]   = { "pmpaddr9",  pmp, read_pmpaddr, write_pmpaddr },
1490     [CSR_PMPADDR10]  = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
1491     [CSR_PMPADDR11]  = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
1492     [CSR_PMPADDR12]  = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
1493     [CSR_PMPADDR13]  = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
1494     [CSR_PMPADDR14] =  { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
1495     [CSR_PMPADDR15] =  { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
1496
1497     /* Performance Counters */
1498     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_zero },
1499     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_zero },
1500     [CSR_HPMCOUNTER5]    = { "hpmcounter5",    ctr,    read_zero },
1501     [CSR_HPMCOUNTER6]    = { "hpmcounter6",    ctr,    read_zero },
1502     [CSR_HPMCOUNTER7]    = { "hpmcounter7",    ctr,    read_zero },
1503     [CSR_HPMCOUNTER8]    = { "hpmcounter8",    ctr,    read_zero },
1504     [CSR_HPMCOUNTER9]    = { "hpmcounter9",    ctr,    read_zero },
1505     [CSR_HPMCOUNTER10]   = { "hpmcounter10",   ctr,    read_zero },
1506     [CSR_HPMCOUNTER11]   = { "hpmcounter11",   ctr,    read_zero },
1507     [CSR_HPMCOUNTER12]   = { "hpmcounter12",   ctr,    read_zero },
1508     [CSR_HPMCOUNTER13]   = { "hpmcounter13",   ctr,    read_zero },
1509     [CSR_HPMCOUNTER14]   = { "hpmcounter14",   ctr,    read_zero },
1510     [CSR_HPMCOUNTER15]   = { "hpmcounter15",   ctr,    read_zero },
1511     [CSR_HPMCOUNTER16]   = { "hpmcounter16",   ctr,    read_zero },
1512     [CSR_HPMCOUNTER17]   = { "hpmcounter17",   ctr,    read_zero },
1513     [CSR_HPMCOUNTER18]   = { "hpmcounter18",   ctr,    read_zero },
1514     [CSR_HPMCOUNTER19]   = { "hpmcounter19",   ctr,    read_zero },
1515     [CSR_HPMCOUNTER20]   = { "hpmcounter20",   ctr,    read_zero },
1516     [CSR_HPMCOUNTER21]   = { "hpmcounter21",   ctr,    read_zero },
1517     [CSR_HPMCOUNTER22]   = { "hpmcounter22",   ctr,    read_zero },
1518     [CSR_HPMCOUNTER23]   = { "hpmcounter23",   ctr,    read_zero },
1519     [CSR_HPMCOUNTER24]   = { "hpmcounter24",   ctr,    read_zero },
1520     [CSR_HPMCOUNTER25]   = { "hpmcounter25",   ctr,    read_zero },
1521     [CSR_HPMCOUNTER26]   = { "hpmcounter26",   ctr,    read_zero },
1522     [CSR_HPMCOUNTER27]   = { "hpmcounter27",   ctr,    read_zero },
1523     [CSR_HPMCOUNTER28]   = { "hpmcounter28",   ctr,    read_zero },
1524     [CSR_HPMCOUNTER29]   = { "hpmcounter29",   ctr,    read_zero },
1525     [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,    read_zero },
1526     [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,    read_zero },
1527
1528     [CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   any,    read_zero },
1529     [CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   any,    read_zero },
1530     [CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   any,    read_zero },
1531     [CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   any,    read_zero },
1532     [CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   any,    read_zero },
1533     [CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   any,    read_zero },
1534     [CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   any,    read_zero },
1535     [CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  any,    read_zero },
1536     [CSR_MHPMCOUNTER11]  = { "mhpmcounter11",  any,    read_zero },
1537     [CSR_MHPMCOUNTER12]  = { "mhpmcounter12",  any,    read_zero },
1538     [CSR_MHPMCOUNTER13]  = { "mhpmcounter13",  any,    read_zero },
1539     [CSR_MHPMCOUNTER14]  = { "mhpmcounter14",  any,    read_zero },
1540     [CSR_MHPMCOUNTER15]  = { "mhpmcounter15",  any,    read_zero },
1541     [CSR_MHPMCOUNTER16]  = { "mhpmcounter16",  any,    read_zero },
1542     [CSR_MHPMCOUNTER17]  = { "mhpmcounter17",  any,    read_zero },
1543     [CSR_MHPMCOUNTER18]  = { "mhpmcounter18",  any,    read_zero },
1544     [CSR_MHPMCOUNTER19]  = { "mhpmcounter19",  any,    read_zero },
1545     [CSR_MHPMCOUNTER20]  = { "mhpmcounter20",  any,    read_zero },
1546     [CSR_MHPMCOUNTER21]  = { "mhpmcounter21",  any,    read_zero },
1547     [CSR_MHPMCOUNTER22]  = { "mhpmcounter22",  any,    read_zero },
1548     [CSR_MHPMCOUNTER23]  = { "mhpmcounter23",  any,    read_zero },
1549     [CSR_MHPMCOUNTER24]  = { "mhpmcounter24",  any,    read_zero },
1550     [CSR_MHPMCOUNTER25]  = { "mhpmcounter25",  any,    read_zero },
1551     [CSR_MHPMCOUNTER26]  = { "mhpmcounter26",  any,    read_zero },
1552     [CSR_MHPMCOUNTER27]  = { "mhpmcounter27",  any,    read_zero },
1553     [CSR_MHPMCOUNTER28]  = { "mhpmcounter28",  any,    read_zero },
1554     [CSR_MHPMCOUNTER29]  = { "mhpmcounter29",  any,    read_zero },
1555     [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  any,    read_zero },
1556     [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  any,    read_zero },
1557
1558     [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_zero },
1559     [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_zero },
1560     [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_zero },
1561     [CSR_MHPMEVENT6]     = { "mhpmevent6",     any,    read_zero },
1562     [CSR_MHPMEVENT7]     = { "mhpmevent7",     any,    read_zero },
1563     [CSR_MHPMEVENT8]     = { "mhpmevent8",     any,    read_zero },
1564     [CSR_MHPMEVENT9]     = { "mhpmevent9",     any,    read_zero },
1565     [CSR_MHPMEVENT10]    = { "mhpmevent10",    any,    read_zero },
1566     [CSR_MHPMEVENT11]    = { "mhpmevent11",    any,    read_zero },
1567     [CSR_MHPMEVENT12]    = { "mhpmevent12",    any,    read_zero },
1568     [CSR_MHPMEVENT13]    = { "mhpmevent13",    any,    read_zero },
1569     [CSR_MHPMEVENT14]    = { "mhpmevent14",    any,    read_zero },
1570     [CSR_MHPMEVENT15]    = { "mhpmevent15",    any,    read_zero },
1571     [CSR_MHPMEVENT16]    = { "mhpmevent16",    any,    read_zero },
1572     [CSR_MHPMEVENT17]    = { "mhpmevent17",    any,    read_zero },
1573     [CSR_MHPMEVENT18]    = { "mhpmevent18",    any,    read_zero },
1574     [CSR_MHPMEVENT19]    = { "mhpmevent19",    any,    read_zero },
1575     [CSR_MHPMEVENT20]    = { "mhpmevent20",    any,    read_zero },
1576     [CSR_MHPMEVENT21]    = { "mhpmevent21",    any,    read_zero },
1577     [CSR_MHPMEVENT22]    = { "mhpmevent22",    any,    read_zero },
1578     [CSR_MHPMEVENT23]    = { "mhpmevent23",    any,    read_zero },
1579     [CSR_MHPMEVENT24]    = { "mhpmevent24",    any,    read_zero },
1580     [CSR_MHPMEVENT25]    = { "mhpmevent25",    any,    read_zero },
1581     [CSR_MHPMEVENT26]    = { "mhpmevent26",    any,    read_zero },
1582     [CSR_MHPMEVENT27]    = { "mhpmevent27",    any,    read_zero },
1583     [CSR_MHPMEVENT28]    = { "mhpmevent28",    any,    read_zero },
1584     [CSR_MHPMEVENT29]    = { "mhpmevent29",    any,    read_zero },
1585     [CSR_MHPMEVENT30]    = { "mhpmevent30",    any,    read_zero },
1586     [CSR_MHPMEVENT31]    = { "mhpmevent31",    any,    read_zero },
1587
1588     [CSR_HPMCOUNTER3H]   = { "hpmcounter3h",   ctr32,  read_zero },
1589     [CSR_HPMCOUNTER4H]   = { "hpmcounter4h",   ctr32,  read_zero },
1590     [CSR_HPMCOUNTER5H]   = { "hpmcounter5h",   ctr32,  read_zero },
1591     [CSR_HPMCOUNTER6H]   = { "hpmcounter6h",   ctr32,  read_zero },
1592     [CSR_HPMCOUNTER7H]   = { "hpmcounter7h",   ctr32,  read_zero },
1593     [CSR_HPMCOUNTER8H]   = { "hpmcounter8h",   ctr32,  read_zero },
1594     [CSR_HPMCOUNTER9H]   = { "hpmcounter9h",   ctr32,  read_zero },
1595     [CSR_HPMCOUNTER10H]  = { "hpmcounter10h",  ctr32,  read_zero },
1596     [CSR_HPMCOUNTER11H]  = { "hpmcounter11h",  ctr32,  read_zero },
1597     [CSR_HPMCOUNTER12H]  = { "hpmcounter12h",  ctr32,  read_zero },
1598     [CSR_HPMCOUNTER13H]  = { "hpmcounter13h",  ctr32,  read_zero },
1599     [CSR_HPMCOUNTER14H]  = { "hpmcounter14h",  ctr32,  read_zero },
1600     [CSR_HPMCOUNTER15H]  = { "hpmcounter15h",  ctr32,  read_zero },
1601     [CSR_HPMCOUNTER16H]  = { "hpmcounter16h",  ctr32,  read_zero },
1602     [CSR_HPMCOUNTER17H]  = { "hpmcounter17h",  ctr32,  read_zero },
1603     [CSR_HPMCOUNTER18H]  = { "hpmcounter18h",  ctr32,  read_zero },
1604     [CSR_HPMCOUNTER19H]  = { "hpmcounter19h",  ctr32,  read_zero },
1605     [CSR_HPMCOUNTER20H]  = { "hpmcounter20h",  ctr32,  read_zero },
1606     [CSR_HPMCOUNTER21H]  = { "hpmcounter21h",  ctr32,  read_zero },
1607     [CSR_HPMCOUNTER22H]  = { "hpmcounter22h",  ctr32,  read_zero },
1608     [CSR_HPMCOUNTER23H]  = { "hpmcounter23h",  ctr32,  read_zero },
1609     [CSR_HPMCOUNTER24H]  = { "hpmcounter24h",  ctr32,  read_zero },
1610     [CSR_HPMCOUNTER25H]  = { "hpmcounter25h",  ctr32,  read_zero },
1611     [CSR_HPMCOUNTER26H]  = { "hpmcounter26h",  ctr32,  read_zero },
1612     [CSR_HPMCOUNTER27H]  = { "hpmcounter27h",  ctr32,  read_zero },
1613     [CSR_HPMCOUNTER28H]  = { "hpmcounter28h",  ctr32,  read_zero },
1614     [CSR_HPMCOUNTER29H]  = { "hpmcounter29h",  ctr32,  read_zero },
1615     [CSR_HPMCOUNTER30H]  = { "hpmcounter30h",  ctr32,  read_zero },
1616     [CSR_HPMCOUNTER31H]  = { "hpmcounter31h",  ctr32,  read_zero },
1617
1618     [CSR_MHPMCOUNTER3H]  = { "mhpmcounter3h",  any32,  read_zero },
1619     [CSR_MHPMCOUNTER4H]  = { "mhpmcounter4h",  any32,  read_zero },
1620     [CSR_MHPMCOUNTER5H]  = { "mhpmcounter5h",  any32,  read_zero },
1621     [CSR_MHPMCOUNTER6H]  = { "mhpmcounter6h",  any32,  read_zero },
1622     [CSR_MHPMCOUNTER7H]  = { "mhpmcounter7h",  any32,  read_zero },
1623     [CSR_MHPMCOUNTER8H]  = { "mhpmcounter8h",  any32,  read_zero },
1624     [CSR_MHPMCOUNTER9H]  = { "mhpmcounter9h",  any32,  read_zero },
1625     [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32,  read_zero },
1626     [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32,  read_zero },
1627     [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32,  read_zero },
1628     [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32,  read_zero },
1629     [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32,  read_zero },
1630     [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32,  read_zero },
1631     [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32,  read_zero },
1632     [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32,  read_zero },
1633     [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32,  read_zero },
1634     [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32,  read_zero },
1635     [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32,  read_zero },
1636     [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32,  read_zero },
1637     [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32,  read_zero },
1638     [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32,  read_zero },
1639     [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32,  read_zero },
1640     [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32,  read_zero },
1641     [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32,  read_zero },
1642     [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32,  read_zero },
1643     [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32,  read_zero },
1644     [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32,  read_zero },
1645     [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32,  read_zero },
1646     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32,  read_zero },
1647 #endif /* !CONFIG_USER_ONLY */
1648 };