2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* This file contains implementation code for the RealView EB interrupt
11 * controller, MPCore distributed interrupt controller and ARMv7-M
12 * Nested Vectored Interrupt Controller.
13 * It is compiled in two ways:
14 * (1) as a standalone file to produce a sysbus device which is a GIC
15 * that can be used on the realview board and as one of the builtin
16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
17 * (2) by being directly #included into armv7m_nvic.c to produce the
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "gic_internal.h"
24 #include "qapi/error.h"
28 #include "sysemu/kvm.h"
30 /* #define DEBUG_GIC */
33 #define DEBUG_GIC_GATE 1
35 #define DEBUG_GIC_GATE 0
38 #define DPRINTF(fmt, ...) do { \
39 if (DEBUG_GIC_GATE) { \
40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
44 static const uint8_t gic_id_11mpcore
[] = {
45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
48 static const uint8_t gic_id_gicv1
[] = {
49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
52 static const uint8_t gic_id_gicv2
[] = {
53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
56 static inline int gic_get_current_cpu(GICState
*s
)
59 return current_cpu
->cpu_index
;
64 /* Return true if this GIC config has interrupt groups, which is
65 * true if we're a GICv2, or a GICv1 with the security extensions.
67 static inline bool gic_has_groups(GICState
*s
)
69 return s
->revision
== 2 || s
->security_extn
;
72 /* TODO: Many places that call this routine could be optimized. */
73 /* Update interrupt status after enabled or pending bits have been changed. */
74 void gic_update(GICState
*s
)
79 int irq_level
, fiq_level
;
83 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
85 s
->current_pending
[cpu
] = 1023;
86 if (!(s
->ctlr
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
))
87 || !(s
->cpu_ctlr
[cpu
] & (GICC_CTLR_EN_GRP0
| GICC_CTLR_EN_GRP1
))) {
88 qemu_irq_lower(s
->parent_irq
[cpu
]);
89 qemu_irq_lower(s
->parent_fiq
[cpu
]);
94 for (irq
= 0; irq
< s
->num_irq
; irq
++) {
95 if (GIC_TEST_ENABLED(irq
, cm
) && gic_test_pending(s
, irq
, cm
) &&
96 (!GIC_TEST_ACTIVE(irq
, cm
)) &&
97 (irq
< GIC_INTERNAL
|| GIC_TARGET(irq
) & cm
)) {
98 if (GIC_GET_PRIORITY(irq
, cpu
) < best_prio
) {
99 best_prio
= GIC_GET_PRIORITY(irq
, cpu
);
105 if (best_irq
!= 1023) {
106 trace_gic_update_bestirq(cpu
, best_irq
, best_prio
,
107 s
->priority_mask
[cpu
], s
->running_priority
[cpu
]);
110 irq_level
= fiq_level
= 0;
112 if (best_prio
< s
->priority_mask
[cpu
]) {
113 s
->current_pending
[cpu
] = best_irq
;
114 if (best_prio
< s
->running_priority
[cpu
]) {
115 int group
= GIC_TEST_GROUP(best_irq
, cm
);
117 if (extract32(s
->ctlr
, group
, 1) &&
118 extract32(s
->cpu_ctlr
[cpu
], group
, 1)) {
119 if (group
== 0 && s
->cpu_ctlr
[cpu
] & GICC_CTLR_FIQ_EN
) {
120 DPRINTF("Raised pending FIQ %d (cpu %d)\n",
123 trace_gic_update_set_irq(cpu
, "fiq", fiq_level
);
125 DPRINTF("Raised pending IRQ %d (cpu %d)\n",
128 trace_gic_update_set_irq(cpu
, "irq", irq_level
);
134 qemu_set_irq(s
->parent_irq
[cpu
], irq_level
);
135 qemu_set_irq(s
->parent_fiq
[cpu
], fiq_level
);
139 void gic_set_pending_private(GICState
*s
, int cpu
, int irq
)
143 if (gic_test_pending(s
, irq
, cm
)) {
147 DPRINTF("Set %d pending cpu %d\n", irq
, cpu
);
148 GIC_SET_PENDING(irq
, cm
);
152 static void gic_set_irq_11mpcore(GICState
*s
, int irq
, int level
,
156 GIC_SET_LEVEL(irq
, cm
);
157 if (GIC_TEST_EDGE_TRIGGER(irq
) || GIC_TEST_ENABLED(irq
, cm
)) {
158 DPRINTF("Set %d pending mask %x\n", irq
, target
);
159 GIC_SET_PENDING(irq
, target
);
162 GIC_CLEAR_LEVEL(irq
, cm
);
166 static void gic_set_irq_generic(GICState
*s
, int irq
, int level
,
170 GIC_SET_LEVEL(irq
, cm
);
171 DPRINTF("Set %d pending mask %x\n", irq
, target
);
172 if (GIC_TEST_EDGE_TRIGGER(irq
)) {
173 GIC_SET_PENDING(irq
, target
);
176 GIC_CLEAR_LEVEL(irq
, cm
);
180 /* Process a change in an external IRQ input. */
181 static void gic_set_irq(void *opaque
, int irq
, int level
)
183 /* Meaning of the 'irq' parameter:
184 * [0..N-1] : external interrupts
185 * [N..N+31] : PPI (internal) interrupts for CPU 0
186 * [N+32..N+63] : PPI (internal interrupts for CPU 1
189 GICState
*s
= (GICState
*)opaque
;
191 if (irq
< (s
->num_irq
- GIC_INTERNAL
)) {
192 /* The first external input line is internal interrupt 32. */
195 target
= GIC_TARGET(irq
);
198 irq
-= (s
->num_irq
- GIC_INTERNAL
);
199 cpu
= irq
/ GIC_INTERNAL
;
205 assert(irq
>= GIC_NR_SGIS
);
207 if (level
== GIC_TEST_LEVEL(irq
, cm
)) {
211 if (s
->revision
== REV_11MPCORE
) {
212 gic_set_irq_11mpcore(s
, irq
, level
, cm
, target
);
214 gic_set_irq_generic(s
, irq
, level
, cm
, target
);
216 trace_gic_set_irq(irq
, level
, cm
, target
);
221 static uint16_t gic_get_current_pending_irq(GICState
*s
, int cpu
,
224 uint16_t pending_irq
= s
->current_pending
[cpu
];
226 if (pending_irq
< GIC_MAXIRQ
&& gic_has_groups(s
)) {
227 int group
= GIC_TEST_GROUP(pending_irq
, (1 << cpu
));
228 /* On a GIC without the security extensions, reading this register
229 * behaves in the same way as a secure access to a GIC with them.
231 bool secure
= !s
->security_extn
|| attrs
.secure
;
233 if (group
== 0 && !secure
) {
234 /* Group0 interrupts hidden from Non-secure access */
237 if (group
== 1 && secure
&& !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_ACK_CTL
)) {
238 /* Group1 interrupts only seen by Secure access if
247 static int gic_get_group_priority(GICState
*s
, int cpu
, int irq
)
249 /* Return the group priority of the specified interrupt
250 * (which is the top bits of its priority, with the number
251 * of bits masked determined by the applicable binary point register).
256 if (gic_has_groups(s
) &&
257 !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) &&
258 GIC_TEST_GROUP(irq
, (1 << cpu
))) {
259 bpr
= s
->abpr
[cpu
] - 1;
265 /* a BPR of 0 means the group priority bits are [7:1];
266 * a BPR of 1 means they are [7:2], and so on down to
267 * a BPR of 7 meaning no group priority bits at all.
269 mask
= ~0U << ((bpr
& 7) + 1);
271 return GIC_GET_PRIORITY(irq
, cpu
) & mask
;
274 static void gic_activate_irq(GICState
*s
, int cpu
, int irq
)
276 /* Set the appropriate Active Priority Register bit for this IRQ,
277 * and update the running priority.
279 int prio
= gic_get_group_priority(s
, cpu
, irq
);
280 int preemption_level
= prio
>> (GIC_MIN_BPR
+ 1);
281 int regno
= preemption_level
/ 32;
282 int bitno
= preemption_level
% 32;
284 if (gic_has_groups(s
) && GIC_TEST_GROUP(irq
, (1 << cpu
))) {
285 s
->nsapr
[regno
][cpu
] |= (1 << bitno
);
287 s
->apr
[regno
][cpu
] |= (1 << bitno
);
290 s
->running_priority
[cpu
] = prio
;
291 GIC_SET_ACTIVE(irq
, 1 << cpu
);
294 static int gic_get_prio_from_apr_bits(GICState
*s
, int cpu
)
296 /* Recalculate the current running priority for this CPU based
297 * on the set bits in the Active Priority Registers.
300 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
301 uint32_t apr
= s
->apr
[i
][cpu
] | s
->nsapr
[i
][cpu
];
305 return (i
* 32 + ctz32(apr
)) << (GIC_MIN_BPR
+ 1);
310 static void gic_drop_prio(GICState
*s
, int cpu
, int group
)
312 /* Drop the priority of the currently active interrupt in the
315 * Note that we can guarantee (because of the requirement to nest
316 * GICC_IAR reads [which activate an interrupt and raise priority]
317 * with GICC_EOIR writes [which drop the priority for the interrupt])
318 * that the interrupt we're being called for is the highest priority
319 * active interrupt, meaning that it has the lowest set bit in the
322 * If the guest does not honour the ordering constraints then the
323 * behaviour of the GIC is UNPREDICTABLE, which for us means that
324 * the values of the APR registers might become incorrect and the
325 * running priority will be wrong, so interrupts that should preempt
326 * might not do so, and interrupts that should not preempt might do so.
330 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
331 uint32_t *papr
= group
? &s
->nsapr
[i
][cpu
] : &s
->apr
[i
][cpu
];
335 /* Clear lowest set bit */
340 s
->running_priority
[cpu
] = gic_get_prio_from_apr_bits(s
, cpu
);
343 uint32_t gic_acknowledge_irq(GICState
*s
, int cpu
, MemTxAttrs attrs
)
348 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
349 * for the case where this GIC supports grouping and the pending interrupt
350 * is in the wrong group.
352 irq
= gic_get_current_pending_irq(s
, cpu
, attrs
);
353 trace_gic_acknowledge_irq(cpu
, irq
);
355 if (irq
>= GIC_MAXIRQ
) {
356 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq
);
360 if (GIC_GET_PRIORITY(irq
, cpu
) >= s
->running_priority
[cpu
]) {
361 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq
);
365 if (s
->revision
== REV_11MPCORE
) {
366 /* Clear pending flags for both level and edge triggered interrupts.
367 * Level triggered IRQs will be reasserted once they become inactive.
369 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
372 if (irq
< GIC_NR_SGIS
) {
373 /* Lookup the source CPU for the SGI and clear this in the
374 * sgi_pending map. Return the src and clear the overall pending
375 * state on this CPU if the SGI is not pending from any CPUs.
377 assert(s
->sgi_pending
[irq
][cpu
] != 0);
378 src
= ctz32(s
->sgi_pending
[irq
][cpu
]);
379 s
->sgi_pending
[irq
][cpu
] &= ~(1 << src
);
380 if (s
->sgi_pending
[irq
][cpu
] == 0) {
381 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
383 ret
= irq
| ((src
& 0x7) << 10);
385 /* Clear pending state for both level and edge triggered
386 * interrupts. (level triggered interrupts with an active line
387 * remain pending, see gic_test_pending)
389 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
394 gic_activate_irq(s
, cpu
, irq
);
396 DPRINTF("ACK %d\n", irq
);
400 void gic_set_priority(GICState
*s
, int cpu
, int irq
, uint8_t val
,
403 if (s
->security_extn
&& !attrs
.secure
) {
404 if (!GIC_TEST_GROUP(irq
, (1 << cpu
))) {
405 return; /* Ignore Non-secure access of Group0 IRQ */
407 val
= 0x80 | (val
>> 1); /* Non-secure view */
410 if (irq
< GIC_INTERNAL
) {
411 s
->priority1
[irq
][cpu
] = val
;
413 s
->priority2
[(irq
) - GIC_INTERNAL
] = val
;
417 static uint32_t gic_get_priority(GICState
*s
, int cpu
, int irq
,
420 uint32_t prio
= GIC_GET_PRIORITY(irq
, cpu
);
422 if (s
->security_extn
&& !attrs
.secure
) {
423 if (!GIC_TEST_GROUP(irq
, (1 << cpu
))) {
424 return 0; /* Non-secure access cannot read priority of Group0 IRQ */
426 prio
= (prio
<< 1) & 0xff; /* Non-secure view */
431 static void gic_set_priority_mask(GICState
*s
, int cpu
, uint8_t pmask
,
434 if (s
->security_extn
&& !attrs
.secure
) {
435 if (s
->priority_mask
[cpu
] & 0x80) {
436 /* Priority Mask in upper half */
437 pmask
= 0x80 | (pmask
>> 1);
439 /* Non-secure write ignored if priority mask is in lower half */
443 s
->priority_mask
[cpu
] = pmask
;
446 static uint32_t gic_get_priority_mask(GICState
*s
, int cpu
, MemTxAttrs attrs
)
448 uint32_t pmask
= s
->priority_mask
[cpu
];
450 if (s
->security_extn
&& !attrs
.secure
) {
452 /* Priority Mask in upper half, return Non-secure view */
453 pmask
= (pmask
<< 1) & 0xff;
455 /* Priority Mask in lower half, RAZ */
462 static uint32_t gic_get_cpu_control(GICState
*s
, int cpu
, MemTxAttrs attrs
)
464 uint32_t ret
= s
->cpu_ctlr
[cpu
];
466 if (s
->security_extn
&& !attrs
.secure
) {
467 /* Construct the NS banked view of GICC_CTLR from the correct
468 * bits of the S banked view. We don't need to move the bypass
469 * control bits because we don't implement that (IMPDEF) part
470 * of the GIC architecture.
472 ret
= (ret
& (GICC_CTLR_EN_GRP1
| GICC_CTLR_EOIMODE_NS
)) >> 1;
477 static void gic_set_cpu_control(GICState
*s
, int cpu
, uint32_t value
,
482 if (s
->security_extn
&& !attrs
.secure
) {
483 /* The NS view can only write certain bits in the register;
484 * the rest are unchanged
486 mask
= GICC_CTLR_EN_GRP1
;
487 if (s
->revision
== 2) {
488 mask
|= GICC_CTLR_EOIMODE_NS
;
490 s
->cpu_ctlr
[cpu
] &= ~mask
;
491 s
->cpu_ctlr
[cpu
] |= (value
<< 1) & mask
;
493 if (s
->revision
== 2) {
494 mask
= s
->security_extn
? GICC_CTLR_V2_S_MASK
: GICC_CTLR_V2_MASK
;
496 mask
= s
->security_extn
? GICC_CTLR_V1_S_MASK
: GICC_CTLR_V1_MASK
;
498 s
->cpu_ctlr
[cpu
] = value
& mask
;
500 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, "
501 "Group1 Interrupts %sabled\n", cpu
,
502 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP0
) ? "En" : "Dis",
503 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP1
) ? "En" : "Dis");
506 static uint8_t gic_get_running_priority(GICState
*s
, int cpu
, MemTxAttrs attrs
)
508 if ((s
->revision
!= REV_11MPCORE
) && (s
->running_priority
[cpu
] > 0xff)) {
513 if (s
->security_extn
&& !attrs
.secure
) {
514 if (s
->running_priority
[cpu
] & 0x80) {
515 /* Running priority in upper half of range: return the Non-secure
516 * view of the priority.
518 return s
->running_priority
[cpu
] << 1;
520 /* Running priority in lower half of range: RAZ */
524 return s
->running_priority
[cpu
];
528 /* Return true if we should split priority drop and interrupt deactivation,
529 * ie whether the relevant EOIMode bit is set.
531 static bool gic_eoi_split(GICState
*s
, int cpu
, MemTxAttrs attrs
)
533 if (s
->revision
!= 2) {
534 /* Before GICv2 prio-drop and deactivate are not separable */
537 if (s
->security_extn
&& !attrs
.secure
) {
538 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE_NS
;
540 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE
;
543 static void gic_deactivate_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
546 int group
= gic_has_groups(s
) && GIC_TEST_GROUP(irq
, cm
);
548 if (!gic_eoi_split(s
, cpu
, attrs
)) {
549 /* This is UNPREDICTABLE; we choose to ignore it */
550 qemu_log_mask(LOG_GUEST_ERROR
,
551 "gic_deactivate_irq: GICC_DIR write when EOIMode clear");
555 if (s
->security_extn
&& !attrs
.secure
&& !group
) {
556 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq
);
560 GIC_CLEAR_ACTIVE(irq
, cm
);
563 void gic_complete_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
568 DPRINTF("EOI %d\n", irq
);
569 if (irq
>= s
->num_irq
) {
570 /* This handles two cases:
571 * 1. If software writes the ID of a spurious interrupt [ie 1023]
572 * to the GICC_EOIR, the GIC ignores that write.
573 * 2. If software writes the number of a non-existent interrupt
574 * this must be a subcase of "value written does not match the last
575 * valid interrupt value read from the Interrupt Acknowledge
576 * register" and so this is UNPREDICTABLE. We choose to ignore it.
580 if (s
->running_priority
[cpu
] == 0x100) {
581 return; /* No active IRQ. */
584 if (s
->revision
== REV_11MPCORE
) {
585 /* Mark level triggered interrupts as pending if they are still
587 if (!GIC_TEST_EDGE_TRIGGER(irq
) && GIC_TEST_ENABLED(irq
, cm
)
588 && GIC_TEST_LEVEL(irq
, cm
) && (GIC_TARGET(irq
) & cm
) != 0) {
589 DPRINTF("Set %d pending mask %x\n", irq
, cm
);
590 GIC_SET_PENDING(irq
, cm
);
594 group
= gic_has_groups(s
) && GIC_TEST_GROUP(irq
, cm
);
596 if (s
->security_extn
&& !attrs
.secure
&& !group
) {
597 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq
);
601 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1
602 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1,
603 * i.e. go ahead and complete the irq anyway.
606 gic_drop_prio(s
, cpu
, group
);
608 /* In GICv2 the guest can choose to split priority-drop and deactivate */
609 if (!gic_eoi_split(s
, cpu
, attrs
)) {
610 GIC_CLEAR_ACTIVE(irq
, cm
);
615 static uint32_t gic_dist_readb(void *opaque
, hwaddr offset
, MemTxAttrs attrs
)
617 GICState
*s
= (GICState
*)opaque
;
625 cpu
= gic_get_current_cpu(s
);
627 if (offset
< 0x100) {
628 if (offset
== 0) { /* GICD_CTLR */
629 if (s
->security_extn
&& !attrs
.secure
) {
630 /* The NS bank of this register is just an alias of the
631 * EnableGrp1 bit in the S bank version.
633 return extract32(s
->ctlr
, 1, 1);
639 /* Interrupt Controller Type Register */
640 return ((s
->num_irq
/ 32) - 1)
641 | ((s
->num_cpu
- 1) << 5)
642 | (s
->security_extn
<< 10);
645 if (offset
>= 0x80) {
646 /* Interrupt Group Registers: these RAZ/WI if this is an NS
647 * access to a GIC with the security extensions, or if the GIC
648 * doesn't have groups at all.
651 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
652 /* Every byte offset holds 8 group status bits */
653 irq
= (offset
- 0x080) * 8 + GIC_BASE_IRQ
;
654 if (irq
>= s
->num_irq
) {
657 for (i
= 0; i
< 8; i
++) {
658 if (GIC_TEST_GROUP(irq
+ i
, cm
)) {
666 } else if (offset
< 0x200) {
667 /* Interrupt Set/Clear Enable. */
669 irq
= (offset
- 0x100) * 8;
671 irq
= (offset
- 0x180) * 8;
673 if (irq
>= s
->num_irq
)
676 for (i
= 0; i
< 8; i
++) {
677 if (s
->security_extn
&& !attrs
.secure
&&
678 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
679 continue; /* Ignore Non-secure access of Group0 IRQ */
682 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
686 } else if (offset
< 0x300) {
687 /* Interrupt Set/Clear Pending. */
689 irq
= (offset
- 0x200) * 8;
691 irq
= (offset
- 0x280) * 8;
693 if (irq
>= s
->num_irq
)
696 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
697 for (i
= 0; i
< 8; i
++) {
698 if (s
->security_extn
&& !attrs
.secure
&&
699 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
700 continue; /* Ignore Non-secure access of Group0 IRQ */
703 if (gic_test_pending(s
, irq
+ i
, mask
)) {
707 } else if (offset
< 0x400) {
708 /* Interrupt Active. */
709 irq
= (offset
- 0x300) * 8 + GIC_BASE_IRQ
;
710 if (irq
>= s
->num_irq
)
713 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
714 for (i
= 0; i
< 8; i
++) {
715 if (s
->security_extn
&& !attrs
.secure
&&
716 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
717 continue; /* Ignore Non-secure access of Group0 IRQ */
720 if (GIC_TEST_ACTIVE(irq
+ i
, mask
)) {
724 } else if (offset
< 0x800) {
725 /* Interrupt Priority. */
726 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
727 if (irq
>= s
->num_irq
)
729 res
= gic_get_priority(s
, cpu
, irq
, attrs
);
730 } else if (offset
< 0xc00) {
731 /* Interrupt CPU Target. */
732 if (s
->num_cpu
== 1 && s
->revision
!= REV_11MPCORE
) {
733 /* For uniprocessor GICs these RAZ/WI */
736 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
737 if (irq
>= s
->num_irq
) {
740 if (irq
>= 29 && irq
<= 31) {
743 res
= GIC_TARGET(irq
);
746 } else if (offset
< 0xf00) {
747 /* Interrupt Configuration. */
748 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
749 if (irq
>= s
->num_irq
)
752 for (i
= 0; i
< 4; i
++) {
753 if (s
->security_extn
&& !attrs
.secure
&&
754 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
755 continue; /* Ignore Non-secure access of Group0 IRQ */
758 if (GIC_TEST_MODEL(irq
+ i
))
759 res
|= (1 << (i
* 2));
760 if (GIC_TEST_EDGE_TRIGGER(irq
+ i
))
761 res
|= (2 << (i
* 2));
763 } else if (offset
< 0xf10) {
765 } else if (offset
< 0xf30) {
766 if (s
->revision
== REV_11MPCORE
) {
770 if (offset
< 0xf20) {
771 /* GICD_CPENDSGIRn */
772 irq
= (offset
- 0xf10);
774 irq
= (offset
- 0xf20);
775 /* GICD_SPENDSGIRn */
778 if (s
->security_extn
&& !attrs
.secure
&&
779 !GIC_TEST_GROUP(irq
, 1 << cpu
)) {
780 res
= 0; /* Ignore Non-secure access of Group0 IRQ */
782 res
= s
->sgi_pending
[irq
][cpu
];
784 } else if (offset
< 0xfd0) {
786 } else if (offset
< 0x1000) {
790 switch (s
->revision
) {
792 res
= gic_id_11mpcore
[(offset
- 0xfd0) >> 2];
795 res
= gic_id_gicv1
[(offset
- 0xfd0) >> 2];
798 res
= gic_id_gicv2
[(offset
- 0xfd0) >> 2];
805 g_assert_not_reached();
809 qemu_log_mask(LOG_GUEST_ERROR
,
810 "gic_dist_readb: Bad offset %x\n", (int)offset
);
814 static MemTxResult
gic_dist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
815 unsigned size
, MemTxAttrs attrs
)
819 *data
= gic_dist_readb(opaque
, offset
, attrs
);
822 *data
= gic_dist_readb(opaque
, offset
, attrs
);
823 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
826 *data
= gic_dist_readb(opaque
, offset
, attrs
);
827 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
828 *data
|= gic_dist_readb(opaque
, offset
+ 2, attrs
) << 16;
829 *data
|= gic_dist_readb(opaque
, offset
+ 3, attrs
) << 24;
836 static void gic_dist_writeb(void *opaque
, hwaddr offset
,
837 uint32_t value
, MemTxAttrs attrs
)
839 GICState
*s
= (GICState
*)opaque
;
844 cpu
= gic_get_current_cpu(s
);
845 if (offset
< 0x100) {
847 if (s
->security_extn
&& !attrs
.secure
) {
848 /* NS version is just an alias of the S version's bit 1 */
849 s
->ctlr
= deposit32(s
->ctlr
, 1, 1, value
);
850 } else if (gic_has_groups(s
)) {
851 s
->ctlr
= value
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
);
853 s
->ctlr
= value
& GICD_CTLR_EN_GRP0
;
855 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n",
856 s
->ctlr
& GICD_CTLR_EN_GRP0
? "En" : "Dis",
857 s
->ctlr
& GICD_CTLR_EN_GRP1
? "En" : "Dis");
858 } else if (offset
< 4) {
860 } else if (offset
>= 0x80) {
861 /* Interrupt Group Registers: RAZ/WI for NS access to secure
862 * GIC, or for GICs without groups.
864 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
865 /* Every byte offset holds 8 group status bits */
866 irq
= (offset
- 0x80) * 8 + GIC_BASE_IRQ
;
867 if (irq
>= s
->num_irq
) {
870 for (i
= 0; i
< 8; i
++) {
871 /* Group bits are banked for private interrupts */
872 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
873 if (value
& (1 << i
)) {
874 /* Group1 (Non-secure) */
875 GIC_SET_GROUP(irq
+ i
, cm
);
877 /* Group0 (Secure) */
878 GIC_CLEAR_GROUP(irq
+ i
, cm
);
885 } else if (offset
< 0x180) {
886 /* Interrupt Set Enable. */
887 irq
= (offset
- 0x100) * 8 + GIC_BASE_IRQ
;
888 if (irq
>= s
->num_irq
)
890 if (irq
< GIC_NR_SGIS
) {
894 for (i
= 0; i
< 8; i
++) {
895 if (value
& (1 << i
)) {
897 (irq
< GIC_INTERNAL
) ? (1 << cpu
) : GIC_TARGET(irq
+ i
);
898 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
900 if (s
->security_extn
&& !attrs
.secure
&&
901 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
902 continue; /* Ignore Non-secure access of Group0 IRQ */
905 if (!GIC_TEST_ENABLED(irq
+ i
, cm
)) {
906 DPRINTF("Enabled IRQ %d\n", irq
+ i
);
907 trace_gic_enable_irq(irq
+ i
);
909 GIC_SET_ENABLED(irq
+ i
, cm
);
910 /* If a raised level triggered IRQ enabled then mark
912 if (GIC_TEST_LEVEL(irq
+ i
, mask
)
913 && !GIC_TEST_EDGE_TRIGGER(irq
+ i
)) {
914 DPRINTF("Set %d pending mask %x\n", irq
+ i
, mask
);
915 GIC_SET_PENDING(irq
+ i
, mask
);
919 } else if (offset
< 0x200) {
920 /* Interrupt Clear Enable. */
921 irq
= (offset
- 0x180) * 8 + GIC_BASE_IRQ
;
922 if (irq
>= s
->num_irq
)
924 if (irq
< GIC_NR_SGIS
) {
928 for (i
= 0; i
< 8; i
++) {
929 if (value
& (1 << i
)) {
930 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
932 if (s
->security_extn
&& !attrs
.secure
&&
933 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
934 continue; /* Ignore Non-secure access of Group0 IRQ */
937 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
938 DPRINTF("Disabled IRQ %d\n", irq
+ i
);
939 trace_gic_disable_irq(irq
+ i
);
941 GIC_CLEAR_ENABLED(irq
+ i
, cm
);
944 } else if (offset
< 0x280) {
945 /* Interrupt Set Pending. */
946 irq
= (offset
- 0x200) * 8 + GIC_BASE_IRQ
;
947 if (irq
>= s
->num_irq
)
949 if (irq
< GIC_NR_SGIS
) {
953 for (i
= 0; i
< 8; i
++) {
954 if (value
& (1 << i
)) {
955 if (s
->security_extn
&& !attrs
.secure
&&
956 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
957 continue; /* Ignore Non-secure access of Group0 IRQ */
960 GIC_SET_PENDING(irq
+ i
, GIC_TARGET(irq
+ i
));
963 } else if (offset
< 0x300) {
964 /* Interrupt Clear Pending. */
965 irq
= (offset
- 0x280) * 8 + GIC_BASE_IRQ
;
966 if (irq
>= s
->num_irq
)
968 if (irq
< GIC_NR_SGIS
) {
972 for (i
= 0; i
< 8; i
++) {
973 if (s
->security_extn
&& !attrs
.secure
&&
974 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
975 continue; /* Ignore Non-secure access of Group0 IRQ */
978 /* ??? This currently clears the pending bit for all CPUs, even
979 for per-CPU interrupts. It's unclear whether this is the
981 if (value
& (1 << i
)) {
982 GIC_CLEAR_PENDING(irq
+ i
, ALL_CPU_MASK
);
985 } else if (offset
< 0x400) {
986 /* Interrupt Active. */
988 } else if (offset
< 0x800) {
989 /* Interrupt Priority. */
990 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
991 if (irq
>= s
->num_irq
)
993 gic_set_priority(s
, cpu
, irq
, value
, attrs
);
994 } else if (offset
< 0xc00) {
995 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
996 * annoying exception of the 11MPCore's GIC.
998 if (s
->num_cpu
!= 1 || s
->revision
== REV_11MPCORE
) {
999 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
1000 if (irq
>= s
->num_irq
) {
1005 } else if (irq
< GIC_INTERNAL
) {
1006 value
= ALL_CPU_MASK
;
1008 s
->irq_target
[irq
] = value
& ALL_CPU_MASK
;
1010 } else if (offset
< 0xf00) {
1011 /* Interrupt Configuration. */
1012 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
1013 if (irq
>= s
->num_irq
)
1015 if (irq
< GIC_NR_SGIS
)
1017 for (i
= 0; i
< 4; i
++) {
1018 if (s
->security_extn
&& !attrs
.secure
&&
1019 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1020 continue; /* Ignore Non-secure access of Group0 IRQ */
1023 if (s
->revision
== REV_11MPCORE
) {
1024 if (value
& (1 << (i
* 2))) {
1025 GIC_SET_MODEL(irq
+ i
);
1027 GIC_CLEAR_MODEL(irq
+ i
);
1030 if (value
& (2 << (i
* 2))) {
1031 GIC_SET_EDGE_TRIGGER(irq
+ i
);
1033 GIC_CLEAR_EDGE_TRIGGER(irq
+ i
);
1036 } else if (offset
< 0xf10) {
1037 /* 0xf00 is only handled for 32-bit writes. */
1039 } else if (offset
< 0xf20) {
1040 /* GICD_CPENDSGIRn */
1041 if (s
->revision
== REV_11MPCORE
) {
1044 irq
= (offset
- 0xf10);
1046 if (!s
->security_extn
|| attrs
.secure
||
1047 GIC_TEST_GROUP(irq
, 1 << cpu
)) {
1048 s
->sgi_pending
[irq
][cpu
] &= ~value
;
1049 if (s
->sgi_pending
[irq
][cpu
] == 0) {
1050 GIC_CLEAR_PENDING(irq
, 1 << cpu
);
1053 } else if (offset
< 0xf30) {
1054 /* GICD_SPENDSGIRn */
1055 if (s
->revision
== REV_11MPCORE
) {
1058 irq
= (offset
- 0xf20);
1060 if (!s
->security_extn
|| attrs
.secure
||
1061 GIC_TEST_GROUP(irq
, 1 << cpu
)) {
1062 GIC_SET_PENDING(irq
, 1 << cpu
);
1063 s
->sgi_pending
[irq
][cpu
] |= value
;
1071 qemu_log_mask(LOG_GUEST_ERROR
,
1072 "gic_dist_writeb: Bad offset %x\n", (int)offset
);
1075 static void gic_dist_writew(void *opaque
, hwaddr offset
,
1076 uint32_t value
, MemTxAttrs attrs
)
1078 gic_dist_writeb(opaque
, offset
, value
& 0xff, attrs
);
1079 gic_dist_writeb(opaque
, offset
+ 1, value
>> 8, attrs
);
1082 static void gic_dist_writel(void *opaque
, hwaddr offset
,
1083 uint32_t value
, MemTxAttrs attrs
)
1085 GICState
*s
= (GICState
*)opaque
;
1086 if (offset
== 0xf00) {
1092 cpu
= gic_get_current_cpu(s
);
1093 irq
= value
& 0x3ff;
1094 switch ((value
>> 24) & 3) {
1096 mask
= (value
>> 16) & ALL_CPU_MASK
;
1099 mask
= ALL_CPU_MASK
^ (1 << cpu
);
1105 DPRINTF("Bad Soft Int target filter\n");
1106 mask
= ALL_CPU_MASK
;
1109 GIC_SET_PENDING(irq
, mask
);
1110 target_cpu
= ctz32(mask
);
1111 while (target_cpu
< GIC_NCPU
) {
1112 s
->sgi_pending
[irq
][target_cpu
] |= (1 << cpu
);
1113 mask
&= ~(1 << target_cpu
);
1114 target_cpu
= ctz32(mask
);
1119 gic_dist_writew(opaque
, offset
, value
& 0xffff, attrs
);
1120 gic_dist_writew(opaque
, offset
+ 2, value
>> 16, attrs
);
1123 static MemTxResult
gic_dist_write(void *opaque
, hwaddr offset
, uint64_t data
,
1124 unsigned size
, MemTxAttrs attrs
)
1128 gic_dist_writeb(opaque
, offset
, data
, attrs
);
1131 gic_dist_writew(opaque
, offset
, data
, attrs
);
1134 gic_dist_writel(opaque
, offset
, data
, attrs
);
1141 static inline uint32_t gic_apr_ns_view(GICState
*s
, int cpu
, int regno
)
1143 /* Return the Nonsecure view of GICC_APR<regno>. This is the
1144 * second half of GICC_NSAPR.
1146 switch (GIC_MIN_BPR
) {
1149 return s
->nsapr
[regno
+ 2][cpu
];
1154 return s
->nsapr
[regno
+ 1][cpu
];
1159 return extract32(s
->nsapr
[0][cpu
], 16, 16);
1164 return extract32(s
->nsapr
[0][cpu
], 8, 8);
1168 g_assert_not_reached();
1173 static inline void gic_apr_write_ns_view(GICState
*s
, int cpu
, int regno
,
1176 /* Write the Nonsecure view of GICC_APR<regno>. */
1177 switch (GIC_MIN_BPR
) {
1180 s
->nsapr
[regno
+ 2][cpu
] = value
;
1185 s
->nsapr
[regno
+ 1][cpu
] = value
;
1190 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 16, 16, value
);
1195 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 8, 8, value
);
1199 g_assert_not_reached();
1203 static MemTxResult
gic_cpu_read(GICState
*s
, int cpu
, int offset
,
1204 uint64_t *data
, MemTxAttrs attrs
)
1207 case 0x00: /* Control */
1208 *data
= gic_get_cpu_control(s
, cpu
, attrs
);
1210 case 0x04: /* Priority mask */
1211 *data
= gic_get_priority_mask(s
, cpu
, attrs
);
1213 case 0x08: /* Binary Point */
1214 if (s
->security_extn
&& !attrs
.secure
) {
1215 if (s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) {
1216 /* NS view of BPR when CBPR is 1 */
1217 *data
= MIN(s
->bpr
[cpu
] + 1, 7);
1219 /* BPR is banked. Non-secure copy stored in ABPR. */
1220 *data
= s
->abpr
[cpu
];
1223 *data
= s
->bpr
[cpu
];
1226 case 0x0c: /* Acknowledge */
1227 *data
= gic_acknowledge_irq(s
, cpu
, attrs
);
1229 case 0x14: /* Running Priority */
1230 *data
= gic_get_running_priority(s
, cpu
, attrs
);
1232 case 0x18: /* Highest Pending Interrupt */
1233 *data
= gic_get_current_pending_irq(s
, cpu
, attrs
);
1235 case 0x1c: /* Aliased Binary Point */
1236 /* GIC v2, no security: ABPR
1237 * GIC v1, no security: not implemented (RAZ/WI)
1238 * With security extensions, secure access: ABPR (alias of NS BPR)
1239 * With security extensions, nonsecure access: RAZ/WI
1241 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1244 *data
= s
->abpr
[cpu
];
1247 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1249 int regno
= (offset
- 0xd0) / 4;
1251 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1253 } else if (s
->security_extn
&& !attrs
.secure
) {
1254 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1255 *data
= gic_apr_ns_view(s
, regno
, cpu
);
1257 *data
= s
->apr
[regno
][cpu
];
1261 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1263 int regno
= (offset
- 0xe0) / 4;
1265 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2 || !gic_has_groups(s
) ||
1266 (s
->security_extn
&& !attrs
.secure
)) {
1269 *data
= s
->nsapr
[regno
][cpu
];
1274 qemu_log_mask(LOG_GUEST_ERROR
,
1275 "gic_cpu_read: Bad offset %x\n", (int)offset
);
1282 static MemTxResult
gic_cpu_write(GICState
*s
, int cpu
, int offset
,
1283 uint32_t value
, MemTxAttrs attrs
)
1286 case 0x00: /* Control */
1287 gic_set_cpu_control(s
, cpu
, value
, attrs
);
1289 case 0x04: /* Priority mask */
1290 gic_set_priority_mask(s
, cpu
, value
, attrs
);
1292 case 0x08: /* Binary Point */
1293 if (s
->security_extn
&& !attrs
.secure
) {
1294 if (s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) {
1295 /* WI when CBPR is 1 */
1298 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1301 s
->bpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_BPR
);
1304 case 0x10: /* End Of Interrupt */
1305 gic_complete_irq(s
, cpu
, value
& 0x3ff, attrs
);
1307 case 0x1c: /* Aliased Binary Point */
1308 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1309 /* unimplemented, or NS access: RAZ/WI */
1312 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1315 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1317 int regno
= (offset
- 0xd0) / 4;
1319 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1322 if (s
->security_extn
&& !attrs
.secure
) {
1323 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1324 gic_apr_write_ns_view(s
, regno
, cpu
, value
);
1326 s
->apr
[regno
][cpu
] = value
;
1330 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1332 int regno
= (offset
- 0xe0) / 4;
1334 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1337 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1340 s
->nsapr
[regno
][cpu
] = value
;
1345 gic_deactivate_irq(s
, cpu
, value
& 0x3ff, attrs
);
1348 qemu_log_mask(LOG_GUEST_ERROR
,
1349 "gic_cpu_write: Bad offset %x\n", (int)offset
);
1356 /* Wrappers to read/write the GIC CPU interface for the current CPU */
1357 static MemTxResult
gic_thiscpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1358 unsigned size
, MemTxAttrs attrs
)
1360 GICState
*s
= (GICState
*)opaque
;
1361 return gic_cpu_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1364 static MemTxResult
gic_thiscpu_write(void *opaque
, hwaddr addr
,
1365 uint64_t value
, unsigned size
,
1368 GICState
*s
= (GICState
*)opaque
;
1369 return gic_cpu_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1372 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
1373 * These just decode the opaque pointer into GICState* + cpu id.
1375 static MemTxResult
gic_do_cpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1376 unsigned size
, MemTxAttrs attrs
)
1378 GICState
**backref
= (GICState
**)opaque
;
1379 GICState
*s
= *backref
;
1380 int id
= (backref
- s
->backref
);
1381 return gic_cpu_read(s
, id
, addr
, data
, attrs
);
1384 static MemTxResult
gic_do_cpu_write(void *opaque
, hwaddr addr
,
1385 uint64_t value
, unsigned size
,
1388 GICState
**backref
= (GICState
**)opaque
;
1389 GICState
*s
= *backref
;
1390 int id
= (backref
- s
->backref
);
1391 return gic_cpu_write(s
, id
, addr
, value
, attrs
);
1394 static const MemoryRegionOps gic_ops
[2] = {
1396 .read_with_attrs
= gic_dist_read
,
1397 .write_with_attrs
= gic_dist_write
,
1398 .endianness
= DEVICE_NATIVE_ENDIAN
,
1401 .read_with_attrs
= gic_thiscpu_read
,
1402 .write_with_attrs
= gic_thiscpu_write
,
1403 .endianness
= DEVICE_NATIVE_ENDIAN
,
1407 static const MemoryRegionOps gic_cpu_ops
= {
1408 .read_with_attrs
= gic_do_cpu_read
,
1409 .write_with_attrs
= gic_do_cpu_write
,
1410 .endianness
= DEVICE_NATIVE_ENDIAN
,
1413 /* This function is used by nvic model */
1414 void gic_init_irqs_and_distributor(GICState
*s
)
1416 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
);
1419 static void arm_gic_realize(DeviceState
*dev
, Error
**errp
)
1421 /* Device instance realize function for the GIC sysbus device */
1423 GICState
*s
= ARM_GIC(dev
);
1424 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1425 ARMGICClass
*agc
= ARM_GIC_GET_CLASS(s
);
1426 Error
*local_err
= NULL
;
1428 agc
->parent_realize(dev
, &local_err
);
1430 error_propagate(errp
, local_err
);
1434 if (kvm_enabled() && !kvm_arm_supports_user_irq()) {
1435 error_setg(errp
, "KVM with user space irqchip only works when the "
1436 "host kernel supports KVM_CAP_ARM_USER_IRQ");
1440 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */
1441 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
);
1443 /* Extra core-specific regions for the CPU interfaces. This is
1444 * necessary for "franken-GIC" implementations, for example on
1446 * NB that the memory region size of 0x100 applies for the 11MPCore
1447 * and also cores following the GIC v1 spec (ie A9).
1448 * GIC v2 defines a larger memory region (0x1000) so this will need
1449 * to be extended when we implement A15.
1451 for (i
= 0; i
< s
->num_cpu
; i
++) {
1453 memory_region_init_io(&s
->cpuiomem
[i
+1], OBJECT(s
), &gic_cpu_ops
,
1454 &s
->backref
[i
], "gic_cpu", 0x100);
1455 sysbus_init_mmio(sbd
, &s
->cpuiomem
[i
+1]);
1459 static void arm_gic_class_init(ObjectClass
*klass
, void *data
)
1461 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1462 ARMGICClass
*agc
= ARM_GIC_CLASS(klass
);
1464 device_class_set_parent_realize(dc
, arm_gic_realize
, &agc
->parent_realize
);
1467 static const TypeInfo arm_gic_info
= {
1468 .name
= TYPE_ARM_GIC
,
1469 .parent
= TYPE_ARM_GIC_COMMON
,
1470 .instance_size
= sizeof(GICState
),
1471 .class_init
= arm_gic_class_init
,
1472 .class_size
= sizeof(ARMGICClass
),
1475 static void arm_gic_register_types(void)
1477 type_register_static(&arm_gic_info
);
1480 type_init(arm_gic_register_types
)