hw/arm/bcm2836.c

   1 /*
   2  * Raspberry Pi emulation (c) 2012 Gregory Estrade
   3  * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
   4  *
   5  * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
   6  * Written by Andrew Baumann
   7  *
   8  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "qemu/module.h"
  15 #include "cpu.h"
  16 #include "hw/arm/bcm2836.h"
  17 #include "hw/arm/raspi_platform.h"
  18 #include "hw/sysbus.h"
  19
  20 typedef struct BCM283XClass {
  21     /*< private >*/
  22     DeviceClass parent_class;
  23     /*< public >*/
  24     const char *name;
  25     const char *cpu_type;
  26     unsigned core_count;
  27     hwaddr peri_base; /* Peripheral base address seen by the CPU */
  28     hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
  29     int clusterid;
  30 } BCM283XClass;
  31
  32 #define BCM283X_CLASS(klass) \
  33     OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
  34 #define BCM283X_GET_CLASS(obj) \
  35     OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
  36
  37 static Property bcm2836_enabled_cores_property =
  38     DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);
  39
  40 static void bcm2836_init(Object *obj)
  41 {
  42     BCM283XState *s = BCM283X(obj);
  43     BCM283XClass *bc = BCM283X_GET_CLASS(obj);
  44     int n;
  45
  46     for (n = 0; n < bc->core_count; n++) {
  47         object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
  48                                 bc->cpu_type);
  49     }
  50     if (bc->core_count > 1) {
  51         qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property);
  52         qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
  53     }
  54
  55     if (bc->ctrl_base) {
  56         object_initialize_child(obj, "control", &s->control,
  57                                 TYPE_BCM2836_CONTROL);
  58     }
  59
  60     object_initialize_child(obj, "peripherals", &s->peripherals,
  61                             TYPE_BCM2835_PERIPHERALS);
  62     object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals),
  63                               "board-rev");
  64     object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals),
  65                               "vcram-size");
  66 }
  67
  68 static bool bcm283x_common_realize(DeviceState *dev, Error **errp)
  69 {
  70     BCM283XState *s = BCM283X(dev);
  71     BCM283XClass *bc = BCM283X_GET_CLASS(dev);
  72     Object *obj;
  73
  74     /* common peripherals from bcm2835 */
  75
  76     obj = object_property_get_link(OBJECT(dev), "ram", &error_abort);
  77
  78     object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj);
  79
  80     if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) {
  81         return false;
  82     }
  83
  84     object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals),
  85                               "sd-bus");
  86
  87     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
  88                             bc->peri_base, 1);
  89     return true;
  90 }
  91
  92 static void bcm2835_realize(DeviceState *dev, Error **errp)
  93 {
  94     BCM283XState *s = BCM283X(dev);
  95
  96     if (!bcm283x_common_realize(dev, errp)) {
  97         return;
  98     }
  99
 100     if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) {
 101         return;
 102     }
 103
 104     /* Connect irq/fiq outputs from the interrupt controller. */
 105     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
 106             qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ));
 107     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
 108             qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ));
 109 }
 110
 111 static void bcm2836_realize(DeviceState *dev, Error **errp)
 112 {
 113     BCM283XState *s = BCM283X(dev);
 114     BCM283XClass *bc = BCM283X_GET_CLASS(dev);
 115     int n;
 116
 117     if (!bcm283x_common_realize(dev, errp)) {
 118         return;
 119     }
 120
 121     /* bcm2836 interrupt controller (and mailboxes, etc.) */
 122     if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) {
 123         return;
 124     }
 125
 126     sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base);
 127
 128     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
 129         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
 130     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
 131         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
 132
 133     for (n = 0; n < BCM283X_NCPUS; n++) {
 134         /* TODO: this should be converted to a property of ARM_CPU */
 135         s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n;
 136
 137         /* set periphbase/CBAR value for CPU-local registers */
 138         if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
 139                                      bc->peri_base, errp)) {
 140             return;
 141         }
 142
 143         /* start powered off if not enabled */
 144         if (!object_property_set_bool(OBJECT(&s->cpu[n].core),
 145                                       "start-powered-off",
 146                                       n >= s->enabled_cpus,
 147                                       errp)) {
 148             return;
 149         }
 150
 151         if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) {
 152             return;
 153         }
 154
 155         /* Connect irq/fiq outputs from the interrupt controller. */
 156         qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n,
 157                 qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ));
 158         qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n,
 159                 qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ));
 160
 161         /* Connect timers from the CPU to the interrupt controller */
 162         qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS,
 163                 qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n));
 164         qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT,
 165                 qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n));
 166         qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP,
 167                 qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n));
 168         qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC,
 169                 qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n));
 170     }
 171 }
 172
 173 static void bcm283x_class_init(ObjectClass *oc, void *data)
 174 {
 175     DeviceClass *dc = DEVICE_CLASS(oc);
 176
 177     /* Reason: Must be wired up in code (see raspi_init() function) */
 178     dc->user_creatable = false;
 179 }
 180
 181 static void bcm2835_class_init(ObjectClass *oc, void *data)
 182 {
 183     DeviceClass *dc = DEVICE_CLASS(oc);
 184     BCM283XClass *bc = BCM283X_CLASS(oc);
 185
 186     bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
 187     bc->core_count = 1;
 188     bc->peri_base = 0x20000000;
 189     dc->realize = bcm2835_realize;
 190 };
 191
 192 static void bcm2836_class_init(ObjectClass *oc, void *data)
 193 {
 194     DeviceClass *dc = DEVICE_CLASS(oc);
 195     BCM283XClass *bc = BCM283X_CLASS(oc);
 196
 197     bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
 198     bc->core_count = BCM283X_NCPUS;
 199     bc->peri_base = 0x3f000000;
 200     bc->ctrl_base = 0x40000000;
 201     bc->clusterid = 0xf;
 202     dc->realize = bcm2836_realize;
 203 };
 204
 205 #ifdef TARGET_AARCH64
 206 static void bcm2837_class_init(ObjectClass *oc, void *data)
 207 {
 208     DeviceClass *dc = DEVICE_CLASS(oc);
 209     BCM283XClass *bc = BCM283X_CLASS(oc);
 210
 211     bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
 212     bc->core_count = BCM283X_NCPUS;
 213     bc->peri_base = 0x3f000000;
 214     bc->ctrl_base = 0x40000000;
 215     bc->clusterid = 0x0;
 216     dc->realize = bcm2836_realize;
 217 };
 218 #endif
 219
 220 static const TypeInfo bcm283x_types[] = {
 221     {
 222         .name           = TYPE_BCM2835,
 223         .parent         = TYPE_BCM283X,
 224         .class_init     = bcm2835_class_init,
 225     }, {
 226         .name           = TYPE_BCM2836,
 227         .parent         = TYPE_BCM283X,
 228         .class_init     = bcm2836_class_init,
 229 #ifdef TARGET_AARCH64
 230     }, {
 231         .name           = TYPE_BCM2837,
 232         .parent         = TYPE_BCM283X,
 233         .class_init     = bcm2837_class_init,
 234 #endif
 235     }, {
 236         .name           = TYPE_BCM283X,
 237         .parent         = TYPE_DEVICE,
 238         .instance_size  = sizeof(BCM283XState),
 239         .instance_init  = bcm2836_init,
 240         .class_size     = sizeof(BCM283XClass),
 241         .class_init     = bcm283x_class_init,
 242         .abstract       = true,
 243     }
 244 };
 245
 246 DEFINE_TYPES(bcm283x_types)