hw/arm/bcm2836.c

   1 /*
   2  * Raspberry Pi emulation (c) 2012 Gregory Estrade
   3  * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
   4  *
   5  * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
   6  * Written by Andrew Baumann
   7  *
   8  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "qemu/module.h"
  15 #include "hw/arm/bcm2836.h"
  16 #include "hw/arm/raspi_platform.h"
  17 #include "hw/sysbus.h"
  18 #include "target/arm/cpu-qom.h"
  19 #include "target/arm/gtimer.h"
  20
  21 struct BCM283XClass {
  22     /*< private >*/
  23     DeviceClass parent_class;
  24     /*< public >*/
  25     const char *name;
  26     const char *cpu_type;
  27     unsigned core_count;
  28     hwaddr peri_base; /* Peripheral base address seen by the CPU */
  29     hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
  30     int clusterid;
  31 };
  32
  33 static Property bcm2836_enabled_cores_property =
  34     DEFINE_PROP_UINT32("enabled-cpus", BCM283XBaseState, enabled_cpus, 0);
  35
  36 static void bcm283x_base_init(Object *obj)
  37 {
  38     BCM283XBaseState *s = BCM283X_BASE(obj);
  39     BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(obj);
  40     int n;
  41
  42     for (n = 0; n < bc->core_count; n++) {
  43         object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
  44                                 bc->cpu_type);
  45     }
  46     if (bc->core_count > 1) {
  47         qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property);
  48         qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
  49     }
  50
  51     if (bc->ctrl_base) {
  52         object_initialize_child(obj, "control", &s->control,
  53                                 TYPE_BCM2836_CONTROL);
  54     }
  55 }
  56
  57 static void bcm283x_init(Object *obj)
  58 {
  59     BCM283XState *s = BCM283X(obj);
  60
  61     object_initialize_child(obj, "peripherals", &s->peripherals,
  62                             TYPE_BCM2835_PERIPHERALS);
  63     object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals),
  64                               "board-rev");
  65     object_property_add_alias(obj, "command-line", OBJECT(&s->peripherals),
  66                               "command-line");
  67     object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals),
  68                               "vcram-size");
  69     object_property_add_alias(obj, "vcram-base", OBJECT(&s->peripherals),
  70                               "vcram-base");
  71 }
  72
  73 bool bcm283x_common_realize(DeviceState *dev, BCMSocPeripheralBaseState *ps,
  74                             Error **errp)
  75 {
  76     BCM283XBaseState *s = BCM283X_BASE(dev);
  77     BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(dev);
  78     Object *obj;
  79
  80     /* common peripherals from bcm2835 */
  81
  82     obj = object_property_get_link(OBJECT(dev), "ram", &error_abort);
  83
  84     object_property_add_const_link(OBJECT(ps), "ram", obj);
  85
  86     if (!sysbus_realize(SYS_BUS_DEVICE(ps), errp)) {
  87         return false;
  88     }
  89
  90     object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(ps), "sd-bus");
  91
  92     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(ps), 0, bc->peri_base, 1);
  93     return true;
  94 }
  95
  96 static void bcm2835_realize(DeviceState *dev, Error **errp)
  97 {
  98     BCM283XState *s = BCM283X(dev);
  99     BCM283XBaseState *s_base = BCM283X_BASE(dev);
 100     BCMSocPeripheralBaseState *ps_base
 101         = BCM_SOC_PERIPHERALS_BASE(&s->peripherals);
 102
 103     if (!bcm283x_common_realize(dev, ps_base, errp)) {
 104         return;
 105     }
 106
 107     if (!qdev_realize(DEVICE(&s_base->cpu[0].core), NULL, errp)) {
 108         return;
 109     }
 110
 111     /* Connect irq/fiq outputs from the interrupt controller. */
 112     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
 113             qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_IRQ));
 114     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
 115             qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_FIQ));
 116 }
 117
 118 static void bcm2836_realize(DeviceState *dev, Error **errp)
 119 {
 120     int n;
 121     BCM283XState *s = BCM283X(dev);
 122     BCM283XBaseState *s_base = BCM283X_BASE(dev);
 123     BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(dev);
 124     BCMSocPeripheralBaseState *ps_base
 125         = BCM_SOC_PERIPHERALS_BASE(&s->peripherals);
 126
 127     if (!bcm283x_common_realize(dev, ps_base, errp)) {
 128         return;
 129     }
 130
 131     /* bcm2836 interrupt controller (and mailboxes, etc.) */
 132     if (!sysbus_realize(SYS_BUS_DEVICE(&s_base->control), errp)) {
 133         return;
 134     }
 135
 136     sysbus_mmio_map(SYS_BUS_DEVICE(&s_base->control), 0, bc->ctrl_base);
 137
 138     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
 139         qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-irq", 0));
 140     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
 141         qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-fiq", 0));
 142
 143     for (n = 0; n < BCM283X_NCPUS; n++) {
 144         object_property_set_int(OBJECT(&s_base->cpu[n].core), "mp-affinity",
 145                                 (bc->clusterid << 8) | n, &error_abort);
 146
 147         /* set periphbase/CBAR value for CPU-local registers */
 148         object_property_set_int(OBJECT(&s_base->cpu[n].core), "reset-cbar",
 149                                 bc->peri_base, &error_abort);
 150
 151         /* start powered off if not enabled */
 152         object_property_set_bool(OBJECT(&s_base->cpu[n].core),
 153                                  "start-powered-off",
 154                                  n >= s_base->enabled_cpus, &error_abort);
 155
 156         if (!qdev_realize(DEVICE(&s_base->cpu[n].core), NULL, errp)) {
 157             return;
 158         }
 159
 160         /* Connect irq/fiq outputs from the interrupt controller. */
 161         qdev_connect_gpio_out_named(DEVICE(&s_base->control), "irq", n,
 162             qdev_get_gpio_in(DEVICE(&s_base->cpu[n].core), ARM_CPU_IRQ));
 163         qdev_connect_gpio_out_named(DEVICE(&s_base->control), "fiq", n,
 164             qdev_get_gpio_in(DEVICE(&s_base->cpu[n].core), ARM_CPU_FIQ));
 165
 166         /* Connect timers from the CPU to the interrupt controller */
 167         qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_PHYS,
 168             qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntpnsirq", n));
 169         qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_VIRT,
 170             qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntvirq", n));
 171         qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_HYP,
 172             qdev_get_gpio_in_named(DEVICE(&s_base->control), "cnthpirq", n));
 173         qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_SEC,
 174             qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntpsirq", n));
 175     }
 176 }
 177
 178 static void bcm283x_base_class_init(ObjectClass *oc, void *data)
 179 {
 180     DeviceClass *dc = DEVICE_CLASS(oc);
 181
 182     /* Reason: Must be wired up in code (see raspi_init() function) */
 183     dc->user_creatable = false;
 184 }
 185
 186 static void bcm2835_class_init(ObjectClass *oc, void *data)
 187 {
 188     DeviceClass *dc = DEVICE_CLASS(oc);
 189     BCM283XBaseClass *bc = BCM283X_BASE_CLASS(oc);
 190
 191     bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
 192     bc->core_count = 1;
 193     bc->peri_base = 0x20000000;
 194     dc->realize = bcm2835_realize;
 195 };
 196
 197 static void bcm2836_class_init(ObjectClass *oc, void *data)
 198 {
 199     DeviceClass *dc = DEVICE_CLASS(oc);
 200     BCM283XBaseClass *bc = BCM283X_BASE_CLASS(oc);
 201
 202     bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
 203     bc->core_count = BCM283X_NCPUS;
 204     bc->peri_base = 0x3f000000;
 205     bc->ctrl_base = 0x40000000;
 206     bc->clusterid = 0xf;
 207     dc->realize = bcm2836_realize;
 208 };
 209
 210 #ifdef TARGET_AARCH64
 211 static void bcm2837_class_init(ObjectClass *oc, void *data)
 212 {
 213     DeviceClass *dc = DEVICE_CLASS(oc);
 214     BCM283XBaseClass *bc = BCM283X_BASE_CLASS(oc);
 215
 216     bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
 217     bc->core_count = BCM283X_NCPUS;
 218     bc->peri_base = 0x3f000000;
 219     bc->ctrl_base = 0x40000000;
 220     bc->clusterid = 0x0;
 221     dc->realize = bcm2836_realize;
 222 };
 223 #endif
 224
 225 static const TypeInfo bcm283x_types[] = {
 226     {
 227         .name           = TYPE_BCM2835,
 228         .parent         = TYPE_BCM283X,
 229         .class_init     = bcm2835_class_init,
 230     }, {
 231         .name           = TYPE_BCM2836,
 232         .parent         = TYPE_BCM283X,
 233         .class_init     = bcm2836_class_init,
 234 #ifdef TARGET_AARCH64
 235     }, {
 236         .name           = TYPE_BCM2837,
 237         .parent         = TYPE_BCM283X,
 238         .class_init     = bcm2837_class_init,
 239 #endif
 240     }, {
 241         .name           = TYPE_BCM283X,
 242         .parent         = TYPE_BCM283X_BASE,
 243         .instance_size  = sizeof(BCM283XState),
 244         .instance_init  = bcm283x_init,
 245         .abstract       = true,
 246     }, {
 247         .name           = TYPE_BCM283X_BASE,
 248         .parent         = TYPE_DEVICE,
 249         .instance_size  = sizeof(BCM283XBaseState),
 250         .instance_init  = bcm283x_base_init,
 251         .class_size     = sizeof(BCM283XBaseClass),
 252         .class_init     = bcm283x_base_class_init,
 253         .abstract       = true,
 254     }
 255 };
 256
 257 DEFINE_TYPES(bcm283x_types)