hw/ppc/pnv.c

   1 /*
   2  * QEMU PowerPC PowerNV machine model
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "sysemu/sysemu.h"
  23 #include "sysemu/numa.h"
  24 #include "sysemu/cpus.h"
  25 #include "hw/hw.h"
  26 #include "target/ppc/cpu.h"
  27 #include "qemu/log.h"
  28 #include "hw/ppc/fdt.h"
  29 #include "hw/ppc/ppc.h"
  30 #include "hw/ppc/pnv.h"
  31 #include "hw/ppc/pnv_core.h"
  32 #include "hw/loader.h"
  33 #include "exec/address-spaces.h"
  34 #include "qemu/cutils.h"
  35 #include "qapi/visitor.h"
  36
  37 #include "hw/ppc/xics.h"
  38 #include "hw/ppc/pnv_xscom.h"
  39
  40 #include "hw/isa/isa.h"
  41 #include "hw/char/serial.h"
  42 #include "hw/timer/mc146818rtc.h"
  43
  44 #include <libfdt.h>
  45
  46 #define FDT_MAX_SIZE            0x00100000
  47
  48 #define FW_FILE_NAME            "skiboot.lid"
  49 #define FW_LOAD_ADDR            0x0
  50 #define FW_MAX_SIZE             0x00400000
  51
  52 #define KERNEL_LOAD_ADDR        0x20000000
  53 #define INITRD_LOAD_ADDR        0x40000000
  54
  55 /*
  56  * On Power Systems E880 (POWER8), the max cpus (threads) should be :
  57  *     4 * 4 sockets * 12 cores * 8 threads = 1536
  58  * Let's make it 2^11
  59  */
  60 #define MAX_CPUS                2048
  61
  62 /*
  63  * Memory nodes are created by hostboot, one for each range of memory
  64  * that has a different "affinity". In practice, it means one range
  65  * per chip.
  66  */
  67 static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start,
  68                                          hwaddr size)
  69 {
  70     char *mem_name;
  71     uint64_t mem_reg_property[2];
  72     int off;
  73
  74     mem_reg_property[0] = cpu_to_be64(start);
  75     mem_reg_property[1] = cpu_to_be64(size);
  76
  77     mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
  78     off = fdt_add_subnode(fdt, 0, mem_name);
  79     g_free(mem_name);
  80
  81     _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
  82     _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
  83                        sizeof(mem_reg_property))));
  84     _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
  85 }
  86
  87 static int get_cpus_node(void *fdt)
  88 {
  89     int cpus_offset = fdt_path_offset(fdt, "/cpus");
  90
  91     if (cpus_offset < 0) {
  92         cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
  93                                       "cpus");
  94         if (cpus_offset) {
  95             _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
  96             _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
  97         }
  98     }
  99     _FDT(cpus_offset);
 100     return cpus_offset;
 101 }
 102
 103 /*
 104  * The PowerNV cores (and threads) need to use real HW ids and not an
 105  * incremental index like it has been done on other platforms. This HW
 106  * id is stored in the CPU PIR, it is used to create cpu nodes in the
 107  * device tree, used in XSCOM to address cores and in interrupt
 108  * servers.
 109  */
 110 static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt)
 111 {
 112     CPUState *cs = CPU(DEVICE(pc->threads));
 113     DeviceClass *dc = DEVICE_GET_CLASS(cs);
 114     PowerPCCPU *cpu = POWERPC_CPU(cs);
 115     int smt_threads = CPU_CORE(pc)->nr_threads;
 116     CPUPPCState *env = &cpu->env;
 117     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
 118     uint32_t servers_prop[smt_threads];
 119     int i;
 120     uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
 121                        0xffffffff, 0xffffffff};
 122     uint32_t tbfreq = PNV_TIMEBASE_FREQ;
 123     uint32_t cpufreq = 1000000000;
 124     uint32_t page_sizes_prop[64];
 125     size_t page_sizes_prop_size;
 126     const uint8_t pa_features[] = { 24, 0,
 127                                     0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
 128                                     0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
 129                                     0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
 130                                     0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
 131     int offset;
 132     char *nodename;
 133     int cpus_offset = get_cpus_node(fdt);
 134
 135     nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
 136     offset = fdt_add_subnode(fdt, cpus_offset, nodename);
 137     _FDT(offset);
 138     g_free(nodename);
 139
 140     _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
 141
 142     _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
 143     _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
 144     _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
 145
 146     _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
 147     _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
 148                             env->dcache_line_size)));
 149     _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
 150                             env->dcache_line_size)));
 151     _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
 152                             env->icache_line_size)));
 153     _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
 154                             env->icache_line_size)));
 155
 156     if (pcc->l1_dcache_size) {
 157         _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
 158                                pcc->l1_dcache_size)));
 159     } else {
 160         error_report("Warning: Unknown L1 dcache size for cpu");
 161     }
 162     if (pcc->l1_icache_size) {
 163         _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
 164                                pcc->l1_icache_size)));
 165     } else {
 166         error_report("Warning: Unknown L1 icache size for cpu");
 167     }
 168
 169     _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
 170     _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
 171     _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
 172     _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
 173     _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
 174
 175     if (env->spr_cb[SPR_PURR].oea_read) {
 176         _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
 177     }
 178
 179     if (env->mmu_model & POWERPC_MMU_1TSEG) {
 180         _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
 181                            segs, sizeof(segs))));
 182     }
 183
 184     /* Advertise VMX/VSX (vector extensions) if available
 185      *   0 / no property == no vector extensions
 186      *   1               == VMX / Altivec available
 187      *   2               == VSX available */
 188     if (env->insns_flags & PPC_ALTIVEC) {
 189         uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
 190
 191         _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
 192     }
 193
 194     /* Advertise DFP (Decimal Floating Point) if available
 195      *   0 / no property == no DFP
 196      *   1               == DFP available */
 197     if (env->insns_flags2 & PPC2_DFP) {
 198         _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
 199     }
 200
 201     page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
 202                                                   sizeof(page_sizes_prop));
 203     if (page_sizes_prop_size) {
 204         _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
 205                            page_sizes_prop, page_sizes_prop_size)));
 206     }
 207
 208     _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
 209                        pa_features, sizeof(pa_features))));
 210
 211     /* Build interrupt servers properties */
 212     for (i = 0; i < smt_threads; i++) {
 213         servers_prop[i] = cpu_to_be32(pc->pir + i);
 214     }
 215     _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
 216                        servers_prop, sizeof(servers_prop))));
 217 }
 218
 219 static void powernv_populate_chip(PnvChip *chip, void *fdt)
 220 {
 221     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 222     char *typename = pnv_core_typename(pcc->cpu_model);
 223     size_t typesize = object_type_get_instance_size(typename);
 224     int i;
 225
 226     pnv_xscom_populate(chip, fdt, 0);
 227
 228     for (i = 0; i < chip->nr_cores; i++) {
 229         PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
 230
 231         powernv_create_core_node(chip, pnv_core, fdt);
 232     }
 233
 234     if (chip->ram_size) {
 235         powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start,
 236                                      chip->ram_size);
 237     }
 238     g_free(typename);
 239 }
 240
 241 static void *powernv_create_fdt(MachineState *machine)
 242 {
 243     const char plat_compat[] = "qemu,powernv\0ibm,powernv";
 244     PnvMachineState *pnv = POWERNV_MACHINE(machine);
 245     void *fdt;
 246     char *buf;
 247     int off;
 248     int i;
 249
 250     fdt = g_malloc0(FDT_MAX_SIZE);
 251     _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
 252
 253     /* Root node */
 254     _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
 255     _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
 256     _FDT((fdt_setprop_string(fdt, 0, "model",
 257                              "IBM PowerNV (emulated by qemu)")));
 258     _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat,
 259                       sizeof(plat_compat))));
 260
 261     buf =  qemu_uuid_unparse_strdup(&qemu_uuid);
 262     _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
 263     if (qemu_uuid_set) {
 264         _FDT((fdt_property_string(fdt, "system-id", buf)));
 265     }
 266     g_free(buf);
 267
 268     off = fdt_add_subnode(fdt, 0, "chosen");
 269     if (machine->kernel_cmdline) {
 270         _FDT((fdt_setprop_string(fdt, off, "bootargs",
 271                                  machine->kernel_cmdline)));
 272     }
 273
 274     if (pnv->initrd_size) {
 275         uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
 276         uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
 277
 278         _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
 279                                &start_prop, sizeof(start_prop))));
 280         _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
 281                                &end_prop, sizeof(end_prop))));
 282     }
 283
 284     /* Populate device tree for each chip */
 285     for (i = 0; i < pnv->num_chips; i++) {
 286         powernv_populate_chip(pnv->chips[i], fdt);
 287     }
 288     return fdt;
 289 }
 290
 291 static void ppc_powernv_reset(void)
 292 {
 293     MachineState *machine = MACHINE(qdev_get_machine());
 294     void *fdt;
 295
 296     qemu_devices_reset();
 297
 298     fdt = powernv_create_fdt(machine);
 299
 300     /* Pack resulting tree */
 301     _FDT((fdt_pack(fdt)));
 302
 303     cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
 304 }
 305
 306 /* If we don't use the built-in LPC interrupt deserializer, we need
 307  * to provide a set of qirqs for the ISA bus or things will go bad.
 308  *
 309  * Most machines using pre-Naples chips (without said deserializer)
 310  * have a CPLD that will collect the SerIRQ and shoot them as a
 311  * single level interrupt to the P8 chip. So let's setup a hook
 312  * for doing just that.
 313  *
 314  * Note: The actual interrupt input isn't emulated yet, this will
 315  * come with the PSI bridge model.
 316  */
 317 static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
 318 {
 319     /* We don't yet emulate the PSI bridge which provides the external
 320      * interrupt, so just drop interrupts on the floor
 321      */
 322 }
 323
 324 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
 325 {
 326      /* XXX TODO */
 327 }
 328
 329 static ISABus *pnv_isa_create(PnvChip *chip)
 330 {
 331     PnvLpcController *lpc = &chip->lpc;
 332     ISABus *isa_bus;
 333     qemu_irq *irqs;
 334     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 335
 336     /* let isa_bus_new() create its own bridge on SysBus otherwise
 337      * devices speficied on the command line won't find the bus and
 338      * will fail to create.
 339      */
 340     isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io,
 341                           &error_fatal);
 342
 343     /* Not all variants have a working serial irq decoder. If not,
 344      * handling of LPC interrupts becomes a platform issue (some
 345      * platforms have a CPLD to do it).
 346      */
 347     if (pcc->chip_type == PNV_CHIP_POWER8NVL) {
 348         irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler, chip, ISA_NUM_IRQS);
 349     } else {
 350         irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, chip,
 351                                   ISA_NUM_IRQS);
 352     }
 353
 354     isa_bus_irqs(isa_bus, irqs);
 355     return isa_bus;
 356 }
 357
 358 static void ppc_powernv_init(MachineState *machine)
 359 {
 360     PnvMachineState *pnv = POWERNV_MACHINE(machine);
 361     MemoryRegion *ram;
 362     char *fw_filename;
 363     long fw_size;
 364     int i;
 365     char *chip_typename;
 366
 367     /* allocate RAM */
 368     if (machine->ram_size < (1 * G_BYTE)) {
 369         error_report("Warning: skiboot may not work with < 1GB of RAM");
 370     }
 371
 372     ram = g_new(MemoryRegion, 1);
 373     memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram",
 374                                          machine->ram_size);
 375     memory_region_add_subregion(get_system_memory(), 0, ram);
 376
 377     /* load skiboot firmware  */
 378     if (bios_name == NULL) {
 379         bios_name = FW_FILE_NAME;
 380     }
 381
 382     fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 383
 384     fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
 385     if (fw_size < 0) {
 386         error_report("Could not load OPAL '%s'", fw_filename);
 387         exit(1);
 388     }
 389     g_free(fw_filename);
 390
 391     /* load kernel */
 392     if (machine->kernel_filename) {
 393         long kernel_size;
 394
 395         kernel_size = load_image_targphys(machine->kernel_filename,
 396                                           KERNEL_LOAD_ADDR, 0x2000000);
 397         if (kernel_size < 0) {
 398             error_report("Could not load kernel '%s'",
 399                          machine->kernel_filename);
 400             exit(1);
 401         }
 402     }
 403
 404     /* load initrd */
 405     if (machine->initrd_filename) {
 406         pnv->initrd_base = INITRD_LOAD_ADDR;
 407         pnv->initrd_size = load_image_targphys(machine->initrd_filename,
 408                                   pnv->initrd_base, 0x10000000); /* 128MB max */
 409         if (pnv->initrd_size < 0) {
 410             error_report("Could not load initial ram disk '%s'",
 411                          machine->initrd_filename);
 412             exit(1);
 413         }
 414     }
 415
 416     /* We need some cpu model to instantiate the PnvChip class */
 417     if (machine->cpu_model == NULL) {
 418         machine->cpu_model = "POWER8";
 419     }
 420
 421     /* Create the processor chips */
 422     chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model);
 423     if (!object_class_by_name(chip_typename)) {
 424         error_report("qemu: invalid CPU model '%s' for %s machine",
 425                      machine->cpu_model, MACHINE_GET_CLASS(machine)->name);
 426         exit(1);
 427     }
 428
 429     pnv->chips = g_new0(PnvChip *, pnv->num_chips);
 430     for (i = 0; i < pnv->num_chips; i++) {
 431         char chip_name[32];
 432         Object *chip = object_new(chip_typename);
 433
 434         pnv->chips[i] = PNV_CHIP(chip);
 435
 436         /* TODO: put all the memory in one node on chip 0 until we find a
 437          * way to specify different ranges for each chip
 438          */
 439         if (i == 0) {
 440             object_property_set_int(chip, machine->ram_size, "ram-size",
 441                                     &error_fatal);
 442         }
 443
 444         snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
 445         object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
 446         object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
 447                                 &error_fatal);
 448         object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
 449         object_property_set_bool(chip, true, "realized", &error_fatal);
 450     }
 451     g_free(chip_typename);
 452
 453     /* Instantiate ISA bus on chip 0 */
 454     pnv->isa_bus = pnv_isa_create(pnv->chips[0]);
 455
 456     /* Create serial port */
 457     serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS);
 458
 459     /* Create an RTC ISA device too */
 460     rtc_init(pnv->isa_bus, 2000, NULL);
 461 }
 462
 463 /*
 464  *    0:21  Reserved - Read as zeros
 465  *   22:24  Chip ID
 466  *   25:28  Core number
 467  *   29:31  Thread ID
 468  */
 469 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
 470 {
 471     return (chip->chip_id << 7) | (core_id << 3);
 472 }
 473
 474 /*
 475  *    0:48  Reserved - Read as zeroes
 476  *   49:52  Node ID
 477  *   53:55  Chip ID
 478  *   56     Reserved - Read as zero
 479  *   57:61  Core number
 480  *   62:63  Thread ID
 481  *
 482  * We only care about the lower bits. uint32_t is fine for the moment.
 483  */
 484 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
 485 {
 486     return (chip->chip_id << 8) | (core_id << 2);
 487 }
 488
 489 /* Allowed core identifiers on a POWER8 Processor Chip :
 490  *
 491  * <EX0 reserved>
 492  *  EX1  - Venice only
 493  *  EX2  - Venice only
 494  *  EX3  - Venice only
 495  *  EX4
 496  *  EX5
 497  *  EX6
 498  * <EX7,8 reserved> <reserved>
 499  *  EX9  - Venice only
 500  *  EX10 - Venice only
 501  *  EX11 - Venice only
 502  *  EX12
 503  *  EX13
 504  *  EX14
 505  * <EX15 reserved>
 506  */
 507 #define POWER8E_CORE_MASK  (0x7070ull)
 508 #define POWER8_CORE_MASK   (0x7e7eull)
 509
 510 /*
 511  * POWER9 has 24 cores, ids starting at 0x20
 512  */
 513 #define POWER9_CORE_MASK   (0xffffff00000000ull)
 514
 515 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
 516 {
 517     DeviceClass *dc = DEVICE_CLASS(klass);
 518     PnvChipClass *k = PNV_CHIP_CLASS(klass);
 519
 520     k->cpu_model = "POWER8E";
 521     k->chip_type = PNV_CHIP_POWER8E;
 522     k->chip_cfam_id = 0x221ef04980000000ull;  /* P8 Murano DD2.1 */
 523     k->cores_mask = POWER8E_CORE_MASK;
 524     k->core_pir = pnv_chip_core_pir_p8;
 525     k->xscom_base = 0x003fc0000000000ull;
 526     k->xscom_core_base = 0x10000000ull;
 527     dc->desc = "PowerNV Chip POWER8E";
 528 }
 529
 530 static const TypeInfo pnv_chip_power8e_info = {
 531     .name          = TYPE_PNV_CHIP_POWER8E,
 532     .parent        = TYPE_PNV_CHIP,
 533     .instance_size = sizeof(PnvChip),
 534     .class_init    = pnv_chip_power8e_class_init,
 535 };
 536
 537 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
 538 {
 539     DeviceClass *dc = DEVICE_CLASS(klass);
 540     PnvChipClass *k = PNV_CHIP_CLASS(klass);
 541
 542     k->cpu_model = "POWER8";
 543     k->chip_type = PNV_CHIP_POWER8;
 544     k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
 545     k->cores_mask = POWER8_CORE_MASK;
 546     k->core_pir = pnv_chip_core_pir_p8;
 547     k->xscom_base = 0x003fc0000000000ull;
 548     k->xscom_core_base = 0x10000000ull;
 549     dc->desc = "PowerNV Chip POWER8";
 550 }
 551
 552 static const TypeInfo pnv_chip_power8_info = {
 553     .name          = TYPE_PNV_CHIP_POWER8,
 554     .parent        = TYPE_PNV_CHIP,
 555     .instance_size = sizeof(PnvChip),
 556     .class_init    = pnv_chip_power8_class_init,
 557 };
 558
 559 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
 560 {
 561     DeviceClass *dc = DEVICE_CLASS(klass);
 562     PnvChipClass *k = PNV_CHIP_CLASS(klass);
 563
 564     k->cpu_model = "POWER8NVL";
 565     k->chip_type = PNV_CHIP_POWER8NVL;
 566     k->chip_cfam_id = 0x120d304980000000ull;  /* P8 Naples DD1.0 */
 567     k->cores_mask = POWER8_CORE_MASK;
 568     k->core_pir = pnv_chip_core_pir_p8;
 569     k->xscom_base = 0x003fc0000000000ull;
 570     k->xscom_core_base = 0x10000000ull;
 571     dc->desc = "PowerNV Chip POWER8NVL";
 572 }
 573
 574 static const TypeInfo pnv_chip_power8nvl_info = {
 575     .name          = TYPE_PNV_CHIP_POWER8NVL,
 576     .parent        = TYPE_PNV_CHIP,
 577     .instance_size = sizeof(PnvChip),
 578     .class_init    = pnv_chip_power8nvl_class_init,
 579 };
 580
 581 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
 582 {
 583     DeviceClass *dc = DEVICE_CLASS(klass);
 584     PnvChipClass *k = PNV_CHIP_CLASS(klass);
 585
 586     k->cpu_model = "POWER9";
 587     k->chip_type = PNV_CHIP_POWER9;
 588     k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
 589     k->cores_mask = POWER9_CORE_MASK;
 590     k->core_pir = pnv_chip_core_pir_p9;
 591     k->xscom_base = 0x00603fc00000000ull;
 592     k->xscom_core_base = 0x0ull;
 593     dc->desc = "PowerNV Chip POWER9";
 594 }
 595
 596 static const TypeInfo pnv_chip_power9_info = {
 597     .name          = TYPE_PNV_CHIP_POWER9,
 598     .parent        = TYPE_PNV_CHIP,
 599     .instance_size = sizeof(PnvChip),
 600     .class_init    = pnv_chip_power9_class_init,
 601 };
 602
 603 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
 604 {
 605     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 606     int cores_max;
 607
 608     /*
 609      * No custom mask for this chip, let's use the default one from *
 610      * the chip class
 611      */
 612     if (!chip->cores_mask) {
 613         chip->cores_mask = pcc->cores_mask;
 614     }
 615
 616     /* filter alien core ids ! some are reserved */
 617     if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
 618         error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
 619                    chip->cores_mask);
 620         return;
 621     }
 622     chip->cores_mask &= pcc->cores_mask;
 623
 624     /* now that we have a sane layout, let check the number of cores */
 625     cores_max = ctpop64(chip->cores_mask);
 626     if (chip->nr_cores > cores_max) {
 627         error_setg(errp, "warning: too many cores for chip ! Limit is %d",
 628                    cores_max);
 629         return;
 630     }
 631 }
 632
 633 static void pnv_chip_init(Object *obj)
 634 {
 635     PnvChip *chip = PNV_CHIP(obj);
 636     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 637
 638     chip->xscom_base = pcc->xscom_base;
 639
 640     object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
 641     object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
 642 }
 643
 644 static void pnv_chip_realize(DeviceState *dev, Error **errp)
 645 {
 646     PnvChip *chip = PNV_CHIP(dev);
 647     Error *error = NULL;
 648     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 649     char *typename = pnv_core_typename(pcc->cpu_model);
 650     size_t typesize = object_type_get_instance_size(typename);
 651     int i, core_hwid;
 652
 653     if (!object_class_by_name(typename)) {
 654         error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
 655         return;
 656     }
 657
 658     /* XSCOM bridge */
 659     pnv_xscom_realize(chip, &error);
 660     if (error) {
 661         error_propagate(errp, error);
 662         return;
 663     }
 664     sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
 665
 666     /* Cores */
 667     pnv_chip_core_sanitize(chip, &error);
 668     if (error) {
 669         error_propagate(errp, error);
 670         return;
 671     }
 672
 673     chip->cores = g_malloc0(typesize * chip->nr_cores);
 674
 675     for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
 676              && (i < chip->nr_cores); core_hwid++) {
 677         char core_name[32];
 678         void *pnv_core = chip->cores + i * typesize;
 679
 680         if (!(chip->cores_mask & (1ull << core_hwid))) {
 681             continue;
 682         }
 683
 684         object_initialize(pnv_core, typesize, typename);
 685         snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
 686         object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
 687                                   &error_fatal);
 688         object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
 689                                 &error_fatal);
 690         object_property_set_int(OBJECT(pnv_core), core_hwid,
 691                                 CPU_CORE_PROP_CORE_ID, &error_fatal);
 692         object_property_set_int(OBJECT(pnv_core),
 693                                 pcc->core_pir(chip, core_hwid),
 694                                 "pir", &error_fatal);
 695         object_property_set_bool(OBJECT(pnv_core), true, "realized",
 696                                  &error_fatal);
 697         object_unref(OBJECT(pnv_core));
 698
 699         /* Each core has an XSCOM MMIO region */
 700         pnv_xscom_add_subregion(chip,
 701                                 PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base,
 702                                                        core_hwid),
 703                                 &PNV_CORE(pnv_core)->xscom_regs);
 704         i++;
 705     }
 706     g_free(typename);
 707
 708     /* Create LPC controller */
 709     object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
 710                              &error_fatal);
 711     pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs);
 712 }
 713
 714 static Property pnv_chip_properties[] = {
 715     DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
 716     DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
 717     DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
 718     DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
 719     DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
 720     DEFINE_PROP_END_OF_LIST(),
 721 };
 722
 723 static void pnv_chip_class_init(ObjectClass *klass, void *data)
 724 {
 725     DeviceClass *dc = DEVICE_CLASS(klass);
 726
 727     set_bit(DEVICE_CATEGORY_CPU, dc->categories);
 728     dc->realize = pnv_chip_realize;
 729     dc->props = pnv_chip_properties;
 730     dc->desc = "PowerNV Chip";
 731 }
 732
 733 static const TypeInfo pnv_chip_info = {
 734     .name          = TYPE_PNV_CHIP,
 735     .parent        = TYPE_SYS_BUS_DEVICE,
 736     .class_init    = pnv_chip_class_init,
 737     .instance_init = pnv_chip_init,
 738     .class_size    = sizeof(PnvChipClass),
 739     .abstract      = true,
 740 };
 741
 742 static PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
 743 {
 744     CPUState *cs;
 745
 746     CPU_FOREACH(cs) {
 747         PowerPCCPU *cpu = POWERPC_CPU(cs);
 748         CPUPPCState *env = &cpu->env;
 749
 750         if (env->spr_cb[SPR_PIR].default_value == pir) {
 751             return cpu;
 752         }
 753     }
 754
 755     return NULL;
 756 }
 757
 758 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
 759 {
 760     PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
 761
 762     return cpu ? ICP(cpu->intc) : NULL;
 763 }
 764
 765 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
 766                               void *opaque, Error **errp)
 767 {
 768     visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp);
 769 }
 770
 771 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
 772                               void *opaque, Error **errp)
 773 {
 774     PnvMachineState *pnv = POWERNV_MACHINE(obj);
 775     uint32_t num_chips;
 776     Error *local_err = NULL;
 777
 778     visit_type_uint32(v, name, &num_chips, &local_err);
 779     if (local_err) {
 780         error_propagate(errp, local_err);
 781         return;
 782     }
 783
 784     /*
 785      * TODO: should we decide on how many chips we can create based
 786      * on #cores and Venice vs. Murano vs. Naples chip type etc...,
 787      */
 788     if (!is_power_of_2(num_chips) || num_chips > 4) {
 789         error_setg(errp, "invalid number of chips: '%d'", num_chips);
 790         return;
 791     }
 792
 793     pnv->num_chips = num_chips;
 794 }
 795
 796 static void powernv_machine_initfn(Object *obj)
 797 {
 798     PnvMachineState *pnv = POWERNV_MACHINE(obj);
 799     pnv->num_chips = 1;
 800 }
 801
 802 static void powernv_machine_class_props_init(ObjectClass *oc)
 803 {
 804     object_class_property_add(oc, "num-chips", "uint32_t",
 805                               pnv_get_num_chips, pnv_set_num_chips,
 806                               NULL, NULL, NULL);
 807     object_class_property_set_description(oc, "num-chips",
 808                               "Specifies the number of processor chips",
 809                               NULL);
 810 }
 811
 812 static void powernv_machine_class_init(ObjectClass *oc, void *data)
 813 {
 814     MachineClass *mc = MACHINE_CLASS(oc);
 815     XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
 816
 817     mc->desc = "IBM PowerNV (Non-Virtualized)";
 818     mc->init = ppc_powernv_init;
 819     mc->reset = ppc_powernv_reset;
 820     mc->max_cpus = MAX_CPUS;
 821     mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
 822                                       * storage */
 823     mc->no_parallel = 1;
 824     mc->default_boot_order = NULL;
 825     mc->default_ram_size = 1 * G_BYTE;
 826     xic->icp_get = pnv_icp_get;
 827
 828     powernv_machine_class_props_init(oc);
 829 }
 830
 831 static const TypeInfo powernv_machine_info = {
 832     .name          = TYPE_POWERNV_MACHINE,
 833     .parent        = TYPE_MACHINE,
 834     .instance_size = sizeof(PnvMachineState),
 835     .instance_init = powernv_machine_initfn,
 836     .class_init    = powernv_machine_class_init,
 837     .interfaces = (InterfaceInfo[]) {
 838         { TYPE_XICS_FABRIC },
 839         { },
 840     },
 841 };
 842
 843 static void powernv_machine_register_types(void)
 844 {
 845     type_register_static(&powernv_machine_info);
 846     type_register_static(&pnv_chip_info);
 847     type_register_static(&pnv_chip_power8e_info);
 848     type_register_static(&pnv_chip_power8_info);
 849     type_register_static(&pnv_chip_power8nvl_info);
 850     type_register_static(&pnv_chip_power9_info);
 851 }
 852
 853 type_init(powernv_machine_register_types)