4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
7 * Copyright 2016 IBM Corp.
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
13 #include "qemu/osdep.h"
14 #include "qemu/units.h"
15 #include "qapi/error.h"
16 #include "hw/misc/unimp.h"
17 #include "hw/arm/aspeed_soc.h"
18 #include "hw/char/serial.h"
19 #include "qemu/module.h"
20 #include "qemu/error-report.h"
21 #include "hw/i2c/aspeed_i2c.h"
23 #include "sysemu/sysemu.h"
25 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
27 static const hwaddr aspeed_soc_ast2400_memmap
[] = {
28 [ASPEED_DEV_IOMEM
] = 0x1E600000,
29 [ASPEED_DEV_FMC
] = 0x1E620000,
30 [ASPEED_DEV_SPI1
] = 0x1E630000,
31 [ASPEED_DEV_EHCI1
] = 0x1E6A1000,
32 [ASPEED_DEV_VIC
] = 0x1E6C0000,
33 [ASPEED_DEV_SDMC
] = 0x1E6E0000,
34 [ASPEED_DEV_SCU
] = 0x1E6E2000,
35 [ASPEED_DEV_HACE
] = 0x1E6E3000,
36 [ASPEED_DEV_XDMA
] = 0x1E6E7000,
37 [ASPEED_DEV_VIDEO
] = 0x1E700000,
38 [ASPEED_DEV_ADC
] = 0x1E6E9000,
39 [ASPEED_DEV_SRAM
] = 0x1E720000,
40 [ASPEED_DEV_SDHCI
] = 0x1E740000,
41 [ASPEED_DEV_GPIO
] = 0x1E780000,
42 [ASPEED_DEV_RTC
] = 0x1E781000,
43 [ASPEED_DEV_TIMER1
] = 0x1E782000,
44 [ASPEED_DEV_WDT
] = 0x1E785000,
45 [ASPEED_DEV_PWM
] = 0x1E786000,
46 [ASPEED_DEV_LPC
] = 0x1E789000,
47 [ASPEED_DEV_IBT
] = 0x1E789140,
48 [ASPEED_DEV_I2C
] = 0x1E78A000,
49 [ASPEED_DEV_ETH1
] = 0x1E660000,
50 [ASPEED_DEV_ETH2
] = 0x1E680000,
51 [ASPEED_DEV_UART1
] = 0x1E783000,
52 [ASPEED_DEV_UART2
] = 0x1E78D000,
53 [ASPEED_DEV_UART3
] = 0x1E78E000,
54 [ASPEED_DEV_UART4
] = 0x1E78F000,
55 [ASPEED_DEV_UART5
] = 0x1E784000,
56 [ASPEED_DEV_VUART
] = 0x1E787000,
57 [ASPEED_DEV_SDRAM
] = 0x40000000,
60 static const hwaddr aspeed_soc_ast2500_memmap
[] = {
61 [ASPEED_DEV_IOMEM
] = 0x1E600000,
62 [ASPEED_DEV_FMC
] = 0x1E620000,
63 [ASPEED_DEV_SPI1
] = 0x1E630000,
64 [ASPEED_DEV_SPI2
] = 0x1E631000,
65 [ASPEED_DEV_EHCI1
] = 0x1E6A1000,
66 [ASPEED_DEV_EHCI2
] = 0x1E6A3000,
67 [ASPEED_DEV_VIC
] = 0x1E6C0000,
68 [ASPEED_DEV_SDMC
] = 0x1E6E0000,
69 [ASPEED_DEV_SCU
] = 0x1E6E2000,
70 [ASPEED_DEV_HACE
] = 0x1E6E3000,
71 [ASPEED_DEV_XDMA
] = 0x1E6E7000,
72 [ASPEED_DEV_ADC
] = 0x1E6E9000,
73 [ASPEED_DEV_VIDEO
] = 0x1E700000,
74 [ASPEED_DEV_SRAM
] = 0x1E720000,
75 [ASPEED_DEV_SDHCI
] = 0x1E740000,
76 [ASPEED_DEV_GPIO
] = 0x1E780000,
77 [ASPEED_DEV_RTC
] = 0x1E781000,
78 [ASPEED_DEV_TIMER1
] = 0x1E782000,
79 [ASPEED_DEV_WDT
] = 0x1E785000,
80 [ASPEED_DEV_PWM
] = 0x1E786000,
81 [ASPEED_DEV_LPC
] = 0x1E789000,
82 [ASPEED_DEV_IBT
] = 0x1E789140,
83 [ASPEED_DEV_I2C
] = 0x1E78A000,
84 [ASPEED_DEV_ETH1
] = 0x1E660000,
85 [ASPEED_DEV_ETH2
] = 0x1E680000,
86 [ASPEED_DEV_UART1
] = 0x1E783000,
87 [ASPEED_DEV_UART2
] = 0x1E78D000,
88 [ASPEED_DEV_UART3
] = 0x1E78E000,
89 [ASPEED_DEV_UART4
] = 0x1E78F000,
90 [ASPEED_DEV_UART5
] = 0x1E784000,
91 [ASPEED_DEV_VUART
] = 0x1E787000,
92 [ASPEED_DEV_SDRAM
] = 0x80000000,
95 static const int aspeed_soc_ast2400_irqmap
[] = {
96 [ASPEED_DEV_UART1
] = 9,
97 [ASPEED_DEV_UART2
] = 32,
98 [ASPEED_DEV_UART3
] = 33,
99 [ASPEED_DEV_UART4
] = 34,
100 [ASPEED_DEV_UART5
] = 10,
101 [ASPEED_DEV_VUART
] = 8,
102 [ASPEED_DEV_FMC
] = 19,
103 [ASPEED_DEV_EHCI1
] = 5,
104 [ASPEED_DEV_EHCI2
] = 13,
105 [ASPEED_DEV_SDMC
] = 0,
106 [ASPEED_DEV_SCU
] = 21,
107 [ASPEED_DEV_ADC
] = 31,
108 [ASPEED_DEV_GPIO
] = 20,
109 [ASPEED_DEV_RTC
] = 22,
110 [ASPEED_DEV_TIMER1
] = 16,
111 [ASPEED_DEV_TIMER2
] = 17,
112 [ASPEED_DEV_TIMER3
] = 18,
113 [ASPEED_DEV_TIMER4
] = 35,
114 [ASPEED_DEV_TIMER5
] = 36,
115 [ASPEED_DEV_TIMER6
] = 37,
116 [ASPEED_DEV_TIMER7
] = 38,
117 [ASPEED_DEV_TIMER8
] = 39,
118 [ASPEED_DEV_WDT
] = 27,
119 [ASPEED_DEV_PWM
] = 28,
120 [ASPEED_DEV_LPC
] = 8,
121 [ASPEED_DEV_I2C
] = 12,
122 [ASPEED_DEV_ETH1
] = 2,
123 [ASPEED_DEV_ETH2
] = 3,
124 [ASPEED_DEV_XDMA
] = 6,
125 [ASPEED_DEV_SDHCI
] = 26,
126 [ASPEED_DEV_HACE
] = 4,
129 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
131 static qemu_irq
aspeed_soc_ast2400_get_irq(AspeedSoCState
*s
, int dev
)
133 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
135 return qdev_get_gpio_in(DEVICE(&s
->vic
), sc
->irqmap
[dev
]);
138 static void aspeed_soc_init(Object
*obj
)
140 AspeedSoCState
*s
= ASPEED_SOC(obj
);
141 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
146 if (sscanf(sc
->name
, "%7s", socname
) != 1) {
147 g_assert_not_reached();
150 for (i
= 0; i
< sc
->num_cpus
; i
++) {
151 object_initialize_child(obj
, "cpu[*]", &s
->cpu
[i
], sc
->cpu_type
);
154 snprintf(typename
, sizeof(typename
), "aspeed.scu-%s", socname
);
155 object_initialize_child(obj
, "scu", &s
->scu
, typename
);
156 qdev_prop_set_uint32(DEVICE(&s
->scu
), "silicon-rev",
158 object_property_add_alias(obj
, "hw-strap1", OBJECT(&s
->scu
),
160 object_property_add_alias(obj
, "hw-strap2", OBJECT(&s
->scu
),
162 object_property_add_alias(obj
, "hw-prot-key", OBJECT(&s
->scu
),
165 object_initialize_child(obj
, "vic", &s
->vic
, TYPE_ASPEED_VIC
);
167 object_initialize_child(obj
, "rtc", &s
->rtc
, TYPE_ASPEED_RTC
);
169 snprintf(typename
, sizeof(typename
), "aspeed.timer-%s", socname
);
170 object_initialize_child(obj
, "timerctrl", &s
->timerctrl
, typename
);
172 snprintf(typename
, sizeof(typename
), "aspeed.adc-%s", socname
);
173 object_initialize_child(obj
, "adc", &s
->adc
, typename
);
175 snprintf(typename
, sizeof(typename
), "aspeed.i2c-%s", socname
);
176 object_initialize_child(obj
, "i2c", &s
->i2c
, typename
);
178 snprintf(typename
, sizeof(typename
), "aspeed.fmc-%s", socname
);
179 object_initialize_child(obj
, "fmc", &s
->fmc
, typename
);
181 for (i
= 0; i
< sc
->spis_num
; i
++) {
182 snprintf(typename
, sizeof(typename
), "aspeed.spi%d-%s", i
+ 1, socname
);
183 object_initialize_child(obj
, "spi[*]", &s
->spi
[i
], typename
);
186 for (i
= 0; i
< sc
->ehcis_num
; i
++) {
187 object_initialize_child(obj
, "ehci[*]", &s
->ehci
[i
],
191 snprintf(typename
, sizeof(typename
), "aspeed.sdmc-%s", socname
);
192 object_initialize_child(obj
, "sdmc", &s
->sdmc
, typename
);
193 object_property_add_alias(obj
, "ram-size", OBJECT(&s
->sdmc
),
196 for (i
= 0; i
< sc
->wdts_num
; i
++) {
197 snprintf(typename
, sizeof(typename
), "aspeed.wdt-%s", socname
);
198 object_initialize_child(obj
, "wdt[*]", &s
->wdt
[i
], typename
);
201 for (i
= 0; i
< sc
->macs_num
; i
++) {
202 object_initialize_child(obj
, "ftgmac100[*]", &s
->ftgmac100
[i
],
206 snprintf(typename
, sizeof(typename
), TYPE_ASPEED_XDMA
"-%s", socname
);
207 object_initialize_child(obj
, "xdma", &s
->xdma
, typename
);
209 snprintf(typename
, sizeof(typename
), "aspeed.gpio-%s", socname
);
210 object_initialize_child(obj
, "gpio", &s
->gpio
, typename
);
212 object_initialize_child(obj
, "sdc", &s
->sdhci
, TYPE_ASPEED_SDHCI
);
214 object_property_set_int(OBJECT(&s
->sdhci
), "num-slots", 2, &error_abort
);
216 /* Init sd card slot class here so that they're under the correct parent */
217 for (i
= 0; i
< ASPEED_SDHCI_NUM_SLOTS
; ++i
) {
218 object_initialize_child(obj
, "sdhci[*]", &s
->sdhci
.slots
[i
],
222 object_initialize_child(obj
, "lpc", &s
->lpc
, TYPE_ASPEED_LPC
);
224 snprintf(typename
, sizeof(typename
), "aspeed.hace-%s", socname
);
225 object_initialize_child(obj
, "hace", &s
->hace
, typename
);
228 static void aspeed_soc_realize(DeviceState
*dev
, Error
**errp
)
231 AspeedSoCState
*s
= ASPEED_SOC(dev
);
232 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
236 create_unimplemented_device("aspeed_soc.io", sc
->memmap
[ASPEED_DEV_IOMEM
],
237 ASPEED_SOC_IOMEM_SIZE
);
239 /* Video engine stub */
240 create_unimplemented_device("aspeed.video", sc
->memmap
[ASPEED_DEV_VIDEO
],
244 for (i
= 0; i
< sc
->num_cpus
; i
++) {
245 if (!qdev_realize(DEVICE(&s
->cpu
[i
]), NULL
, errp
)) {
251 memory_region_init_ram(&s
->sram
, OBJECT(dev
), "aspeed.sram",
252 sc
->sram_size
, &err
);
254 error_propagate(errp
, err
);
257 memory_region_add_subregion(get_system_memory(),
258 sc
->memmap
[ASPEED_DEV_SRAM
], &s
->sram
);
261 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->scu
), errp
)) {
264 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->scu
), 0, sc
->memmap
[ASPEED_DEV_SCU
]);
267 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->vic
), errp
)) {
270 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->vic
), 0, sc
->memmap
[ASPEED_DEV_VIC
]);
271 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 0,
272 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_IRQ
));
273 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 1,
274 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_FIQ
));
277 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->rtc
), errp
)) {
280 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->rtc
), 0, sc
->memmap
[ASPEED_DEV_RTC
]);
281 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->rtc
), 0,
282 aspeed_soc_get_irq(s
, ASPEED_DEV_RTC
));
285 object_property_set_link(OBJECT(&s
->timerctrl
), "scu", OBJECT(&s
->scu
),
287 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->timerctrl
), errp
)) {
290 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->timerctrl
), 0,
291 sc
->memmap
[ASPEED_DEV_TIMER1
]);
292 for (i
= 0; i
< ASPEED_TIMER_NR_TIMERS
; i
++) {
293 qemu_irq irq
= aspeed_soc_get_irq(s
, ASPEED_DEV_TIMER1
+ i
);
294 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timerctrl
), i
, irq
);
298 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->adc
), errp
)) {
301 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->adc
), 0, sc
->memmap
[ASPEED_DEV_ADC
]);
302 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->adc
), 0,
303 aspeed_soc_get_irq(s
, ASPEED_DEV_ADC
));
306 aspeed_soc_uart_init(s
);
309 object_property_set_link(OBJECT(&s
->i2c
), "dram", OBJECT(s
->dram_mr
),
311 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->i2c
), errp
)) {
314 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
), 0, sc
->memmap
[ASPEED_DEV_I2C
]);
315 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
), 0,
316 aspeed_soc_get_irq(s
, ASPEED_DEV_I2C
));
318 /* FMC, The number of CS is set at the board level */
319 object_property_set_link(OBJECT(&s
->fmc
), "dram", OBJECT(s
->dram_mr
),
321 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->fmc
), errp
)) {
324 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 0, sc
->memmap
[ASPEED_DEV_FMC
]);
325 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 1,
326 ASPEED_SMC_GET_CLASS(&s
->fmc
)->flash_window_base
);
327 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->fmc
), 0,
328 aspeed_soc_get_irq(s
, ASPEED_DEV_FMC
));
331 for (i
= 0; i
< sc
->spis_num
; i
++) {
332 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->spi
[i
]), errp
)) {
335 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
336 sc
->memmap
[ASPEED_DEV_SPI1
+ i
]);
337 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 1,
338 ASPEED_SMC_GET_CLASS(&s
->spi
[i
])->flash_window_base
);
342 for (i
= 0; i
< sc
->ehcis_num
; i
++) {
343 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->ehci
[i
]), errp
)) {
346 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ehci
[i
]), 0,
347 sc
->memmap
[ASPEED_DEV_EHCI1
+ i
]);
348 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ehci
[i
]), 0,
349 aspeed_soc_get_irq(s
, ASPEED_DEV_EHCI1
+ i
));
352 /* SDMC - SDRAM Memory Controller */
353 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sdmc
), errp
)) {
356 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdmc
), 0, sc
->memmap
[ASPEED_DEV_SDMC
]);
359 for (i
= 0; i
< sc
->wdts_num
; i
++) {
360 AspeedWDTClass
*awc
= ASPEED_WDT_GET_CLASS(&s
->wdt
[i
]);
362 object_property_set_link(OBJECT(&s
->wdt
[i
]), "scu", OBJECT(&s
->scu
),
364 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->wdt
[i
]), errp
)) {
367 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0,
368 sc
->memmap
[ASPEED_DEV_WDT
] + i
* awc
->offset
);
372 if (!aspeed_soc_dram_init(s
, errp
)) {
377 for (i
= 0; i
< sc
->macs_num
; i
++) {
378 object_property_set_bool(OBJECT(&s
->ftgmac100
[i
]), "aspeed", true,
380 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), errp
)) {
383 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
384 sc
->memmap
[ASPEED_DEV_ETH1
+ i
]);
385 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
386 aspeed_soc_get_irq(s
, ASPEED_DEV_ETH1
+ i
));
390 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->xdma
), errp
)) {
393 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->xdma
), 0,
394 sc
->memmap
[ASPEED_DEV_XDMA
]);
395 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->xdma
), 0,
396 aspeed_soc_get_irq(s
, ASPEED_DEV_XDMA
));
399 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->gpio
), errp
)) {
402 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
), 0, sc
->memmap
[ASPEED_DEV_GPIO
]);
403 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
), 0,
404 aspeed_soc_get_irq(s
, ASPEED_DEV_GPIO
));
407 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sdhci
), errp
)) {
410 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdhci
), 0,
411 sc
->memmap
[ASPEED_DEV_SDHCI
]);
412 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sdhci
), 0,
413 aspeed_soc_get_irq(s
, ASPEED_DEV_SDHCI
));
416 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->lpc
), errp
)) {
419 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->lpc
), 0, sc
->memmap
[ASPEED_DEV_LPC
]);
421 /* Connect the LPC IRQ to the VIC */
422 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 0,
423 aspeed_soc_get_irq(s
, ASPEED_DEV_LPC
));
426 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
427 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by
428 * contrast, on the AST2600, the subdevice IRQs are connected straight to
431 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output
432 * to the VIC is at offset 0.
434 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_1
,
435 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_1
));
437 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_2
,
438 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_2
));
440 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_3
,
441 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_3
));
443 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_4
,
444 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_4
));
447 object_property_set_link(OBJECT(&s
->hace
), "dram", OBJECT(s
->dram_mr
),
449 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->hace
), errp
)) {
452 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->hace
), 0, sc
->memmap
[ASPEED_DEV_HACE
]);
453 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->hace
), 0,
454 aspeed_soc_get_irq(s
, ASPEED_DEV_HACE
));
456 static Property aspeed_soc_properties
[] = {
457 DEFINE_PROP_LINK("dram", AspeedSoCState
, dram_mr
, TYPE_MEMORY_REGION
,
459 DEFINE_PROP_UINT32("uart-default", AspeedSoCState
, uart_default
,
461 DEFINE_PROP_END_OF_LIST(),
464 static void aspeed_soc_class_init(ObjectClass
*oc
, void *data
)
466 DeviceClass
*dc
= DEVICE_CLASS(oc
);
468 dc
->realize
= aspeed_soc_realize
;
469 /* Reason: Uses serial_hds and nd_table in realize() directly */
470 dc
->user_creatable
= false;
471 device_class_set_props(dc
, aspeed_soc_properties
);
474 static const TypeInfo aspeed_soc_type_info
= {
475 .name
= TYPE_ASPEED_SOC
,
476 .parent
= TYPE_DEVICE
,
477 .instance_size
= sizeof(AspeedSoCState
),
478 .class_size
= sizeof(AspeedSoCClass
),
479 .class_init
= aspeed_soc_class_init
,
483 static void aspeed_soc_ast2400_class_init(ObjectClass
*oc
, void *data
)
485 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
487 sc
->name
= "ast2400-a1";
488 sc
->cpu_type
= ARM_CPU_TYPE_NAME("arm926");
489 sc
->silicon_rev
= AST2400_A1_SILICON_REV
;
490 sc
->sram_size
= 0x8000;
496 sc
->irqmap
= aspeed_soc_ast2400_irqmap
;
497 sc
->memmap
= aspeed_soc_ast2400_memmap
;
499 sc
->get_irq
= aspeed_soc_ast2400_get_irq
;
502 static const TypeInfo aspeed_soc_ast2400_type_info
= {
503 .name
= "ast2400-a1",
504 .parent
= TYPE_ASPEED_SOC
,
505 .instance_init
= aspeed_soc_init
,
506 .instance_size
= sizeof(AspeedSoCState
),
507 .class_init
= aspeed_soc_ast2400_class_init
,
510 static void aspeed_soc_ast2500_class_init(ObjectClass
*oc
, void *data
)
512 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
514 sc
->name
= "ast2500-a1";
515 sc
->cpu_type
= ARM_CPU_TYPE_NAME("arm1176");
516 sc
->silicon_rev
= AST2500_A1_SILICON_REV
;
517 sc
->sram_size
= 0x9000;
523 sc
->irqmap
= aspeed_soc_ast2500_irqmap
;
524 sc
->memmap
= aspeed_soc_ast2500_memmap
;
526 sc
->get_irq
= aspeed_soc_ast2400_get_irq
;
529 static const TypeInfo aspeed_soc_ast2500_type_info
= {
530 .name
= "ast2500-a1",
531 .parent
= TYPE_ASPEED_SOC
,
532 .instance_init
= aspeed_soc_init
,
533 .instance_size
= sizeof(AspeedSoCState
),
534 .class_init
= aspeed_soc_ast2500_class_init
,
536 static void aspeed_soc_register_types(void)
538 type_register_static(&aspeed_soc_type_info
);
539 type_register_static(&aspeed_soc_ast2400_type_info
);
540 type_register_static(&aspeed_soc_ast2500_type_info
);
543 type_init(aspeed_soc_register_types
);
545 qemu_irq
aspeed_soc_get_irq(AspeedSoCState
*s
, int dev
)
547 return ASPEED_SOC_GET_CLASS(s
)->get_irq(s
, dev
);
550 void aspeed_soc_uart_init(AspeedSoCState
*s
)
552 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
555 /* Attach an 8250 to the IO space as our UART */
556 serial_mm_init(get_system_memory(), sc
->memmap
[s
->uart_default
], 2,
557 aspeed_soc_get_irq(s
, s
->uart_default
), 38400,
558 serial_hd(0), DEVICE_LITTLE_ENDIAN
);
559 for (i
= 1, uart
= ASPEED_DEV_UART1
; i
< sc
->uarts_num
; i
++, uart
++) {
560 if (uart
== s
->uart_default
) {
563 serial_mm_init(get_system_memory(), sc
->memmap
[uart
], 2,
564 aspeed_soc_get_irq(s
, uart
), 38400,
565 serial_hd(i
), DEVICE_LITTLE_ENDIAN
);
570 * SDMC should be realized first to get correct RAM size and max size
573 bool aspeed_soc_dram_init(AspeedSoCState
*s
, Error
**errp
)
575 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
576 ram_addr_t ram_size
, max_ram_size
;
578 ram_size
= object_property_get_uint(OBJECT(&s
->sdmc
), "ram-size",
580 max_ram_size
= object_property_get_uint(OBJECT(&s
->sdmc
), "max-ram-size",
583 memory_region_init(&s
->dram_container
, OBJECT(s
), "ram-container",
585 memory_region_add_subregion(&s
->dram_container
, 0, s
->dram_mr
);
588 * Add a memory region beyond the RAM region to let firmwares scan
589 * the address space with load/store and guess how much RAM the
592 if (ram_size
< max_ram_size
) {
593 DeviceState
*dev
= qdev_new(TYPE_UNIMPLEMENTED_DEVICE
);
595 qdev_prop_set_string(dev
, "name", "ram-empty");
596 qdev_prop_set_uint64(dev
, "size", max_ram_size
- ram_size
);
597 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), errp
)) {
601 memory_region_add_subregion_overlap(&s
->dram_container
, ram_size
,
602 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0), -1000);
605 memory_region_add_subregion(get_system_memory(),
606 sc
->memmap
[ASPEED_DEV_SDRAM
], &s
->dram_container
);